RT8108

5V to 12V Single Synchronous Buck PWM Controller

General Description Features
The RT8108 series are single-phase synchronous buck z Single IC Supply Voltage ( 5V to 12V)
PWM DC/DC controllers designed to drive two z Drive Two N-MOSFETs
N-MOSFETs. They provide a highly accurate, z Fixed Operating Frequency at 200kHz, 300kHz and
programmable output voltage precisely regulated to low 500kHz
voltage requirement with an internal 0.6V or 0.8V reference. z Voltage Mode PWM Control with External
Feedback Loop Compensation
The RT8108 series use a single feedback loop voltage mode
z Over Current Protection by Sensing MOSFET RDS(ON)
PWM control for fast transient response. The high driving
z Hardware Pin for On/Off Control
capability makes it suitable for large output current
z Full 0 to 90% Duty Cycle
applications. An oscillator with fixed frequency 200kHz /
z Fast Transient Response
300kHz / 500kHz reduces the component size of the
z RoHS Compliant and Halogen Free
external inductor and capacitor for saving PCB board area
and cost.
Applications
The RT8108 series integrate complete protection functions
z Mother Boards and Desktop Servers
such as OCP, OVP and OTP UVP into SOP-8 and SOP-8
z Graphic Cards
(Exposed Pad) surface mount packages.
z Switching Power Supply
z Generic DC/DC Power Regulator
Ordering Information
RT8108
Pin Configurations
Package Type
S : SOP-8 (TOP VIEW)
SP : SOP-8 (Exposed Pad-Option 1)
BOOT 8 PHASE
Lead Plating System UGATE 2 7 COMP/SD
G : Green (Halogen Free and Pb Free) GND 3 6 FB
Frequency / VREF Options LGATE/OCSET 4 5 VCC
A : 300k / 0.6V
B : 300k / 0.8V SOP-8
C : 200k / 0.6V
D : 200k / 0.8V BOOT 8 PHASE
E : 500k / 0.6V UGATE 2 7 COMP/SD
F : 500k / 0.8V GND
GND 3 6 FB
9
Note : LGATE/OCSET 4 5 VCC
Richtek products are :
` RoHS compliant and compatible with the current require- SOP-8 (Exposed Pad)
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.

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RT8108
Typical Application Circuit
VIN
3.3V to 12V

CHF CBULK
RT8108x
VCC 5 VCC RBOOT CBOOT
5V or 12V BOOT 1
CDCPL 2
UGATE LOUT
RUGATE
8
7 COMP PHASE VOUT
/SD
LGATE/ 4 R COUT
RF OCSET
6
C1 FB 3
GND C
EN CF RS

ROFFSET ROCSET

Functional Pin Description

Pin No.
SOP-8 Pin Nam e Pin Function
SOP-8 (Exposed Pad)
Bootstrap Supply Pin for the Upper Gate Driver. Connect the
1 1 BOOT
bootstrap capacitor between BOOT and PHASE pins.
Upper Gate Driver Output. Connect this pin to gate of the high side
2 2 UGATE
power N-MOSFET.
Both Signal and Power Ground for the IC. Tie this pin directly to the
3, low-side MOSFET source and ground plane with the lowest
3 GND
9 (Exposed Pad) impedance. The exposed pad must be soldered to a large PCB
and connected to GND for maximum power dissipation.
Low-Side Gate Drive. It also acts as over current setup pin by
4 4 LGATE/OCSET
adjusting the resistor connecting to GND.
Connect this Pin to a Well-Decoupled 5V or 12V Bias Supply. It is
5 5 VCC
also the positive supply for the lower gate driver.
6 6 FB Feedback of the Output Voltage.
7 7 COMP/SD Feedback Compensation and Enable/Shutdown Control Pin.
Connect this pin to the source of the upper MOSFET and the drain
8 8 PHASE
of the lower MOSFET.

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 RT8108
Function Block Diagram
VCC

Delay
5V
Sample DBOOT
- POR and Internal
and Hold BOOT
Soft-Start Regulator
+
OC
IOCSET Comparator UGATE
5V int.

VREF -1 PHASE
(0.6V / 0.8V)
PWM
Comparator INHIBIT
+ Gate Control
EA +
FB - Logic
- PWM
0.2V + DIS
VCC
- DIS
LGATE/OCSET
COMP/SD Oscillator
GND
Fixed 200kHz / 300kHz / 500kHz

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RT8108
Absolute Maximum Ratings (Note 1)
z Supply Input Voltage, VCC ------------------------------------------------------------------------------ 16V
z BOOT to PHASE ----------------------------------------------------------------------------------------- 15V
z BOOT to GND
DC ------------------------------------------------------------------------------------------------------------ −0.3V to VCC + 15V
<200ns ------------------------------------------------------------------------------------------------------ −0.3V to 42V
z PHASE to GND
DC ------------------------------------------------------------------------------------------------------------ −0.5V to 15V
<200ns ------------------------------------------------------------------------------------------------------ −5V to 30V
z UGATE Voltage ------------------------------------------------------------------------------------------- VPHASE − 0.3V to VBOOT + 0.3V
<200ns ------------------------------------------------------------------------------------------------------ VPHASE − 5V to VBOOT + 5V
z LGATE Voltage -------------------------------------------------------------------------------------------- GND − 0.3V to VCC + 0.3V
<200ns ------------------------------------------------------------------------------------------------------ GND− 5V to VCC + 5V
z Other Input or Output Voltages ------------------------------------------------------------------------ GND − 0.3V to 7V
z Power Dissipation, PD @ TA = 25°C
SOP-8 ------------------------------------------------------------------------------------------------------- 0.909W
SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------- 1.333W
z Package Thermal Resistance (Note 2)
SOP-8, θJA ------------------------------------------------------------------------------------------------- 110°C/W
SOP-8 (Exposed Pad), θJA ----------------------------------------------------------------------------- 75°C/W
SOP-8 (Exposed Pad), θJC ---------------------------------------------------------------------------- 28°C/W
z Junction Temperature ------------------------------------------------------------------------------------ 150°C
z Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------- 260°C
z Storage Temperature Range --------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)

z Supply Input Voltage, VCC ------------------------------------------------------------------------------ 5V ± 5%, 12V ± 10%
z Junction Temperature Range --------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range --------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics
(VCC = 12V, TA = 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

Supply Input
Supply Input Voltage V CC 4.75 -- 13.2 V
Supply Current ICC UGATE, LGATE Open -- 2.5 10 mA
Shutdown Current ISHDN UGATE, LGATE Open -- 2 -- mA
Power-On Reset
POR Threshold V CC_RTH VCC Rising 3.8 4 4.3 V
Power On Reset Hysteresis V CC_HYS -- 0.4 -- V
To be continued
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 RT8108
Parameter Symbol Test Conditions Min Typ Max Unit
Oscillator
RT8108A/B 250 300 350
PWM
RT8108C/D F SW 170 200 230 kHz
Frequency
RT8108E/F 425 500 575
Ramp Amplitude ΔVOSC -- 1.5 -- VP-P
Reference

Reference RT8108A/C/E 0.594 0.6 0.606

V REF V
Voltage RT8108B/D/F 0.792 0.8 0.808
PWM Controller
Open Loop DC Gain AO -- 88 -- dB
Gain Bandwidth GBW -- 15 -- MHz
fOSC = 200kHz / 300kHz -- 92 -- %
Maximum Duty DMAX
fOSC = 500kHz -- 85 -- %
PWM Controller Gate Driver
Upper Gate Source IUGATEsr VBOOT − V PHASE = 12V 1 1.2 -- A
Upper Gate Sink RUGATEsk VUGATE − VPHASE = 0.1V, I = 50mA -- 2.25 4 Ω
Lower Gate Source ILGATEsr VCC = 12V 1 1.2 -- A
Lower Gate Sink RLGATEsk VLGATE = 0.1V, I = 50mA -- 1 2 Ω
Protection
Under Voltage Protection (UVP) V FB_UVP Sweep VFB 68 75 82 %
Over Voltage Protection V FB_OVP Sweep VFB (After POR) 115 125 130 %
Over Voltage Protection V pre_OVP Sweep VFB (Before POR) -- 130 -- %
LGATE OC Setting Current IOCSET 22 25 28 μA
Over Temperature Protection T OTP -- 165 -- °C
RT8108A/B 1 3 5
Soft-Start
RT8108C/D T SS Measure FB from 10% to 90% 1 4 7 ms
Interval
RT8108E/F 0.7 2.5 4
COMP/SD Shutdown Threshold V SD -- -- 0.2 V

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers, 2S2P)
of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
.

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RT8108
Typical Operating Characteristics
Efficiency vs. Load Current Output Voltage vs. Load Current
100 1.210
90
80 1.206

Output Voltage (V)

70
Efficiency (%)

60 1.202
50
40 1.198
30
20 1.194
10
VIN = VCC = 12V VIN = VCC = 12V
0 1.190
0 5 10 15 20 25 30 0 5 10 15 20 25
Load Current (A) Load Current (A)

Reference Voltage vs. Temperature Frequency vs. Temperature

0.605 400

0.604
Reference Voltage (V)

350
0.603
Frequency (kHz)11

0.602 300
0.601

0.600 250

0.599
200
0.598
VIN = VCC = 12V, No Load VIN = VCC = 12V, No Load
0.597 150
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

Power On from VIN Power Off from VIN

VOUT VOUT
(1V/Div) (1V/Div)

VIN VIN
(10V/Div) (10V/Div)

V CC V CC
(10V/Div) (10V/Div)
UGATE UGATE
(20V/Div) (20V/Div)
VIN = VCC = 12V, No Load VIN = VCC = 12V, No Load

Time (4ms/Div) Time (100ms/Div)

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 RT8108

Power On from COMP/SD Power Off from COMP/SD

VCOMP
VCOMP (1V/Div)
(1V/Div)
VOUT
(1V/Div) VOUT
(1V/Div)

UGATE UGATE
(20V/Div) (20V/Div)

LGATE LGATE
(10V/Div) (10V/Div)
VIN = VCC = 12V, No Load VIN = VCC = 12V, No Load
Time (1ms/Div) Time (20ms/Div)

Load Transient Response Load Transient Response

VIN = VCC = 12V, ILOAD = 0A to 15A VIN = VCC = 12V, ILOAD = 15A to 0A
L = 1uH, COUT = 1640uF L = 1uH, COUT = 1640uF

VOUT_ac VOUT_ac
(50mV/Div) (50mV/Div)

UGATE UGATE
(20V/Div) (20V/Div)

I LOAD I LOAD
(10A/Div) (10A/Div)

Time (10μs/Div) Time (10μs/Div)

Over Current Protection Over Voltage Protection

IL VFB
(10A/Div) (1V/Div)

VOUT VOUT
(1V/Div) (1V/Div)

UGATE
UGATE (20V/Div)
(20V/Div)

LGATE LGATE
(10V/Div) (10V/Div)
VCC = 12V, IOCSET = 15A VIN = VCC = 12V, No Load
Time (10ms/Div) Time (20ms/Div)

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RT8108
Application Information
Function Description voltage during the soft-start interval. After the internal soft-
The RT8108 series are single-phase synchronous buck start voltage exceeds the reference voltage, the FB voltage
PWM controllers with embedded MOSFET drivers. The no longer tracks the soft-start voltage but follows the
MOSFET drivers are designed with high-current driving reference voltage. Therefore, the duty cycle of thr UGATE
capability to support up to 12V+12V bootstrapped voltage signal at power up is limited and so does the input current.
for high efficiency power conversion. The RT8108 series
utilize voltage-mode control scheme, which is implemented Power-up with Pre-biased Voltage
with a voltage error amplifier to provide a simple control Generally, if the output voltage is not initially zero at power-
loop. A fixed frequency oscillator (200kHz/300kHz/500kHz, up, or the output capacitor is pre-charged, the voltage at
typical) is integrated to eliminate external component FB pin is not equal to zero. The controller will turn on the
count. The soft-start function is also integrated to eliminate low-side MOSFET to discharge the output capacitor, forcing
the external timing capacitor. The RT8108 series provide the feedback voltage to follow the reference voltage. Large
full protection functions to protect the load. The feedback current is then drawn from the output capacitor while
voltage at the FB pin is monitored for over-voltage protection discharging. The discharge current depends on the
and under-voltage protection. An internal 0.6V/0.8V inductance and the output capacitance. Output voltage may
reference allows the output voltage to be precisely regulated oscillate and be negative.
for low output voltage applications. An elaborately designed The negative output voltage could damage the load. The
control circuit allows the converter to power up with pre- RT8108 series implement elaborate control circuits to
biased output voltage to avoid negative voltage damage to prevent the negative voltage when the converter is powered-
the load. The RT8108 series use RDS(ON) current-sensing up with pre-biased voltage on the output capacitor. Figure
technique, which is lossless and cost-effective. Inductor 1 shows the waveform that converter is powered-up at no
current information is monitored by the voltage across load with pre-biased output voltage. The output voltage rises
RDS(ON) of the low-side MOSFET for over current protection. from its pre-charged initial value during soft-start without
being pulled down.
Power-up
The power on reset (POR) circuit monitors the supply
voltage of the controller (VCC). If VCC exceeds the POR VCOMP
rising threshold voltage, the controller is initiated. The (2V/Div)
controller sets the over current protection threshold prior
VOUT
to the beginning of soft start. If VCC falls below the POR (1V/Div)
falling threshold during normal operation, all MOSFETs
UGATE
stop switching and the controller is reset. The POR rising (20V/Div)
and falling threshold has a hysteresis to prevent noise-
LGATE
caused reset. (10V/Div)

Soft-start Time (1ms/Div)

The RT8108 series provide soft-start function internally. Figure 1. Power Up with Pre-Biased Output Voltage
The soft-start function is used to prevent the large inrush
current while the converter is powered-up. An internal COMP/SD Enable/Disable
current source charges the internal soft-start capacitor The COMP/SD pin can also be used to enable or to disable
such that the internal soft-start voltage ramps up in a the controller. Pull down COMP/SD pin below the shutdown
monotone. The FB voltage will track the internal soft-start level VSHDN can disable the controller. When the controller
is disabled, UGATE signal goes low first and then LGATE

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 RT8108
signal also goes low after a short delay time. In practical current sensing, the voltage across the low-side MOSFET
applications, connect a small signal MOFSET to is sampled and held after low-side MOSFET is turned on.
COMP/SD pin to pull down the COMP/SD voltage to This sampled and held voltage represents the inductor peak
implement the enable/disable function. current and is compared to the user-programmed protection
level.
Over Voltage Protection (OVP)
Once the inductor current exceeds the protection level,
The output voltage is scaled by the divider resistors and
OCP will be triggered. When the OCP is triggered, both
fed back to the FB pin. The voltage on the FB pin will be
UGATE and LGATE go low to stop the energy transferring
compared to the internal reference voltage VREF for voltage-
to the load. Like UVP, the OCP is a continuing hiccupped
related protection functions, including over voltage
protection. The soft start will be initiated again after a
protection and under voltage protection. If the FB voltage
specific period of time (4*Tss, typical). If OCP situation is
is higher than the OVP threshold during operation, OVP
not removed, controller will always try to restart.
will be triggered. When OVP is triggered, UGATE will go
low and LGATE will go high to discharge the output OCP Setting
capacitor. Once OVP is triggered, controller will be latched The RT8108 series employ an elaborate topology for OCP
unless VCC POR is detected again. setting, which eliminates controller pin count. Connect a
Besides, the RT8108 series also provide OVP even if VCC resistor from LGATE to GND to set the OCP level as shown
is below the POR threshold. This can protect the load in Figure 2.
even if the high-side MOSFET is shorted before the power- 5V
on-reset. If the FB voltage is higher than the OVP threshold
while VCC rises but not exceeds the POR threshold, OVP IOCSET
-1 PHASE
will be triggered. The LGATE signal will go high to discharge +
OC
-
the output capacitor.
Sample LGATE
& Hold
Under Voltage Protection (UVP) ROCSET
The voltage on the FB pin is also monitored for under voltage POR Delay
protection. If the FB voltage is lower than the UVP threshold
during normal operation, UVP will be triggered. When UVP Figure 2. OCP Setting
is triggered, both UGATE and LGATE go low. Unlike OVP,
When the VCC exceeds the POR threshold at power up,
UVP is not a latched protection. The controller will begin
LGATE is internally floating and enters tri-state. An internal
soft start again after a specific period of time (~40ms).
current source I OCSET then flows through R OCSET to
Furthermore, the controller will enter the hiccup mode and
determine the OCP threshold voltage. The voltage across
always try to restart if UVP situation is not removed. The
the ROCSET is stored as the over current level for OCP.
UVP is reset by detecting VCC POR again. Unlike OVP,
After that, the current source is switched off, and LGATE
the output voltage is monitored for UVP only after soft-
leaves the tri-state and prepared for the soft-start. Therefore,
start completes.
no extra pin is required to set the OCP threshold. The
Over Current Protection (OCP) internal current source IOC is only active for a short period
of time after VCC POR. The ROCSET can be determined
The RT8108 series sense output current through low-side
using the following equation.
MOSFET RDS(ON) for over current protection. When the
LGATE is turned on, the controller monitors voltage across RDS(ON) × IMAX
ROCSET =
2 x IOCSET
the low-side MOSFET. The lossless RDS(ON) current sensing
technique is cost-effective, because no external component where IOCSET is 25uA (typical), IMAX represents the allowed
is required. The RT8108 series utilize cycle-by-cycle peak maximum inductor peak current.

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RT8108
MOSFET Drivers inductors can save board space especially when the height
The RT8108 series integrate high-current gate drivers for has limitation.
MOSFETs to obtain high-efficiency power conversion in Additionally, larger inductance results in lower ripple current,
synchronous buck topology. A dead time is used to prevent and therefore the lower power loss. However, the inductor
the crossover conduction for the high-side and low-side current rising time increases with inductance value. This
MOSFETs. Because both the two gate signals are off means the inductor will have a longer charging time before
during the dead time, the inductor current freewheels its current reaches the required output current. Since the
through the body diode of the low-side MOSFET. The response time is increased, the transient response
freewheeling current and the forward voltage of the body performance will be decreased. Therefore, the inductor
diode contribute to the power loss. The RT8108 series design is a trade-off between performance, size and cost.
employ a constant dead time control scheme to ensure
In general, inductance is designed such that the ripple
safe operation without sacrificing efficiency. Furthermore,
current ranges between 20% to 30% of full load current.
an elaborate logic circuit is implemented to prevent the
The inductance can be calculated using the following
cross-conduction between MOSFETs.
equation.
For high output current applications, two or more power VIN − VOUT V
LMIN = × OUT
MOSFETs are paralleled to have reduced RDS(ON). The gate FSW × k × IOUT_Full Load VIN
driver needs to provide more current to switch on/off these
where k is 0.2 to 0.3.
paralleled MOSFETs. Gate driver with lower source/sink
current capability results in longer rising/ falling time in Input Capacitor Selection
gate signals, and therefore the higher switching loss.
Voltage rating and current rating are the key parameters in
The RT8108 series employ embedded high-current gate selecting input capacitor. The voltage rating must be 1.25
drivers to obtain high-efficiency power conversion. The times greater than the maximum input voltage to ensure
embedded drivers contribute to the majority of the controller enough room for safe operation. Generally, input capacitor
power dissipation. If no gate resistor is used, the power has a voltage rating of 1.5 times greater than the maximum
dissipation of the controller can be approximately calculated input voltage is a conservatively safe design.
using the following equation.
The input capacitor is used to supply the input RMS
PSW = FSW x (Qg_High-Side x VBOOT + Qg_Low-Side current, which can be approximately calculated using the
x VDrive_Low-Side ) following equation.
VOUT ⎛ VOUT ⎞
where VBOOT represents the voltage across the bootstrap IRMS = IOUT × × 1−
VIN ⎜⎝ VIN ⎟⎠
capacitor.
It is important to ensure the package can dissipate the Refer to the manufacturer's databook for RMS current rating
switching loss and have enough room for safe operation. to select proper capacitor. Use more than one capacitor
with low equivalent series resistance (ESR) in parallel to
Inductor Selection form a capacitor bank is popular. Besides, placing ceramic
Inductor plays an importance role in the buck converter capacitor close to the drain of the high-side MOSFET is
because the energy from the input power rail is stored in it helpful in reducing the input voltage ripple at heavy load.
and then released to the load. From the viewpoint of
Output Capacitor Selection
efficiency, the dc resistance (DCR) of inductor should be
as small as possible because inductor carries current all The output capacitor and the inductor form a low-pass filter
the time. Using inductor that has lower DCR can obtain in the buck topology. The electrolytic capacitor is usually
higher efficiency. In addition, because inductor cost most used because it can provide large capacitance value. In
of the board space, its size is also important. Low profile steady state condition, the output capacitor supplies only
AC ripple current to the load. The ripple current flows into/

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 RT8108
out of the capacitor results in ripple voltage, which can be In order to achieve fast transient response and accurate
determined using the following equation. output regulation, an adequate compensator design is
ΔVOUT_ESR = ΔIL x ESR necessary. The goal of the compensation network is to
provide adequate phase margin (greater than 45 degrees)
In addition, the output voltage ripple is also influenced by
and the highest 0dB crossing frequency. It is also
the switching frequency and the capacitance value.
recommended to manipulate loop frequency response that
ΔVOUT_C = ΔIL × 1
8 × COUT × FSW its gain crosses over 0dB at a slope of −20dB/dec.
V IN
The total output voltage ripple is the sum of VOUT_ESR and
OSC Driver
VOUT_C. PWM
Comparator
L OUT
If the specification for steady-state output voltage ripple is -
V OUT
ΔV OSC Driver PHASE
known, the ESR can be determined using the above +
C OUT
equations.
ESR
Another parameter that has influence on the output voltage Z FB

undershoot is the equivalent series inductance (ESL). The COMP

- Z IN
rapid change in load current results in di/dt during transient. EA
+
REF
Therefore, ESL contributes to part of the voltage
undershoot. Use capacitor that has low ESL to obtain better
transient performance. Generally, use several capacitors Z FB V OUT
C2 Z IN
connected in parallel can have better transient performance C1 R2 C3 R3
than use single capacitor for the same total ESR. R1
COMP
- FB
Unlike the electrolytic capacitor, the ceramic capacitor has EA
+
relatively low ESR and can reduce the voltage deviation REF

during load transient. However, the ceramic capacitor can

only provide low capacitance value. Therefore, use a mixed Figure 3. Control Loop for Voltage Mode Buck Converter
combination of electrolytic capacitor and ceramic capacitor
can also have better transient performance. 1) Modulator and Output LC filter
Referring to Figure 3, the modulator gain is the input voltage
Feedback Loop Compensation
VIN divided by the peak to peak oscillator voltage VOSC as
Figure 3 shows the voltage mode control loop for a buck
shown as following Equation :
converter. The control loop consists of the modulator, output
VIN
LC filter and the compensator. The modulator is composed ModulatorGain =
ΔVOSC
of the PWM comparator and power MOSFETs. The PWM
where ΔVOSC = 1.5V (typ.)
comparator compares the error amplifier EA output (COMP)
with the oscillator (OSC) sawtooth wave to generate a PWM The output LC filter introduces a double pole to the transfer
signal. The MOSFETs is then switched on and off function, creating −40dB/decade gain slope above its corner
according to the duty cycle of the PWM signal. The voltage frequency, with a phase lag of 180 degrees. The frequency
presented at PHASE node is a square wave of 0V to Vin. at the double-pole of LC filter is expressed as follows.
The PHASE voltage is filtered by the output filter LOUT and fLC = 1
COUT to produce output voltage VOUT, which is fedback to 2π × LOUT × COUT
the inverting input of the error amplifier. The output voltage
is then regulated according to the reference voltage VREF.

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RT8108
In addition, the ESR of the output capacitor introduces a 80 80
Loop Gain
zero to the transfer function, creating a +20dB/dec gain 60
slope with a phase shift of 90 degree. The frequency of the
40 40
Compensation
ESR zero is expressed as follows. Gain
20
fESR = 1

Gain (dB)
2π × ESR × COUT 0
0
Modulator
2) Compensator -20 Gain

Fugire 4 illustrates the type II compensator, which consists -40-40

of the error amplifier and the impedance ZC and ZF.
-60-60
10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz
ZF 10vdb(vo) vdb(comp2)100vdb(lo) 1k 10k 100k 1M
Frequency
Frequency (Hz)
C1
ZC
C2 Figure 5. System Gain Bode Plot
R2 R1
V OUT

Layout Considerations

FB
PCB layout is critical to high-current high-frequency
-
COMP
EA
+ switching converter designs. A good layout can help the
RF
V REF controller to function properly and achieve expected
performance. On the other hand, PCB without a carefully
Figure 4. Type II Compensator layout can radiate excessive noise, having more power
loss and even malfunction in the controller. In order to avoid
Type II compensator provides two poles and one zero to the above condition, the following general guidelines must
the system. The first pole is located at low frequency to be followed in PCB layout.
increase the dc gain for regulation accuracy. The location
` Power stage components should be placed first. Place
of the other pole and the zero is expressed as follows.
the input bulk capacitors close to the high-side power
fZ1 = 1
2π × R2 × C2 MOSFETs, and then locate the output inductor and finally
the output capacitors.
fP1 = 1
2π × R2 × C1× C2 ` Place the ceramic capacitor physically close to the drain
C1+ C2
of the high-side MOSFET. This can reduce the input
Figure 5 shows the Bode plot for the gain of system. The
voltage drop when high-side MOSFET is turned on. If
compensation gain determined by ZC and ZF should be
more than one MOSFET is paralleled, each should have
designed to have high crossover frequency (bandwidth) with
its own individual ceramic capacitor.
sufficient phase margin. In order to make the gain crosses
over 0dB at a slope of −20dB/dec, place the zero before ` Keep the high-current loops as short as possible. During
the LC double-pole frequency. Empirically, fz1 is placed at high speed switching, the current transition between
75% of the LC double-pole frequency. Furthermore, the MOSFETs usually causes di/dt voltage spike due to the
bandwidth of the system is the factor that affects the parasitic components on PCB trace. Therefore, making
converter's transient performance. High bandwidth results the trace length between power MOSFETs and inductors
in fast transient response, but it often jeopardizes the wide and short can reduce the voltage spike and EMI.
system stability. The bandwidth should be designed to be ` Make MOSFET gate driver path as short as possible.
less than 1/5 of the switching frequency. Properly adjust Since the gate driver uses narrow-width high-current
R1 and R2 to change the mid-frequency gain to obtain the pulses to switch on/off the power MOSFET, the driver
required bandwidth. The pole at fp1 is usually placed at half path must be short to reduce the trace inductance. This
of the switching frequency to have sufficient phase margin is especially important for low-side MOSFET, because
and attenuation at high frequency. this can reduce the possibility of shoot-through.

[Link] DS8108-03 September 2011

12
 RT8108
` Providing enough copper area around the power
MOSFETs to help heat dissipation. Using thick copper
also reduces the trace resistance and inductance to have
better performance.
` The output capacitors should be placed physically close
to the load. This can minimize the trace parasitic
components and improve transient response.
` All small signal components should be located close to
the controller. The small signal components include the
feedback voltage divider resistors, compensator, function
setting components and high-frequency bypass
capacitors. The feedback voltage divider resistor and the
compensator must be placed close to FB pin and COMP
pin, because these pins are inherently noise-sensitive.
` Voltage feedback path must be kept away from the
switching nodes. The noisy switching node is, for
example, the interconnection between high-side
MOSFET, low-side MOSFET and inductor. The feedback
path must be kept away from this kind of noisy node to
avoid noise pick-up.
` A multi-layer PCB design is recommended. Make use Figure 6. PCB Layout
of one single layer as the ground and have separate
layers for power rail or signal that is suitable for PCB
design.

DS8108-03 September 2011 [Link]

13
RT8108
Outline Dimension

H
A

J B

C
I
D

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 3.988 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.050 0.254 0.002 0.010
J 5.791 6.200 0.228 0.244
M 0.400 1.270 0.016 0.050

8-Lead SOP Plastic Package

[Link] DS8108-03 September 2011

14
 RT8108
H
A

EXPOSED THERMAL PAD Y

(Bottom of Package)
J X B

C
I
D

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 4.000 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.510 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.000 0.152 0.000 0.006
J 5.791 6.200 0.228 0.244
M 0.406 1.270 0.016 0.050
X 2.000 2.300 0.079 0.091
Option 1
Y 2.000 2.300 0.079 0.091
X 2.100 2.500 0.083 0.098
Option 2
Y 3.000 3.500 0.118 0.138

8-Lead SOP (Exposed Pad) Plastic Package

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Headquarter Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@[Link]

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,
specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

DS8108-03 September 2011 [Link]

15