TLV757P

SBVS322C – OCTOBER 2017 – REVISED MARCH 2024

TLV757P 1A, Low IQ, Small-Size, Low-Dropout Regulator

1 Features 3 Description
• SOT-23 (DYD) package with 60.3°C/W RθJA The TLV757P low-dropout regulator (LDO) is an
available ultra-small, low quiescent current LDO that sources
• Input voltage range: 1.45V to 5.5V 1A with good line and load transient performance.
• Available in fixed-output voltages: The TLV757P is optimized for a wide variety of
– 0.6V to 5V (50mV steps) applications by supporting an input voltage range from
• Low IQ: 25μA (typical) 1.45V to 5.5V. To minimize cost and solution size,
• Low dropout: the device is offered in fixed output voltages ranging
– 425mV (maximum) at 1A (3.3VOUT) from 0.6V to 5V. This range supports the lower
• Output accuracy: 1% (maximum) core voltages of modern microcontrollers (MCUs).
• Built-in soft-start with monotonic VOUT rise Additionally, the TLV757P has a low IQ with enable
• Foldback current limit functionality to minimize standby power. This device
• Active output discharge features an internal soft-start to lower the inrush
• High PSRR: 45dB at 100kHz current. This feature provides a controlled voltage to
• Stable with a 1µF ceramic output capacitor the load and minimizes the input voltage drop during
• Packages: start-up. When shutdown, the device actively pulls
– 2.9mm × 2.8mm SOT-23-5 (DBV) down the output to quickly discharge the outputs and
– 2.9mm × 2.8mm SOT-23-5 (DYD) with thermal provides a known start-up state.
pad The TLV757P is stable with small ceramic output
– 2mm × 2mm WSON-6 (DRV) capacitors allowing for a small overall solution size.
A precision band-gap and error amplifier provides
2 Applications
a typical accuracy of 1%. All device versions
• Set-top boxes, TV, and gaming consoles have integrated thermal shutdown, current limit, and
• Portable and battery-powered equipment undervoltage lockout (UVLO). The TLV757P has
• Desktops, notebooks, and ultrabooks an internal foldback current limit that helps reduce
• Tablets and remote controls thermal dissipation during short-circuit events.
• White goods and appliances
• Grid infrastructure and protection relays The TLV757 is available in the popular SON and
• Camera modules and image sensors SOT23-5 packages. This device is also available in
a thermally enhanced SOT23-5 package (DYD) with
a thermal pad. This package provides significantly
IN OUT reduced thermal resistance compared to a standard
CIN TLV757P COUT SOT23-5 package.
EN GND Package Information
ON PART NUMBER PACKAGE(1) PACKAGE SIZE(2)

OFF DRV (WSON, 6) 2mm × 2mm

TLV757P DBV (SOT-23, 5) 2.9mm × 2.8mm
Typical Application DYD (SOT-23, 5) 2.9mm × 1.6mm
7 175
VOUT VIN VEN IOUT (1) For more information, see the Mechanical, Packaging, and
6 150 Orderable Information.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
Output Current (mA)

5 125
Voltage (V)

4 100

3 75

2 50

1 25

0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (ms)

Start-Up Waveform
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV757P
SBVS322C – OCTOBER 2017 – REVISED MARCH 2024 [Link]

Table of Contents
1 Features............................................................................1 7 Application and Implementation.................................. 15
2 Applications..................................................................... 1 7.1 Application Information............................................. 15
3 Description.......................................................................1 7.2 Typical Application.................................................... 19
4 Pin Configuration and Functions...................................3 7.3 Power Supply Recommendations.............................20
5 Specifications.................................................................. 4 7.4 Layout....................................................................... 21
5.1 Absolute Maximum Ratings........................................ 4 8 Device and Documentation Support............................22
5.2 ESD Ratings .............................................................. 4 8.1 Device Support......................................................... 22
5.3 Recommended Operating Conditions.........................4 8.2 Receiving Notification of Documentation Updates....22
5.4 Thermal Information....................................................5 8.3 Support Resources................................................... 22
5.5 Electrical Characteristics.............................................5 8.4 Trademarks............................................................... 22
5.6 Typical Characteristics................................................ 7 8.5 Electrostatic Discharge Caution................................22
6 Detailed Description......................................................12 8.6 Glossary....................................................................22
6.1 Overview................................................................... 12 9 Revision History............................................................ 22
6.2 Functional Block Diagram......................................... 12 10 Mechanical, Packaging, and Orderable
6.3 Feature Description...................................................12 Information.................................................................... 23
6.4 Device Functional Modes..........................................14

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4 Pin Configuration and Functions

IN 1 5 OUT IN 1 5 OUT

Thermal
GND 2
GND 2 Pad

EN 3 4 NC
EN 3 4 NC

Not to scale
Not to scale Figure 4-2. DYD Package, 5-Pin SOT-23 With
Figure 4-1. DBV Package, 5-Pin SOT-23 (Top View) Exposed Thermal Pad (Top View)

OUT 1 6 IN

NC 2 Thermal 5 NC
Pad
GND 3 4 EN

Not to scale

Figure 4-3. DRV Package, 6-Pin WSON With Exposed Thermal Pad (Top View)

Table 4-1. Pin Functions

PIN
TYPE DESCRIPTION
NAME DBV DYD DRV
Enable pin. Drive EN greater than VHI to turn on the regulator. Drive EN
EN 3 3 4 I
less than VLO to place the LDO into shutdown mode.
GND 2 2 3 — Ground pin.
Input pin. A capacitor with a value of 1µF or larger is required from this
IN 1 1 6 I pin to ground.(1) See the Input and Output Capacitor Selection section for
more information.
NC 4 4 2, 5 — No internal connection.
Regulated output voltage pin. A capacitor with a value of 1µF or larger
OUT 5 5 1 O is required from this pin to ground.(1) See the Input and Output Capacitor
Selection section for more information.
Connect the thermal pad to a large-area ground plane. The thermal pad is
Thermal pad — Pad Pad —
internally connected to GND.

(1) Make sure the nominal input and output capacitance are greater than 0.47µF. Throughout this document the nominal derating on these
capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 0.47µF.

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage,VIN –0.3 6.0 V
Enable voltage, VEN –0.3 6.0 V
Output voltage, VOUT –0.3 VIN + 0.3(2) V
Operating junction temperature range, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The absolute maximum rating is VIN + 0.3V or 6.0V, whichever is smaller

5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250V CDM is possible with the necessary precautions.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 1.45 5.5 V
VOUT Output voltage 0.6 5.0 V
VEN Enable voltage 0 5.5 V
IOUT Output current 0 1 A
CIN Input capacitor 1 µF
COUT Output capacitor 1 200 µF
fEN Enable toggle frequency 10 kHz
TJ Junction temperature –40 125 °C

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5.4 Thermal Information

TLV757
PCB THERMAL METRIC(1) (2) DYD (SOT-23) DBV (SOT-23) DRV (SON) UNIT
5 PINS 5 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 60.3 100.8 N/A °C/W
EVM ψJT Junction-to-top characterization parameter 14.2 23.3 N/A °C/W
ψJB Junction-to-board characterization parameter 35.9 67.8 N/A °C/W
RθJA Junction-to-ambient thermal resistance 92.5 231.1 100.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 119.8 118.4 108.5 °C/W
RθJB Junction-to-board thermal resistance 45.8 64.4 64.3 °C/W
JEDEC
ψJT Junction-to-top characterization parameter 16.7 28.4 10.4 °C/W
ψJB Junction-to-board characterization parameter 44.9 63.8 64.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 34.3 N/A 34.7 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) JEDEC thermal metrics apply to JEDEC standard PCB (2s2p, no vias to internal plane and bottom layer). EVM metrics apply to the
LP087A EVM with an exposed pad SOT-23-5 (DYD) layout.

5.5 Electrical Characteristics

over operating free-air temperature range (TJ = –40°C to +125°C), VIN = VOUT + 0.5 V or 1.45 V (whichever is greater), IOUT =
1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 1.45 5.5 V
VOUT Output voltage 0.6 5.0 V
–40°C ≤ TJ ≤ 85°C, VOUT ≥ 1V –1 1 %
–40°C ≤ TJ ≤ 85°C, 0.6V ≤ VOUT < 1V –10 10 mV
Output accuracy
VOUT ≥ 1V –1.5 1.5 %
0.6V ≤ VOUT < 1V –15 15 mV
(ΔVOUT)ΔVIN Line regulation VOUT + 0.5V(1) ≤ VIN ≤ 5.5V 2 mV
DRV package 0.044
ΔVOUT/ΔIOUT Load regulation 0.1mA ≤ IOUT ≤ 1A, VIN ≥ 2.4V V/A
DBV package 0.060
ΔVOUT/ΔIOUT Load regulation 0.1 mA ≤ IOUT ≤ 1A, VIN ≥ 2.4V DYD package 0.069 V/A
TJ = 25°C 25 31
IGND Ground current –40°C ≤ TJ ≤ +85°C 33 µA
–40°C ≤ TJ ≤ +125°C 40
ISHDN Shutdown current VEN ≤ 0.4V, 1.45V ≤ VIN ≤ 5.5V 0.1 1 µA
VOUT = VOUT - 0.2V, VOUT ≤ 1.5V
ICL Output current limit VIN = VOUT + VDO(MAX) + 0.25V VOUT = 0.9 x VOUT, 1.2 1.55 1.78 A
1.5V < VOUT ≤ 4.5V
ISC Short circuit current limit VOUT = 0V, VIN = VOUT + VDO(MAX) + 0.25V 755 mA

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5.5 Electrical Characteristics (continued)

over operating free-air temperature range (TJ = –40°C to +125°C), VIN = VOUT + 0.5 V or 1.45 V (whichever is greater), IOUT =
1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.6V ≤ VOUT < 0.8V 1350 1400
0.8V ≤ VOUT < 1V 1200 1300
0.8V ≤ VOUT < 1V, DYD package 1225 1325
1V ≤ VOUT < 1.2V 1100 1150
1V ≤ VOUT < 1.2V, DYD package 1125 1175
1.2V ≤ VOUT < 1.5V 1000 1050
1.2V ≤ VOUT < 1.5V, DYD package 1025 1075
IOUT = 1A,
1.5V ≤ VOUT < 1.8V 700 800
–40°C ≤ TJ ≤ +85°C
1.5V ≤ VOUT < 1.8V, DYD package 725 825
1.8V ≤ VOUT < 2.5V 650 750
1.8V ≤ VOUT < 2.5V, DYD package 650 775
2.5V ≤ VOUT < 3.3V 500 600
2.5V ≤ VOUT < 3.3V, DYD package 525 625
3.3V ≤ VOUT < 5.0V 300 425
3.3V ≤ VOUT < 5.0V, DYD package 300 450
VDO Dropout voltage mV
0.6V ≤ VOUT < 0.8V 1450
0.8V ≤ VOUT < 1V 1350
0.8V ≤ VOUT < 1V, DYD package 1375
1V ≤ VOUT < 1.2V 1200
1V ≤ VOUT < 1.2V, DYD package 1225
1.2V ≤ VOUT < 1.5V 1100
1.2V ≤ VOUT < 1.5V, DYD package 1125
IOUT = 1A,
1.5V ≤ VOUT < 1.8V 850
–40°C ≤ TJ ≤ +125°C
1.5V ≤ VOUT < 1.8V, DYD package 875
1.8V ≤ VOUT < 2.5V 800
1.8V ≤ VOUT < 2.5V, DYD package 825
2.5V ≤ VOUT < 3.3V 650
2.5V ≤ VOUT < 3.3V, DYD package 675
3.3V ≤ VOUT < 5.0V 475
3.3V ≤ VOUT < 5.0V, DYD package 500
f = 1kHz, VIN = VOUT + 1V, IOUT = 50mA 52
PSRR Power supply rejection ratio f = 100kHz, , VIN = VOUT + 1 V, IOUT = 50mA 46 dB
f = 1MHz, , VIN = VOUT + 1V, IOUT = 50mA 52
Vn Output noise voltage BW = 10Hz to 100kHz, VOUT = 1.2V, IOUT = 1A 71.5 µVRMS
VUVLO Undervoltage lockout VIN rising 1.21 1.3 1.44 V
Undervoltage lockout
VUVLO, HYST VIN falling 40 mV
hysteresis
tSTR Startup time 550 µs
EN pin high voltage
VHI 1 V
(enabled)
EN pin low voltage
VLO 0.3 V
(enabled)
IEN Enable pin current VIN = 5.5V, EN = 5.5V 10 nA
RPULLDOWN Pulldown resistance VIN = 3.3V (P version only) 95 Ω
Shutdown, temperature increasing 165 °C
TSD Thermal shutdown
Reset, temperature decreasing 155 °C

(1) VIN = 1.45V for VOUT < 0.9V

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5.6 Typical Characteristics

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5V or 1.45V (whichever is greater), IOUT = 1mA, VEN = VIN, and CIN
= COUT = 1µF (unless otherwise noted)

80 80

70 70
Power Supply Rejection Ratio (dB)

Power Supply Rejection Ratio (dB)

60 60

50 50

40 40

30 30

20 20 VIN = 3.8 V
IOUT VIN = 4 V
10 10 mA 100 mA 1A 10 VIN = 4.3 V
50 mA 500 mA VIN = 5 V
0 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

VIN = 4.3V, VOUT = 3.3V, COUT = 1µF VOUT = 3.3V, COUT = 1µF, IOUT = 1A
Figure 5-1. PSRR vs IOUT Figure 5-2. PSRR vs VIN
80 10
5
70
Power Supply Rejection Ratio (dB)

2
60
1
Noise (PV/—Hz)

50 0.5

40 0.2

30 0.1
COUT
COUT 0.05 4.7 PF, 151 PVRMS
20 1 PF 10 PF, 150 PVRMS
10 PF 0.02 22 PF, 151 PVRMS
10 22 PF 47 PF, 150 PVRMS
0.01
100 PF 100 PF, 148 PVRMS
0 0.005
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

VIN = 4.3V, VOUT = 3.3V, COUT = 1µF VOUT = 3.3V, IOUT = 1A, VRMS BW = 10Hz to 100kHz
Figure 5-3. PSRR vs COUT Figure 5-4. Output Spectral Noise Density
10 10
5 5
2
2
1
1 0.5
Noise (PV/—Hz)

Noise (PV/—Hz)

0.5
0.2
0.2 0.1
0.05
0.1
IOUT
0.02
0.05 10 mA, 158 PVRMS VOUT
50 mA, 159 PVRMS 0.01 0.9 V, 53.8 PVRMS
0.02 100 mA, 159 PVRMS 0.005 1.2 V, 71.47 PVRMS
500 mA, 153 PVRMS 3.3 V, 151 PVRMS
0.01 0.002
1 A, 151 PVRMS 5 V, 217 PVRMS
0.005 0.001
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

VOUT = 3.3V, COUT = 1µF, VRMS BW = 10Hz to 100kHz IOUT = 1A, COUT = 1µF, VRMS BW = 10Hz to 100kHz
Figure 5-5. Output Spectral Noise Density Figure 5-6. Output Noise vs Frequency and VOUT

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5.6 Typical Characteristics (continued)

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5V or 1.45V (whichever is greater), IOUT = 1mA, VEN = VIN, and CIN
= COUT = 1µF (unless otherwise noted)

220 6 3.328
VIN
200 VOUT
5 3.32
Output Noise Voltage (PVRMS)

180

Output Voltage (V)

Input Voltage (V)
160 4 3.312

140
3 3.304
120

100 2 3.296

80
1 3.288
60

40 0 3.28
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 20 40 50
Output Voltage (V) Time (ms)

IOUT = 1A, COUT = 1µF, VRMS BW = 10Hz to 100kHz VOUT = 3.3V, COUT = 1µF, VIN slew rate = 1V/µs
Figure 5-7. Output Noise Voltage vs VOUT Figure 5-8. Line Transient
200 2.2 6
VOUT VIN
150 2
IOUT VOUT
AC Coupled Output Voltage (mV)

100 1.8 5

50 1.6
Output Current (A)

4
0 1.4
Voltage (V)

-50 1.2
3
-100 1
-150 0.8
2
-200 0.6
-250 0.4 1
-300 0.2
-350 0 0
0 20 40 60 80 100 120 140 160 180 200 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Time (Ps) Time (ms)

VIN = 5V, VOUT = 3.3V, COUT = 1µF, IOUT slew rate = 1A/µs
Figure 5-9. 3.3V, 1mA to 1A Load Transient Figure 5-10. VIN = VEN Power-Up
6 7 175
VIN VOUT VIN VEN IOUT
VOUT 6 150
5

Output Current (mA)

5 125
4
Voltage (V)

Voltage (V)

4 100
3
3 75
2
2 50

1 1 25

0 0 0
0 1 2 3 4 5 6 7 8 9 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (ms) Time (ms)

VIN = 5V, IOUT = 100mA, VEN slew rate = 1V/µs, VOUT = 3.3V
Figure 5-11. VIN = VEN Shutdown Figure 5-12. EN Start-Up

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5.6 Typical Characteristics (continued)

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5V or 1.45V (whichever is greater), IOUT = 1mA, VEN = VIN, and CIN
= COUT = 1µF (unless otherwise noted)

15 400
-40qC -40qC 85qC
0qC 350 0qC 125qC
Change in Output Voltage (mV)

0 25qC 25qC
85qC 300

Dropout Voltage (mV)

125qC
-15 250

200
-30 150

100
-45
50

-60 0
0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000
Output Current (mA) Output Current (mA)

Figure 5-13. Load Regulation vs IOUT Figure 5-14. 3.3V Dropout Voltage vs IOUT
400 1
-40qC -40qC 25qC 125qC
350 0qC 0.75 0qC 85qC
25qC
300 85qC 0.5
Dropout Voltage (mV)

125qC
Accuracy (%)

250 0.25

200 0

150 -0.25

100 -0.5

50 -0.75

0 -1
0 100 200 300 400 500 600 700 800 900 1000 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Output Current (mA) Input Voltage (V)

VOUT = 3.3V, IOUT = 1mA

Figure 5-15. 5.0V Dropout Voltage vs IOUT Figure 5-16. 3.3V Regulation vs VIN (Line Regulation)
1 1400
-40qC 25qC 125qC 1300
0.75 0qC 85qC 1200
1100
0.5
GND Pin Current (PA)

1000
900
Accuracy (%)

0.25
800
0 700
600
-0.25 500
400 -40qC
-0.5 0qC
300
25qC
-0.75 200 85qC
100 125qC
-1 0
5 5.1 5.2 5.3 5.4 5.5 0 100 200 300 400 500 600 700 800 900 1000
Input Voltage (V) Output Current (mA)

IOUT = 1mA, VOUT = 5V

Figure 5-17. 5.0V Accuracy vs VIN (Line Regulation) Figure 5-18. IGND vs IOUT

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5.6 Typical Characteristics (continued)

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5V or 1.45V (whichever is greater), IOUT = 1mA, VEN = VIN, and CIN
= COUT = 1µF (unless otherwise noted)

650 300
600 -40qC -40qC
0qC 0qC
550 25qC 250 25qC
500 85qC 85qC

Quiescent Current (PA)

GND Pin Current (PA)

450 125qC 125qC

200
400
350
150
300
250
200 100
150
100 50
50
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
Input Voltage (V) Input Voltage (V)

VOUT = 3.3V, IOUT = 1mA VOUT = 3.3V, IOUT = 0mA

Figure 5-19. IGND vs VIN Figure 5-20. IGND vs VIN
350 180
-40qC
0qC 160
300
25qC
85qC 140
Shutdown Current (nA)

Shutdown Current (nA)

250 125qC
120
200 100

150 80

60
100
40
50
20

0 0
0 1 2 3 4 5 6 -40 -20 0 20 40 60 80 100 120 140
Input Voltage (V) Temperature (qC)

Figure 5-21. ISHDN vs VIN Figure 5-22. ISHDN vs Temperature

800 250
-40qC
0qC
750 25qC
200
85qC
Enable Threshold (mV)

Enable Current (PA)

125qC
700
150
650
100
600

50
550

EN Negative EN Positive
500 0
-50 -25 0 25 50 75 100 125 0 1 2 3 4 5 6
Temperature (qC) Input Voltage (V)

VEN = 5.5V
Figure 5-23. Enable Threshold vs Temperature Figure 5-24. IEN vs VIN

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5.6 Typical Characteristics (continued)

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5V or 1.45V (whichever is greater), IOUT = 1mA, VEN = VIN, and CIN
= COUT = 1µF (unless otherwise noted)

1.4 600
550 -40qC 85qC
0qC 125qC
500 25qC
1.36
450

Output Voltage (mV)

UVLO Threshold (V)

400
1.32 350
300
1.28 250
200
150
1.24
100

UVLO Negative UVLO Positive 50

1.2 0
-50 -25 0 25 50 75 100 125 0 1 2 3 4 5
Temperature (qC) Output Current (mA)

Figure 5-25. UVLO Threshold vs Temperature Figure 5-26. IOUT vs VOUT Pulldown Resistor
4

3.2
Output Voltage (V)

2.4

1.6

-40qC
0qC
0.8 25qC
85qC
125qC
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Output Current (mA)

Figure 5-27. 3.3V Foldback Current Limit vs IOUT

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6 Detailed Description
6.1 Overview
The TLV757P is a next-generation, low-dropout regulator (LDO). This device consumes low quiescent current
and delivers excellent line and load transient performance. The TLV757P is optimized for a wide variety of
applications by supporting an input voltage range from 1.4V to 5.5V. To minimize cost and solution size, the
device is offered in fixed output voltages ranging from 0.6V to 5V. This range supports the lower core voltages of
modern microcontrollers (MCUs).
This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature
is –40°C to +125°C.
6.2 Functional Block Diagram

IN OUT
Current
Limit

R1
Thermal
± + Shutdown

UVLO
120 Ÿ

R2

EN Bandgap GND

Logic

A. R2 = 550kΩ, R1 = adjustable.

6.3 Feature Description

6.3.1 Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) circuit disables the output until the input voltage is greater than the rising UVLO
voltage (VUVLO). This circuit makes sure the device does not exhibit unpredictable behavior when the supply
voltage is lower than the operational range of the internal circuitry. When VIN is less than VUVLO, the output is
connected to ground with a 120Ω pulldown resistor.
6.3.2 Enable (EN)
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VHI. Turn off the device by
forcing the EN pin below VLO. If shutdown capability is not required, connect EN to IN.
The device has an internal pull-down that connects a 120Ω resistor to ground when the device is disabled. The
discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel
with the 120Ω pulldown resistor. Equation 1 calculates the time constant τ:

120 · RL
t= · COUT
120 + RL (1)

The EN pin is independent of the input pin. However, if the EN pin is driven to a higher voltage than VIN, the
current into the EN pin increases. This effect is illustrated in Figure 5-24. When the EN voltage is higher than

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the input voltage there is an increased current flow into the EN pin. If this increased flow causes problems in the
application, sequence the EN pin after VIN is high, or tie EN to VIN. If EN is driven to a higher voltage than VIN,
limit the frequency on EN to below 10kHz.
6.3.3 Internal Foldback Current Limit
The TLV757P has an internal current limit that protects the regulator during fault conditions. The current limit is
a hybrid scheme with brick wall until the output voltage is less than 0.4 × VOUT(NOM). When the voltage drops
below 0.4 × VOUT(NOM), a foldback current limit is implemented that scales back the current as the output voltage
approaches GND. When the output shorts, the LDO supplies a typical current of ISC. The output voltage is not
regulated when the device is in current limit. In this condition, the output voltage is the product of the regulated
current and the load resistance. When the device output is shorts, the PMOS pass transistor dissipates power
[(VIN – VOUT) × ISC] until thermal shutdown is triggered and the device turns off. After the device cools down,
the internal thermal shutdown circuit turns the device back on. If the fault condition continues, the device cycles
between current limit and thermal shutdown.
The foldback current-limit circuit limits the current that is allowed through the device to current levels lower than
the minimum current limit at nominal VOUT current limit (ICL) during start up. See Figure 5-27 for typical current
limit values. If the output is loaded by a constant-current load during start up, or if the output voltage is negative
when the device is enabled, then the load current demanded by the load potentially exceeds the foldback current
limit. Thus, causing the device to possibly not rise to the full output voltage. For constant-current loads, disable
the output load until the output rises to the nominal voltage.
Excess inductance causes the current limit to oscillate. Minimize the inductance to keep the current limit from
oscillating during a fault condition.
6.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 165°C.
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the
junction temperature cools to approximately 155°C, the output circuitry is enabled again. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit cycles on and off. This
cycling limits regulator dissipation, which protects the circuit from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product
of the (VIN – VOUT) voltage and the load current. For reliable operation, limit junction temperature to a maximum
of 125°C. To estimate the margin of safety in a complete design, increase the ambient temperature until the
thermal protection is triggered; use worst-case loads and signal conditions.
The internal protection circuitry protects against overload conditions but is not intended to be activated in normal
operation. Continuously running the device into thermal shutdown degrades device reliability.

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6.4 Device Functional Modes

Table 6-1 lists a comparison between the normal, dropout, and disabled modes of operation.
Table 6-1. Device Functional Modes Comparison
PARAMETER
OPERATING MODE
VIN EN IOUT TJ
Normal(1) VIN > VOUT(NOM) + VDO VEN > VHI IOUT < ICL TJ < TSD
Dropout(1) VIN < VOUT(NOM) + VDO VEN > VHI — TJ < TSD
Disabled(2) VIN < VUVLO VEN < VLO — TJ > TSD

(1) Make sure all table conditions are met.

(2) The device is disabled when any condition is met.

6.4.1 Normal Operation

The device regulates to the nominal output voltage when all of the following conditions are met.
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
6.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device degrades because the pass
transistor is in a triode state and no longer controls the output voltage of the LDO. Line or load transients in
dropout result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) +
VDO, right after being in a normal regulation state, but not during start-up), the pass transistor is driven as hard
as possible when the control loop is out of balance. During the normal time required for the device to regain
regulation, VIN ≥ VOUT(NOM) + VDO, VOUT overshoots VOUT(NOM) during fast transients.
6.4.3 Disabled
The output is shut down by forcing the enable pin below VLO. When disabled, the pass transistor is turned off,
internal circuits are shut down, and the output voltage is actively discharged to ground by an internal switch from
the output to ground. The active pulldown is on when sufficient input voltage is provided.

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Application Information

7.1.1 Input and Output Capacitor Selection
The TLV757P requires an output capacitance of 0.47μF or larger for stability. Use X5R- and X7R-type
ceramic capacitors because these capacitors have minimal variation in capacitance value and equivalent series
resistance (ESR) over temperature. When selecting a capacitor for a specific application, consider the DC
bias characteristics for the capacitor. Higher output voltages cause a significant derating of the capacitor. As
a general rule, make sure ceramic capacitors are derated by 50%. For best performance, use an output
capacitance value no greater than 200µF.
Place a 1µF or greater capacitor on the input pin of the LDO. Some input supplies have a high impedance.
Placing a capacitor on the input supply reduces the input impedance. The input capacitor counteracts reactive
input sources and improves transient response and PSRR. If the input supply has high impedance over a large
range of frequencies, use several input capacitors in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are expected, or if the device is located several
inches from the input power source.
7.1.2 Dropout Voltage
The TLV757P uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass transistor is in the linear region of operation and the input-to-output resistance
is the RDS(ON) of the PMOS pass transistor. VDO scales linearly with the output current because the PMOS
transistor functions like a resistor in dropout mode. As with any linear regulator, PSRR and transient response
degrade as (VIN – VOUT) approaches dropout operation. See Figure 5-14 and Figure 5-15 for typical dropout
values.
7.1.3 Exiting Dropout
Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up.
As with other LDOs, the output overshoots on recovery from these conditions. A ramping input supply causes an
LDO to overshoot on start-up when the slew rate and voltage levels are in the correct range; see Figure 7-1. Use
an enable signal to avoid this condition.

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Input Voltage

Response time for

LDO to get back into
regulation. Load current discharges
output voltage.
VIN = VOUT(nom) + VDO

Output Voltage

Dropout
Voltage

VOUT = VIN - VDO

Output Voltage in
normal regulation.

Time

Figure 7-1. Start-Up Into Dropout

Line transients out of dropout also cause overshoot on the output of the regulator. These overshoots are caused
by the error amplifier having to drive the gate capacitance of the pass transistor and bring the gate back to the
correct voltage for proper regulation. Figure 7-2 illustrates what is happening internally with the gate voltage and
how overshoot is caused during operation. When the LDO is placed in dropout, the gate voltage (VGS) is pulled
all the way down to give the pass transistor the lowest on-resistance as possible. However, if a line transient
occurs when the device is in dropout, the loop is not in regulation, which causes the output to overshoot until the
loop responds and the output current pulls the output voltage back down into regulation. If these transients are
not acceptable, then continue to add input capacitance in the system until the transient is slow enough to reduce
the overshoot.

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Figure 7-2. Line Transients From Dropout

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7.1.4 Reverse Current

As with most LDOs, excessive reverse current potentially damages this device.
Reverse current flows through the body diode on the pass transistor instead of the normal conducting channel.
At high magnitudes, this current flow degrades the long-term reliability of the device, as a result of one of the
following conditions:
• Degradation caused by electromigration
• Excessive heat dissipation
• Potential for a latch-up condition
Conditions where reverse current occurs are outlined in this section, all of which exceed the absolute maximum
rating of VOUT > VIN + 0.3V:
• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply
If reverse current flow is expected in the application, use external protection to protect the device. Figure 7-3
shows one approach of protecting the device.
Schottky Diode

Internal Body Diode

IN OUT

CIN Device COUT

GND

Figure 7-3. Example Circuit for Reverse Current Protection Using a Schottky Diode

7.1.5 Power Dissipation (PD)

Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. Make sure the PCB area around the
regulator is as free of other heat-generating devices as possible that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:

PD = (VIN – VOUT) × IOUT (2)

Minimize power dissipation to achieve greater efficiency. This minimizing process is achieved by selecting the
correct system voltage rails. Proper selection helps obtain the minimum input-to-output voltage differential. The
low dropout of the device allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, solder the
thermal pad to a copper pad area under the device. Make sure this pad area contains an array of plated vias that
conduct heat to inner plane areas or to a bottom-side copper plane.
The maximum allowable junction temperature (TJ) determines the maximum power dissipation for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB, device package, and the temperature of the ambient air (TA), according to Equation
3.

TJ = TA + RθJA × PD (3)

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Unfortunately, this thermal resistance (RθJA) is dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location
of the planes. The RθJA value is only used as a relative measure of package thermal performance. RθJA is the
sum of the WSON package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance
contribution by the PCB copper.
[Link] Estimating Junction Temperature
The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not thermal resistances, but
offer practical and relative means of estimating junction temperatures. These psi metrics are independent of the
copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are shown in the Thermal Information table and
are used in accordance with Equation 4.

YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD (4)

where:
• PD is the power dissipated as shown in Equation 2
• TT is the temperature at the center-top of the device package
• TB is the PCB surface temperature measured 1mm from the device package and centered on the package
edge
7.2 Typical Application

IN OUT

DC-DC 1 μF 1 μF
Converter TLV757P
Load

EN GND

ON

OFF

Figure 7-4. TLV757P Typical Application

7.2.1 Design Requirements

Table 7-1 lists the design requirements for this application.
Table 7-1. Design Parameters
PARAMETER DESIGN REQUIREMENT
Input voltage 2.5V
Output voltage 1.8V
Input current 700mA (maximum)
Output load 600mA DC
Maximum ambient temperature 70°C

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7.2.2 Detailed Design Procedure

[Link] Input Current
During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.
During start-up, the input current is higher as a result of the inrush current charging the output capacitor. Use
Equation 5 to calculate the current through the input.

COUT ´ dVOUT(t) VOUT(t)

IOUT(t) = +
dt RLOAD (5)

where:
• VOUT(t) is the instantaneous output voltage of the turn-on ramp
• dVOUT(t) / dt is the slope of the VOUT ramp
• RLOAD is the resistive load impedance
[Link] Thermal Dissipation
Junction temperature is determined using the junction-to-ambient thermal resistance (RθJA) and the total power
dissipation (PD). Use Equation 6 to calculate the power dissipation. Multiply PD by RθJA and add the ambient
temperature (TA) to calculate the junction temperature (TJ) as Equation 7 shows.

PD = (IGND+ IOUT) × (VIN – VOUT) (6)

TJ = RθJA × PD + TA (7)

If the (TJ(MAX)) value does not exceed 125°C, calculate the maximum ambient temperature as Equation 8 shows.
Equation 9 calculates the maximum ambient temperature with a value of 82.916°C.

TA(MAX) = TJ(MAX) – RθJA × PD (8)

TA(MAX) = 125°C – 100.2 × (2.5V –1.8V) × (0.6A) = 82.916°C (9)

7.2.3 Application Curves

3 1.2 100
Power Supply Rejection Ratio (dB)

2.5 1
80
Input Current (A)

2 0.8
Voltage (V)

60
1.5 0.6
40
1 0.4
VIN
VOUT 20
0.5 0.2
EN
IIN IOUT = 600 mA
0 0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 10 100 1k 10k 100k 1M 10M
Time (ms) Frequency (Hz)

VIN = 2.5V, VOUT = 1.8V, IOUT = 600mA

Figure 7-5. Start-Up With a 600mA Load Figure 7-6. PSRR (2.5V to 1.8V at 600mA)

7.3 Power Supply Recommendations

Connect a low output impedance power supply directly to the IN pin of the TLV757P. If the input source
is reactive, use multiple input capacitors in parallel with the 1µF input capacitor to lower the input supply
impedance over frequency.

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7.4 Layout
7.4.1 Layout Guidelines
• Place input and output capacitors as close as possible to the device.
• Use copper planes for device connections to optimize thermal performance.
• Place thermal vias around the device to distribute the heat.
• For packages with thermal pads, solder the thermal pad to copper to achieve best thermal resistance.
Thermal resistance increases significantly when the thermal pad is not soldered.
7.4.2 Layout Examples
VIN VOUT

1 5

CIN 2 COUT

3 4
EN

GND PLANE

Represents via used for

application specific connections

Figure 7-7. Layout Example: DBV Package

VOUT VIN

1 6

COUT 2 5 CIN

3 4

EN
GND PLANE

Represents via used for

application specific connections

Figure 7-8. Layout Example: DRV Package

VIN VOUT
1 6

CIN
Thermal COUT
Pad
2

VEN
3 5
GND PLANE

Represents via used for

application specific connections

Figure 7-9. Layout Example: DYD Package

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8 Device and Documentation Support

8.1 Device Support
8.1.1 Device Nomenclature
Table 8-1. Device Nomenclature(1)(2)
PRODUCT VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 50mV, two digits are used in
the ordering number; otherwise, three digits are used (for example, 28 = 2.8V; 125 = 1.25V).
P indicates an active output discharge feature. All members of the TLV757P family actively discharge
TLV757xx(x)Pyyyz
the output when the device is disabled.
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on [Link].
(2) Output voltages from 0.6V to 5V in 50mV increments are available. Contact the factory for details and availability.

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on [Link]. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2023) to Revision C (March 2024) Page
• Changed DYD package from Preview to Production Data ................................................................................ 1
• Added SOT-23 (DYD) package bullet to Features section................................................................................. 1
• Added last bullet item to Layout Guidelines section......................................................................................... 21
• Added Layout Example: DYD Package figure..................................................................................................21

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Changes from Revision A (December 2017) to Revision B (December 2023) Page

• Changed DBV package from Preview to Production Data (active).................................................................... 1
• Added DYD package as Preview....................................................................................................................... 1
• Added links to Applications section.................................................................................................................... 1
• Added package discussion to Description section............................................................................................. 1

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

[Link] 23-Aug-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TLV75709PDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1H8F
TLV75709PDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1H8F
TLV75709PDBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1H8F
TLV75709PDRVR Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HGH
TLV75709PDRVR.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HGH
TLV75710PDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FEF
TLV75710PDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FEF
TLV75710PDBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FEF
TLV75710PDRVR Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HHH
TLV75710PDRVR.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HHH
TLV75712PDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FFF
TLV75712PDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1FFF
TLV75712PDRVR Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HIH
TLV75712PDRVR.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HIH
TLV75712PDYDR Active Production SOT-23 (DYD) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 3DVH
TLV75712PDYDR.A Active Production SOT-23 (DYD) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 3DVH
TLV75715PDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FGF
TLV75715PDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FGF
TLV75715PDBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FGF
TLV75715PDRVR Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HJH
TLV75715PDRVR.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HJH
TLV75715PDRVRG4 Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HJH
TLV75715PDRVRG4.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HJH
TLV75718PDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FHF
TLV75718PDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FHF
TLV75718PDBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FHF
TLV75718PDRVR Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HKH
TLV75718PDRVR.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HKH
TLV75718PDYDR Active Production SOT-23 (DYD) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 3DWH

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 23-Aug-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TLV75718PDYDR.A Active Production SOT-23 (DYD) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 3DWH
TLV75719PDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1H7F
TLV75719PDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1H7F
TLV75719PDBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1H7F
TLV75719PDRVR Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HLH
TLV75719PDRVR.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HLH
TLV75725PDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FIF
TLV75725PDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FIF
TLV75725PDBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FIF
TLV75725PDBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FIF
TLV75725PDBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FIF
TLV75725PDRVR Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HMH
TLV75725PDRVR.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HMH
TLV75725PDYDR Active Production SOT-23 (DYD) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 3DXH
TLV75725PDYDR.A Active Production SOT-23 (DYD) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 3DXH
TLV75728PDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FJF
TLV75728PDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FJF
TLV75728PDBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FJF
TLV75728PDRVR Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HNH
TLV75728PDRVR.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HNH
TLV75728PDRVRG4 Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HNH
TLV75728PDRVRG4.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HNH
TLV75728PDYDR Active Production SOT-23 (DYD) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 3DZH
TLV75728PDYDR.A Active Production SOT-23 (DYD) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 3DZH
TLV75729PDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1H9F
TLV75729PDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1H9F
TLV75730PDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1GHF
TLV75730PDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1GHF
TLV75730PDBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1GHF
TLV75730PDRVR Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HOH
TLV75730PDRVR.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HOH

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

[Link] 23-Aug-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TLV75730PDRVRG4 Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HOH
TLV75730PDRVRG4.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HOH
TLV75730PDYDR Active Production SOT-23 (DYD) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 3E1H
TLV75730PDYDR.A Active Production SOT-23 (DYD) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 3E1H
TLV75733PDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FKF
TLV75733PDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1FKF
TLV75733PDRVR Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HPH
TLV75733PDRVR.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HPH
TLV75733PDRVRG4 Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HPH
TLV75733PDRVRG4.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HPH
TLV75733PDYDR Active Production SOT-23 (DYD) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 3E2H
TLV75733PDYDR.A Active Production SOT-23 (DYD) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 3E2H
TLV75740PDRVR Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HQH
TLV75740PDRVR.A Active Production WSON (DRV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1HQH

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

[Link] 23-Aug-2025

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 4
 PACKAGE MATERIALS INFORMATION

[Link] 24-Jun-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV75709PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75709PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75710PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75710PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75710PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75712PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75712PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75712PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75712PDYDR SOT-23 DYD 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75715PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75715PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75715PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75715PDRVRG4 WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75718PDBVR SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75718PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75718PDYDR SOT-23 DYD 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 24-Jun-2025

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV75719PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75719PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75719PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75725PDBVR SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75725PDBVRG4 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75725PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75725PDYDR SOT-23 DYD 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75728PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75728PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75728PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75728PDRVRG4 WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75728PDYDR SOT-23 DYD 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75729PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75729PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75730PDBVR SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75730PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75730PDRVRG4 WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75730PDYDR SOT-23 DYD 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75733PDBVR SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75733PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75733PDRVRG4 WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75733PDYDR SOT-23 DYD 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75740PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 24-Jun-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV75709PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75709PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75710PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75710PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75710PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75712PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75712PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75712PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75712PDYDR SOT-23 DYD 5 3000 210.0 185.0 35.0
TLV75715PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75715PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75715PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75715PDRVRG4 WSON DRV 6 3000 210.0 185.0 35.0
TLV75718PDBVR SOT-23 DBV 5 3000 208.0 191.0 35.0
TLV75718PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75718PDYDR SOT-23 DYD 5 3000 210.0 185.0 35.0
TLV75719PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75719PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0

Pack Materials-Page 3
 PACKAGE MATERIALS INFORMATION

[Link] 24-Jun-2025

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV75719PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75725PDBVR SOT-23 DBV 5 3000 208.0 191.0 35.0
TLV75725PDBVRG4 SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75725PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75725PDYDR SOT-23 DYD 5 3000 210.0 185.0 35.0
TLV75728PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75728PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75728PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75728PDRVRG4 WSON DRV 6 3000 210.0 185.0 35.0
TLV75728PDYDR SOT-23 DYD 5 3000 210.0 185.0 35.0
TLV75729PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75729PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75730PDBVR SOT-23 DBV 5 3000 208.0 191.0 35.0
TLV75730PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75730PDRVRG4 WSON DRV 6 3000 210.0 185.0 35.0
TLV75730PDYDR SOT-23 DYD 5 3000 210.0 185.0 35.0
TLV75733PDBVR SOT-23 DBV 5 3000 208.0 191.0 35.0
TLV75733PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75733PDRVRG4 WSON DRV 6 3000 210.0 185.0 35.0
TLV75733PDYDR SOT-23 DYD 5 3000 210.0 185.0 35.0
TLV75740PDRVR WSON DRV 6 3000 210.0 185.0 35.0

Pack Materials-Page 4
 PACKAGE OUTLINE
DYD0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3
1.025
0.925
(0.16)
(0.0625)

(0.24)

PKG
1.75
1.65

4228946/A 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.

[Link]
 EXAMPLE BOARD LAYOUT
DYD0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG

(0.0625) ( 0.2) TYP

5X (1.1)
1

5
5X (0.6)

2 SYMM (1.9)

(1.7)

2X (0.95)
(1.1)
3
4

(R0.05) TYP
(0.975)

(1.3)

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4228946/A 08/2022

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DYD0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG

(0.0625)
5X (1.1)
1

5
5X (0.6)

2 SYMM
(1.9)
(1.7)
2X(0.95)

3 4

(R0.05) TYP

(0.975)

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:20X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.100 1.09 X 1.90
0.125 0.975 X 1.700 (SHOWN)
0.150 0.89 X 1.55
0.175 0.82 X 1.44

4228946/A 08/2022

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/K 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

[Link]
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/K 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/K 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
 GENERIC PACKAGE VIEW
DRV 6 WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4206925/F
 PACKAGE OUTLINE
DRV0006A SCALE 5.500
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

2.1 A
B
1.9

PIN 1 INDEX AREA

2.1
1.9

0.8
0.7 C

SEATING PLANE

0.08 C

(0.2) TYP
1 0.1 0.05
EXPOSED 0.00
THERMAL PAD

3
4

2X
7
1.3 1.6 0.1

6
1
4X 0.65
0.35
6X
PIN 1 ID 0.3 0.25
6X
(OPTIONAL) 0.2 0.1 C A B
0.05 C

4222173/B 04/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

[Link]
 EXAMPLE BOARD LAYOUT
DRV0006A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

6X (0.45)
(1)
1 7

6X (0.3) 6

SYMM (1.6)
(1.1)

4X (0.65)

4
3

(R0.05) TYP SYMM

( 0.2) VIA
TYP (1.95)

LAND PATTERN EXAMPLE

SCALE:25X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

4222173/B 04/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 ([Link]/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

[Link]
 EXAMPLE STENCIL DESIGN
DRV0006A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM
6X (0.45)
METAL
1 7

6X (0.3) 6

(0.45)
SYMM

4X (0.65)
(0.7)
4
3

(R0.05) TYP
(1)

(1.95)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X

4222173/B 04/2018
NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

[Link]
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