WALCHAND COLLEGE OF ENGINEERING
(Government Aided Autonomous Institute)
Visharambag, Sangli – 416415
Second Year [Link]. (Information Technology)
ESE , ODD SEMESTER, AY 2022-23
Microprocessors (6IT203) ESE
PRN: ________________________
Day & Date: Wednesday, 21/12/2022 Time: 10.00 am to 12.00 noon
Max Marks: 50
IMP: Verify that you have received question papers with correct course code, branch etc.
Instructions a) All questions are compulsory.
b) Writing question number on answer book is compulsory otherwise answers may not be assessed.
c) Assume suitable data wherever necessary.
d) Figures to the right of question text indicate full marks.
e) Mobile phones, smart gadgets and programmable calculators are strictly prohibited.
f) Except PRN anything else writing on question paper is not allowed.
g) Exchange/Sharing of stationery, calculator etc. not allowed.
Text on the right of marks indicates course outcomes (Only for faculty use) Marks
Q1 A) Write Boolean function for SUM of Full Adder and implement same using single 4 CO1
4X1 MUX.
Soln:
4 i/ps = D0, D1, D2 and D3
1 o/p = Y = SUM = F(A,B,C) = ∑m(1,2,4,7)
Therefore, i/ps to the 4X1 MUX are D0=A, D1=A’, D2=A’ and D3=A
B) Design and implement MOD 5 Asynchronous up counter using positive edge CO1
triggered JK flip flop.
Soln:
State diagram: Unique five states are 000, 001, 010, 011 & 100
No. of JK F/Fs are: 3 and all inputs connected to Logic 1 and output Q’ of LSB F/F
is CLK i/p to next.
C) Categories following statements into TRUE and FALSE. 3 CO1
i) An encoder in which the highest and lowest value input digits are encoded
simultaneously is known as a priority encoder. - False
ii) The following combination is correct for an EVEN parity data transmission
system: data = 100111100 and parity = 0 - False
iii) An exclusive-OR gate will invert a signal on one input if the other is always
HIGH. – True
D) Implement Boolean function F = (X + Y)(Z + W) using only NAND gates. 2 CO1
Q2 A) Identify Machine cycles and Execution time required for an instruction STA 2065H, 3 CO2
if a crystal used to generate operating frequency 8085 is 5MHz in 8085?
Soln:
Page 1 of 3
M/C = 4, T states = 13 (4+3+3+3), Operating frequency (F)= 5/2 = 2.5MHz, T = 1/F =
1/2.5 = 0.4microSec, Exe Time = 13 x 0.4 = 5.2 microSec
B) Use suitable address decoding scheme and interface 4K EPROM with 8085. 5 CO2
Soln:
8085 (IO/M’, RD’, A0 to A15, D0 to D7, ALE), 3 to 8 decoder for chip select, Latch
for separating multiplexed address and data lines, Bubbled NAND gate to generate
MEMR’ signal to enable output of 4K EPROM chip.
C) Specify content of registers used and flag status after execution of following sequence 5 CO1
of instructions, assume initially (at START) all flags are reset.
START: MVI D, 9BH
MVI E, A7H
MOV A, D
ADD E
ORA A
HLT
Soln: S Z AY P CY
MVI D, 9BH; D=9BH, 0 0 0 0 0
MVI E, A7H; E=A7H 0 0 0 0 0
MOV A, D; A=9BH 0 0 0 0 0
ADD E; A=9BH + A7H = 42H 0 0 1 1 1
ORA A; A=(9BH + A7H) OR 9BH = 42H 0 0 0 1 0
HLT; EXE STOP
Q3 A) Assume accumulator holds data AAH and all flags are clear; illustrate the 3 CO2
accumulator content after the execution of RAL instruction twice.
Soln:
1) A = AAH = 10101010 and CY = 0
RAL; A = 01010100 = 54H and CY = 1
2) A = 54H = 01010100 and CY = 1
RAL; A = 10101001 = A9H and CY = 0
B) Identify the memory locations that are cleared after execution of following sequence 2 CO1
of instructions?
MVI B, 00H
LXI H, 1075H
MOV M, B
INX H
MOV M, B
HLT
Soln:
1075H and 1076H memory will be cleared.
C) Calculate the COUNT in HEX to obtain 50microSec loop Delay, where operating 4 CO2
frequency is 5MHz.
MVI B, COUNT
*NOP
NOP
DCR B
Page 2 of 3
JNZ *
HLT
Soln:
NOP = 4T, DCR B = 4T and JNZ = 10/7T
Loop T states = 22, JNZ with (-3T is neglected as small compare to total T)
For single exe of loop time required is = 22 * 1/5MHz
D) What would be the Stack memory content/status after execution of following CO2
instructions?
LXI SP, 2400H
LXI H, 2150H
LXI B, 2280H
MOV A, M
PUSH H
PUSH B
PUSH PSW
Soln:
23DFH
(Flag Reg.) 23EFH
(A) 23FAH
80 23FCH
22 23FDH
50 23FEH
21 23FFH
TOS 2400H
Q4 A) Specify which addressing mode is used in the instruction MOV AX, 50[BX][SI]? and 3 CO3
calculate physical address of data, if DS=A000H, BX=2000H, SI=3000H.
Soln:
Relative Based Indexed
Physical Address = 10H*DS+[BX]+[SI]+50H
B) What do you mean by pipelined architecture? How it is implemented in 8086? 4 CO3
Soln:
The 8086 has 6 byte instruction prefetch queue, thus even the largest instruction can
be prefetched from the memory and stored in the prefetch queue. This results in a
faster execution of instructions.
C) Write long forms of following 8086 instructions. 3 CO1
i) RCL: Rotate Left through Carry
ii) CMPS: Compare string byte or string word
iii) DAS: Decimal Adjust after Subtraction
⋅ ⋅ ⋅ ⋅ ⋅ End of question paper ⋅ ⋅ ⋅ ⋅ ⋅
45
Page 3 of 3
