A Curvature Compensated Bandgap Reference with

low Drift and low Noise

Junmin JIANG, Student Member, IEEE, Zhihua NING and Lenian HE
Institute of Very Large Integrated Circuits
Zhejiang University
Hangzhou 310027, China
Email: zjujjm@[Link],{ningzh, helenian}@[Link]

Abstract—A low temperature drift and low noise curvature- large number of switches leads larger die area. Malcovati[3]
compensated CMOS bandgap reference is proposed. A dual- uses VEB linearization technique to compensate high-order
differential input pair amplifier was employed to add compen- terms of bandgap reference with current mode structure. It
sation with a high-order term of T ln T to the traditional 1st-
order compensated bandgap. To reduce the offset of amplifi- needs trimming circuits of 1st-order and high-order separately,
er and output noise of bandgap reference, input differential increasing the complexity of trimming operation.
pairs are large-sized PMOS. With a low dropout regulator Voltage reference based on ΔVgs was proposed[4]. The
stage, the voltage reference was increased to 3V. The voltage reference only uses MOSFETS in CMOS technology, which
reference’s temperature curvature is further corrected by 8-bit improves the simplicity of circuit design. However, VREF
resistor trimming network. To avoid degrading the precision,
noise performance is properly taken into account. The chip in[4] depends on process parameters, thus, the magnitude
was fabricated by using TSMC’s 0.35μm CMOS process. The might vary[5]. It was suggested that among various device
temperature coefficient was measured only to be 2.1 ppm/◦ C parameters in semiconductor technologies, the characteristics
over -40∼125 ◦ C after trimming. The output noise is 42 μVrms of bipolar transistors have proven to be the most repoducible
from 0.1Hz to 10Hz. and well-defined quantities that can provide positive and
Index Terms—Voltage Reference, Bandgap, Curvature-
compensation, Low drift, Low noise, Dual-differential input pair negative TCs[6]. Therefore, bipolar operation still forms the
amplifier core of this voltage reference.
For high precision applications, the noise generated by
I. I NTRODUCTION integreted devices and from power supply will degenerate the
performance of voltage reference, thereby affect the static and
In high precision systems such as singal processing systems, dynamic performance of certain systems. For data converters,
power converters and RF circuits, the best performance totally the parameters of Signal-to-Noise Distortion Ratio (SNDR)
depends on the accuracy of reference. It is the reason why and Spurious-Free Dynamic Range (SFDR) are sensitive to
voltage reference is the vital block in electronic systems. noise. Therefore, if noise is not properly taken into account,
CMOS bandgap reference is a popular implementation of the performance of systems that can be achieved might be
voltage references. The reference is required to be temperature misevaluated.
independent and stable with variation of process. For instance, This paper proposes a new structure of bandgap reference.
data converters require a voltage reference with less than 1 Reference is compensated with 1st-order and high-order terms
LSB error to guarantee the accuracy. For data converters whose to reduce temperature drift. Trimming with a switched resistor
operating temperature ranges from -40 ∼ 125◦ C, 1 LSB error network is also used to minimize the process deviation. In our
is 240 ppm for 12-bit and 12 ppm for 16-bit. design considerations, noise is an important factor. The impact
In order to reduce the temperature drift of voltage refer- of noise is presented and optimization for decreasing noise is
ences, several creative methods for bandgap reference have proposed. The measurement results and conclusion are given
been proposed[1]-[4]. A resistor ratio between a high-resistive finally.
poly-silicon resistor and a diffused resistor was used to provide
high-order compensation[1]. However, the resistor’s tempera- II. P ROPOSED BANDGAP R EFERENCE
ture cofficient varies quiet a lot with process variation. It’s Fig. 1 shows the circuits of bandgap reference proposed
possible to hold the value of TC to tolerances of better than by this paper, which contains three parts: bandgap core,
250 ppm/◦ C for a poly resistor. Therefore, in [1], a complex low dropout regulator (LDO) and curvature compensation
trimming circuit is required in order to obtain a high precision circuit. The bandgap core generates proportional-to-absolute-
reference for the design. Six temperature measurements are temperature (PTAT) currents I1 and I2 flowing through Q1
needed during one trimming operation[1]. Atrash[2] uses and Q2 , respectively, while the curvature compensation circuit
switching techniques to reduce offsets of the op-amp and produces a complementary-to-absolute-temperature (CTAT)
current source devices. Still, the design only use 1st-order current I3 which flows through Q3 . Therefore, ΔVEB the
compensation and its drift is larger than 10 ppm/◦ C. Also a differential value of emitter-base voltage between Q1 and

978-1-61284-865-52011
c IEEE 547
 9'' Thus, the drain current of M9 to M12 can be expressed as:
 
W
enVSGn1
0
0 In1 = 400I0 (2)
L
 
5
W
Ip1 = 400I0 enVSGp1 (3)
L
%* /'2

 
9RXWSXW

W
In2 = 20I0 enVSGn2 (4)
L
5 0 0

 
5 5
W
5 Ip2 = 20I0 enVSGp2 (5)
S
, , ,
L
Q

0 GXDO2S$PS 5 As shown in Fig. 2, the load current mirror consists of

S
Q
MN13 and MN14. The multiplier of MN13 and MN14 are
equal. So when MN13 and MN14 working in balanced status,
their IDS should be same. Therefore, we can obtain:
4 4 4 5
P 1 P 
*1'

%DQGJDS&RUH /'2 &XUYDWXUH&RPSHQVDWLRQ In1 + In2 = Ip1 + Ip2 (6)

Fig. 1. Proposed bandgap reference Two differential pairs’ tail current mirror’s ratio is 10. Thus,
we can obtain:
9''
In1 + Ip1 = 10(In2 + Ip2 ) (7)

0 0
From the schematic as seen in Fig. 1, the amplifier’s input
9E
P  nodes voltages are:
VG,n1 = VEB1 + I1 R1 (8)
Q 0 0 S Q 0 0 S VG,p1 = VEB2 (9)
P  P  P  P 
VG,n2 = VEB3 (10)
VG,p2 = VEB1 (11)
9R

Caculate from Eq. (2) to (11),the final reference output

voltage is[7]:
0 0  
2R3 + 3R4
P  P 
VREF = VEB1 + 1 + (VEB2 − VEB1 )
R1
 
2R3 + 3R4 R4 ξT ln T
+ 1+ + (12)
Fig. 2. Structure of dual-pair op amp R1 R3 10
where VEB2 − VEB1 is the PTAT current term, which can
provide 1st-order compensation. T ln T is the high order term
Q3 is a high-order term associated with temperature, which compensation to VEB . Then Eq. (12) could be simplified as
was added to traditional 1st-order temperature compensated follows:
bandgap by dual differential-pair amplifier in bandgap core. VREF = VEB1 + αT + βT ln T (13)
A LDO is also integrated for driving ability and provides a where,  
stable power supply for curvature compensation circuit. 2R3 + 3R4 k
The structure of the dual-pair amplifier is shown in Fig. 2. α= 1+ ln(2N ) (14)
R1 q
The size of input differential transistors is very large, which  
would reduce the amplifier’s offset and 1/f noise. Moreover, 1 2R1 + 3R4 R4
β= 1+ + ξ (15)
the input differential pairs are working in weak inversion 10 R1 R3
region to keep a low quiescent current. III. N OISE A NALYSIS
When PMOS works in weak inversion region, its drain
For high precision applications, the noise generated by
current can be given as[6]:
integreted devices and from power supply will degenerate the
W VSG W
I0 e ξVT =
IDS = I0 enVSG (1) performance of voltage reference, thereby affect the static and
L L dynamic performance of certain systems. Therefore, if noise
Where ξ is the process parameter and usually 1 < ξ < 3, performance is not properly taken into account, the perfor-
n = ξV1T . I0 is the drain current value when VSG = 0. W
L is mance that can be achieved might be misevaluated. There is a
the width and length ratio of PMOS. tradeoff among TC performance, noise and power dissipation.

548 2011 International Symposium on Integrated Circuits

 TABLE I
N OISE CONTRIBUTION IN C IRCUIT
0 ,Q

9JP
Device Parameter % Device Parameter %
0'
 OP.MN13 Flick Noise 43.05 OP.MN14 Flick Noise 42.85
5
287 OP.MP7 Flick Noise 7.34 OP.MP12 Flick Noise 1.73
OP.MP11 Flick Noise 1.73 OP.MP8 Flick Noise 0.77
5 5
OP.MP9 Flick Noise 0.22 OP.MP10 Flick Noise 0.22
0'
Req Thermal 0.06 OP.MN13 Thermal 0.03
OP.MN14 Thermal 0.03 Others 1.97
95HT 9S 9S 5

4 4 t0 t1 t2 t3 t4 t5 t6 t7 k7 k6 k5

k4

GND k3
Fig. 3. Noise analysis model
B k2
Vout
A k1

In order to get better TC performance, curvature compensation Avdd C D

k0

circuits and resistors’ trimming circuits are added into design, Dvdd
VBG
which brings in more power dissipation and noise. In this
paper, we try to evaluate the circuit’s noise performance and A:BGR B:Trimming
C:LDO D:Capacitor
present the method of optimization.
As shown in Fig. 1, the bandgap reference output is connect- Fig. 4. Chip mircophotograph
ed to current source which is decided by the gate voltage of
M2, then all noise sources can be modeled by a noisy source
at this point as v̄g,M2 . Because of dual-pair input structure, op
amp’s input referred noise could be considered as two parts In our design, gm,Q1 and gm,Q2 are constant in the circuit.
v̄p1 and v̄p2 . Also MP12 and MP11’s muliplier is far less To decrease the output noise v̄o , the resistors R1 R2 R3
than MP10 and MP9’s, therefore, the noise from curvature and Req should be decreased. It requires the current source
compensation could be ignored. Then the main noise sources to provide more current in the reference’s output branch.
of this circuit are amplifier’s input referred noise v̄p1 and v̄p2 , Additionally, reducing resistance reduces the chip size. In our
current mirror noise of M2 īn,M2 and equivalent resistors’ proposed bandgap reference in Fig 1, R1 is 10.53kΩ, R2 is
thermal noise v̄Req . The noise analysis model is built as shown 35.81kΩ, R3 is 17.9kΩ. As seen in Eq. (12), VREF depend
in Fig. 3. Thus, we can obtain: on the ratio of R1 R3 and R4 . These resistors’ absolute value
 2
2 2 1 R3 gm,Q2 + 1 could be decreased to get a better noise performance without
v̄g,M2 = v̄p1 affecting TC performance.
gm2 Req
 2 Table I is the simulation result of the output noise contribu-
2 1 (R1 + R2 )gm,Q1 + 1
+v̄p2 tion. From Table I and Eq. (18), the output noise is mainly due
gm2 Req
to dual pair input amplifier’s input referred noise v̄p1 and v̄p2 .
4kT 1 ī2n,M2
+ + 2 (16) It is possible to see that the dual-pair amplifier is the major
Req + R4 gm22 gm2 noise generator in bandgap reference, producing more than
where 97% of the noise in circuit. Because the input refered noise
    of dual-pair amplifier is amlified by the closed-loop gain.[8]
1 1
Req = R1 + R 2 + // R3 + (17)
gm,Q1 gm,Q2 From the Table I, we can also see that most of the noise
comes from 1st-stage of amplifier. In consideration of noise,
gm2 is the transconductor of M2. gm,Q1 and gm,Q2 are the
we make input pair PMOS a very large size to reduce flick
transconductor of PNP transistors of Q1 and Q2 , respectively.
noise. As a consequence, the load devices of current mirror
Consequently, the output noise is:
MN13, MN14 become the major noise sources. If the tran-
v̄o2 = 2
v̄g,M2 (gm2 Req )2 sistor operates as a constant current sources, it is required to
2
= v̄p1 (R3 gm,Q2 + 1)2 minimize its transconductance to reduce current mirror load’s
2 2 flick noise[6]. Therefore, the transconductance of MN13 and
+v̄p2 [(R1 + R2 )gm,Q1 + 1] MN14 should be decreased, as the tail current remains the
2
4kT Req same. But the amplifier’s operation headroom will decrease
+ + ī2n,M2 Req
2
(18)
Req + R4 correspondingly.

2011 International Symposium on Integrated Circuits 549

 −5
3.001 x 10
1.6
3.0008
1.4
3.0006
1.2

Noise Output (V/sqrt Hz)

Reference Voltage (V)

3.0004
1
3.0002
0.8
3
0.6
2.9998
0.4
2.9996
0.2
2.9994

0
2.9992 10
−1 0
10
1
10 10
2
10
3 4
10
5
10
6
10
7
10
−40 −20 0 20 40 60 80 100 120
Temperature (degree C) Frequency (Hz)

Fig. 5. TC Simulation result of voltage reference for temperature as function Fig. 7. Optimiezed output noise density of reference
of -40 to 125◦ C

3.006
V. C ONCLUSIONS
A low temperature drift, low noise bandgap voltage ref-
3.005
erence fabricated in TSMC’s 0.35-μm CMOS process has
been presented. The design considerations are minimizing the
3.004
temperature drift and the noise. A dual pair input amplifier
Reference Voltage (V)

3.003
is used to add compensation with a high-order iterm of
T ln T to the tranditional 1st-order compensated bandgap. The
3.002
expression of output reference has benn calculated in detail.
Noise analysis of bandgap circuit is made. To reduce the
3.001 noise of the bandgap reference, input differential transistors
of large size in amplifier are employed and they all work
3
−40 −20 0 20 40 60 80 100 120 in weak inversion to reduce power dissipation. The best TC
of reference is only 2.1ppm/◦ C over -40 to 125◦ C. and
Temperature (degree C)

Fig. 6. TC Testing result of voltage reference for temperature as function the noise is 42μV rms over the frequency of 0.1Hz to 10Hz.
of -40 to 125◦ C. +  × and ♦ stand for four measured chips. The performance make the reference very attractive for high
precision application.
R EFERENCES
IV. M EASUREMENT R ESULTS [1] N. L. Ka, P. K. T. Mok, and Y. L. Chi, “A 2-V 23-μA 5.3-ppm/◦ C
curvature-compensated CMOS bandgap voltage reference,” IEEE Journal
of Solid-State Circuits, vol. 38, no. 3, pp. 561– 564, 2003.
[2] A. H. Atrash and A. Aude, “A bandgap reference circuit utilizing
The proposed voltage reference has been implemented by switching to reduce offsets and a novel technique for leakage current
using TSMC’s 0.35μm CMOS process. The chip micropho- compensation,” in The 2nd Annual IEEE Northeast Workshop on Circuits
tograph is show in Fig. 4. The chip area is 0.4mm2 . A B C and Systems, 2004. NEWCAS 2004., ser. Circuits and Systems, 2004.
NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on, 2004,
and D in Fig. 6 indicate the area of bandgap-core, trimming pp. 297– 300.
cricuit, LDO and capacitor in the chip, respectively. 28 chips [3] P. Malcovati, F. Maloberti, C. Fiocchi, and M. Pruzzi, “Curvature-
from different areas of the same Multi-Project Wafer (MPW) compensated BiCMOS bandgap with 1-V supply voltage,” Solid-State
Circuits, IEEE Journal of, vol. 36, no. 7, pp. 1076–1081, 2001.
have been measured. Fig.5 is the simulation result of TC [4] N. L. Ka and P. K. T. Mok, “A CMOS voltage reference based on
performance. Fig. 6 shows the measurement results of TC weighted ΔVGS for CMOS low-dropout linear regulators,” IEEE Journal
performance by setting trimming bits. Measurement results of Solid-State Circuits, vol. 38, no. 1, pp. 146– 150, 2003.
[5] P. K. T. Mok and N. L. Ka, “Design considerations of recent advanced
are connected by smoothing curves. The trend of curves low-voltage low-temperature-coefficient CMOS bandgap voltage refer-
meets the expectation. The temperature varition is from - ence ,” in Custom Integrated Circuits Conference, 2004. Proceedings
40 to 125◦ C. When setting trimming bits samely, the chips’ of the IEEE 2004, ser. Custom Integrated Circuits Conference, 2004.
Proceedings of the IEEE 2004, 2004, pp. 635 – 642.
smallest temperature drift is only 2.1 ppm/◦ C. To achieve a [6] B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw-Hill
more precise reference, each chip was trimmed separately. In Education, 2000.
this case the best value of TC is only 1.1 ppm/◦ C. All chips’ [7] Z. Ning and L. He, “A low drift curvature-compensated bandgap ref-
erence with trimming resistive circuit,” Journal of Zhejiang University-
TC are small than 7 ppm/◦ C. SCIENCE, 2011.
Fig. 7 is the simulation result of output noise after opti- [8] D. Colombo, G. Wirth, S. Bampi, and C. Fayomi, “Impact of noise on
trim circuits for bandgap voltage references,” in 14th IEEE International
mization. The figure shows that the typical output noise is Conference on Electronics, Circuits and Systems, 2007. ICECS 2007.,
16.01μVrms from 0.1Hz to 10Hz. The measurement result of ser. Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE
noise was found to be 42μVrms from 0.1Hz to 10Hz. International Conference on, 2007, pp. 775–778.

550 2011 International Symposium on Integrated Circuits