7/11/22, 4:07 PM Quiz #2: Xem lại lần làm thử

Kien truc may tinh va hop ngu_ Nhom 02CLC

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/ Chapter 4: The Central Processing Unit / Quiz #2

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Kết thúc lúc Monday, 11 July 2022, 4:02 PM
Thời gian thực 39 phút 48 giây
hiện

Câu hỏi 1
Hoàn thành

Đạt điểm 1,00

Which set of registers point to the next instruction?

Select one:
CS:IP

CS:PC

CS:IR

ES:IP

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Câu hỏi 2
Hoàn thành

Đạt điểm 1,00

Select correct match for carry and sign flag at watch points:
MOV AX, 4FCA

ADD AX, DDA9

watch point #1:

ADD AH, F3
watch point #2:

......

watch point #1 - Carry Flag

set

watch point #1 - Sign Flag

not set

Câu hỏi 3
Hoàn thành

Đạt điểm 1,00

Which ones are not correct for static RAM?

Select one or more:

faster than dynamic RAM because they are made from capacitor

Cost per bit is higher than dynamic RAM

Cheaper than dynamic RAM because simpler chip controller

Cost per bit is lower than dynamic RAM

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Câu hỏi 4
Hoàn thành

Đạt điểm 5,00

A 512 KB cache memory that organized in 256-bytes blocks, operates along with the main memory of 4GB.

1. The number of address bits used to index the main memory:

32

2. The number of bits used to index a particular memory block:

24

3. The number of bits used to index the cache:

32

4. The number of bits used to index every cache line:

24

5. The number of bits used to index every single byte on a cache line:

Câu hỏi 5
Không trả lời

Đạt điểm 2,00

A computer system has main memory size = 16MB with 16 bytes block size. The direct-mapped cache memory operates alongside having
212 cache lines.

Consider 2 consecutive bytes in the main memory starting at 0xad0134

The tag bits would be (binary)

, and cache index for the 1st byte would be (hex) 0x

(hex digit in lowercase)

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Câu hỏi 6
Hoàn thành

Đạt điểm 1,00

Select correct match for register values at watch points:

MOV AX, 152D

ADD AX, 003F

watch point #1:

ADD AH, 10

watch point #2:

......

watch point #1:

AH = 25

watch point #2:

AH = 25

Câu hỏi 7
Không trả lời

Đạt điểm 2,00

A computer system has main memory size = 4MB with 16 bytes block size. The direct-mapped cache memory operates alongside having
212 cache lines.

Consider 2 consecutive bytes in the main memory starting at 0x3f15ab.

The tag bits would be (binary)

, and cache index for the 1st byte would be (hex) 0x

(hex digit in lowercase)

Câu hỏi 8
Không trả lời

Đạt điểm 1,00

Select the correct sequence of instructions to compute -1024/128 (all values are in hex).

Step 1:
Chọn...

Step 2:
Chọn...

Step 3:
Chọn...

Step 4:
Chọn...
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Câu hỏi 9
Hoàn thành

Đạt điểm 1,00

In 16-bit real mode, which set of registers are valid for addressing a memory location?

Select one or more:

SS:DI

DS:SI

DS:BX

CS:IP

Câu hỏi 10
Hoàn thành

Đạt điểm 1,00

Choose correct features for SRAM and DRAM

DRAM
Faster access time, cost more per bit, smaller size

SRAM
Slow access time, cheaper cost per bit, can only manufacture at larger size

Câu hỏi 11
Hoàn thành

Đạt điểm 1,00

The following sequence of instructions is executed. What is the correct values at watch point?

MOV AX, 0x67FE

MOV BX, AX

MOV CL, BH

MOV CH, BL

watch point:

BX =
0x67FE

CX =
0xFE67

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Câu hỏi 12
Hoàn thành

Đạt điểm 1,00

The following sequence of instructions is executed. What is the correct value of flag bits at watch point?

MOV AL, 0x0F

ADD AL, 0xF1

watch point:

Carry flag (CF) = set

Zero flag (OF) =

set

Câu hỏi 13
Hoàn thành

Đạt điểm 1,00

Which of the following instructions are not legal addressing?

Select one or more:

mov eax, dword[esp+1]

mov ecx, dword[esi]

mov eax, dword[ebx+esp]

mov eax, dword[edi]

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Câu hỏi 14
Hoàn thành

Đạt điểm 5,00

A 4MB cache memory that organized in 256-bytes blocks, operates along with the main memory of 16GB.

1. The number of address bits used to index the main memory:

34

2. The number of bits used to index a particular memory block:

14

3. The number of bits used to index the cache:

4. The number of bits used to index every cache line:

14

5. The number of bits used to index every single byte on a cache line:

Câu hỏi 15
Hoàn thành

Đạt điểm 1,00

Match the correct definition of flag bits in PSW.

indicates the overflow of leftmost bit of data after an arithmetic operation

AF

contains the carry from bit 3 to bit 4 following an arithmetic operation OF

shows the sign of the result of an arithmetic operation

CF

indicates the result of an arithmetic or comparison operation SF

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Câu hỏi 16
Hoàn thành

Đạt điểm 1,00

Select correct definition of seek time, rotational delay, access time, transfer time for hard drives with moveable-head system:

seek time
time for the head to settle at the request track

access time
seek time + rotational delay

rotational delay
time for the sector in the request track to reach the head

Câu hỏi 17
Hoàn thành

Đạt điểm 4,00

A 256KB direct-mapped cache organized in 64-byte lines. The main memory size is 8MB.

1. The number of Tag bits of the cache is

2. The number of bits used to index a particular cache line:

12

3. The number of bits used to index the cache:

17

4. The number of bits used to index every single byte on a cache line:

34

Câu hỏi 18
Hoàn thành

Đạt điểm 1,00

Bus is a shared transmission medium, multiple devices connect to it but only one at a time can successfully transmit. Which component in
computer facilitates this operation?

Select one:
Programmed I/O

Bus Arbiter

Bus master

Direct Memory Access (DMA)

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Câu hỏi 19
Hoàn thành

Đạt điểm 1,00

Given a row of memory image viewed in gdb

0xbfff8120 13 96 D0 E0 D0 E0 A2 1E - 99 80 3E 20 99 00 75 24
Initially, eax=ebx=ecx=edx=0, esi=0xbfff8121

What are value of cx,dx after execution of the following instructions?

mov dx, word[esi]
mov cx, word[esi+2]

DX =
D096

CX =
D0E0

Câu hỏi 20
Hoàn thành

Đạt điểm 1,00

What are the features of direct-mapping cache organization?

Select one or more:

small cache memory

faster

Thrash --> low hit ratio

Simple and inexpensive

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Câu hỏi 21
Hoàn thành

Đạt điểm 4,00

A direct-mapped cache comprised of 1024 lines works alongside the main memory of 8MB.
Assume the cache memory has 6-bit tags, therefore:

1. The cache memory size is

(KB)
2. The number of bits used to index a particular cache line:

10

3. The number of bits used to index the cache:

16

4. The number of bits used to index every single byte on a cache line:

29

Câu hỏi 22
Không trả lời

Đạt điểm 2,00

Consider a 4-way set associative mapped cache of size 64 KB with block size 512 bytes. The size of main memory is 4MB.

Find:
1. Number of bits in tag

2. Tag directory size

bytes

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Câu hỏi 23
Hoàn thành

Đạt điểm 1,00

A processor with 16-bit instruction set. The instructions comprise 2 fields: opcode is in the first 8 bits while operand/operand address
stores in the last 8 bits.
What is the maximum directly addressable memory capacity?

Select one:
256

512

256K

1024

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