AMERICAN INTERNATIONAL UNIVERSITY BANGLADESH
Faculty of Engineering
Laboratory Report Cover Sheet
Students must complete all details except the faculty use part.
Please submit all reports to your subject supervisor or the office of the concerned faculty.
Laboratory Title: Design of adder and comparator circuits__________________
Experiment Number : 03___ Due Date: _23/03/25_ Semester: spring 2025______________
Subject Code: EEE 3102 Subject Name: Digital Logic & Circuits Laboratory Section: G_
Course Instructor: MD. ASHIQUZZAMAN Degree Program: BSC in CSE
Declaration and Statement of Authorship:
1. I/we hold a copy of this report, which can be produced if the original is lost/ damaged.
2. This report is my/our original work and no part of it has been copied from any other student’s work or from
any other source except where due acknowledgement is made.
3. No part of this report has been written for me/us by any other person except where such collaboration has
been authorized by the lecturer/teacher concerned and is clearly acknowledged in the report.
4. I/we have not previously submitted or currently submitting this work for any other course/unit.
5. This work may be reproduced, communicated, compared and archived for the purpose of detecting
plagiarism.
6. I/we give permission for a copy of my/our marked work to be retained by the school for review and
comparison, including review by external examiners.
I/we understand that
7. Plagiarism is the presentation of the work, idea or creation of another person as though it is your own. It is a
form of cheating and is a very serious academic offence that may lead to expulsion from the University.
Plagiarized material can be drawn from, and presented in, written, graphic and visual form, including
electronic data, and oral presentations. Plagiarism occurs when the origin of the material used is not
appropriately cited.
8. Enabling plagiarism is the act of assisting or allowing another person to plagiarize or to copy your work
Group Number (if applicable): Individual Submission Group Submission
No. Student Name Student Student Date
Number Signature
Submitted by:
1 Md Ratul Hasan Siam 23-51052-1
Group Members:
2 Hamed Mohammed Adel 23-55566-3
3 Tania Akter Jasy 23-51594-2
4 Eva Jahan 23-55536-3
5 Zannatul Adon 20-42796-1
1. ABSTRACT:
The purpose of this experiment is to learn the design and behavior of adders, subtractor and
comparator logic circuits. Adders and subtractors are the most basic and most important part of
digital electronics.
Part I (Adder): Adders and subtractors are digital circuits which are capable of adding and subtracting
binary digits. They are the most important part in the design of Arithmetic Logic Unit (ALU). In this
experiment different types of adders and subtractors will be designed and their behavior will be observed.
2. INTRODUCTION:
The purpose of this experiment is to learn the design and behavior of adder, subtractor and comparator
logic circuits. In digital circuits, an adder subtractor is a circuit that is capable of adding or subtracting
numbers (inparticular, binary). It is also possible to construct a circuit that performs both addition and
subtraction at the same time. Below is a circuit that adds or subtracts depending on a control signal. They
are the most important part in the design of Arithmetic Logic Unit (ALU). In this experiment different
types of adders and subtractors will be designed and their behavior will be observed. The design and
analysis of adder, subtractor, and comparator circuits are fundamental to understanding digital systems
and their operations. Adders and subtractors are essential components capable of performing binary
arithmetic operations such as addition and subtraction.
A versatile adder-subtractor circuit can perform both functions, depending on a control signal, making it a
key element in optimizing space and functionality in digital designs. Comparators, on the other hand, are
logic circuits that compare two binary numbers to determine their relationship, such as greater than, less
than, or equal to. These circuits are crucial in decision-making processes and control systems. Together,
adders, subtractors, and comparators form the building blocks of an Arithmetic Logic Unit (ALU), the
core of microprocessors. This experiment focuses on designing and analyzing these circuits to understand
their behavior and functionality. By exploring their design, we gain insights into the principles of digital
logic, Boolean algebra, and practical applications in computational systems.
3. THEORY AND METHOLOGY:
An adder or summer is a combinational circuit that adds binary numbers. There are mainly two
kinds of adders, half adder and full adder. The half adder can add only two single bits of binary
digit and outputs the sum of the bits and a carry which is the overflow of the sum. A full adder
can add two single bit digits and one carry bit which is the overflow of the sum of the previous
stage of addition and outputs the sum and the carry.
A
B
in
A
SB
C
Half Adder Full Adder
Fig.1.1: Schematics of Half Adder and Full Adder
The Boolean expression for half and full adder is given below –
Half Adder:
S =A B
Cout = AB Full
Adder:
S = A B Cin
Cout = Cin (A B) + AB
Table 01: Truth table for half adder –
Inputs Outputs
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Table 02: Truth table for full adder –
Inputs Outputs
A B Cin S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Using Full Adder blocks for addition of n- bit systems:
Full adder blocks can be connected for summation of n-bit systems. To design a 2-bit full adder,
two 1-bit full adders are connected in parallel connection as shown in the figure below. The
same process can be used for designing n-bit Full Adder for addition of words having a length
of n-bits.
Fig. 1.3: 2-bit Full adder design using 1-bit full adder blocks
Here, the LSB of both word A and B (A0 and B0) are connected in the first stage full adder
block and Cin of this block (Cin0) is connected to ground (as there is no carry in available at
the initial stage). The MSB of both word A and B (A1 and B1) are connected in the first stage
full adder block and Cin of this block (Cin1) is connected to the previous stage Cout (Cout0).
Summation output for the LSB is available from the first stage Sum (S0). The next stage block
outputs Sum (S1) and carry out (Cout1) provide the MSBs for the next stage output (S1 and
and S2).
Part II (Comparator): A magnitude comparator is a device that takes in two sets of inputs in
its input and compares them to provide an output, if they are equal, greater than or less than the
other. In this experiment 1-bit comparator will be designed at first and using the 1-bit
comparator block, 2-bit comparator will be designed.
Theory and Methodology: Magnitude Comparators are combinational logic circuits that take
2 sets of data as its inputs and tests whether the value represented by one binary word is greater
than, less than, or equal to the value represented by another binary word.
Fig.2.1: Block Diagram of 1 Bit Magnitude Comparator
Depending on the input combination for a 1-bit magnitude comparator, the following behavior
table can be developed using the logic expressions.
A=B if, A=B=0 or A=B=1;
A>B if A=1 and B=0;
A<B if A=0 and B=1;
Table 3: Truth table of 1-bit magnitude comparator
Inputs Outputs
A B A=B A>B A<B
0 0 1 0 0
0 1 0 0 1
1 0 0 1 0
1 1 1 0 0
The SOP expressions for the output lines can be written as
(A=B)= A’B’+AB;
(A<B)= AB’;
(A>B)=A’B;
Fig.2.2: 1-Bit Comparator
Fig.2.3: Timing Diagram for 1-Bit Comparator 2 Bit
Comparator design using 1 bit block:
Using 1-bit blocks, n-bit Magnitude comparator can be designed.
Fig.2.4: 1-Bit Comparator Block
Designing a 2-bit comparator using 1-bit blocks:
Let us consider 2 words,
Word A ->
A1A0 Word B-
> B1B0
For comparing, the following process is used as writing the logic equations.
For A=B,
If (A1=B1) & (A0=B0), then (A=B);
For A>B,
If (A1>B1) then (A>B) or if
(A1=B1) & (A0>B0), then (A>B);
For A<B,
If (A1<B1) then (A<B) or if
(A1=B1) & (A0<B0), then (A<B)
Fig.2.5: 2-Bit Comparator using 1_bit Comparator Block
Table 04: Truth table of 2-bit magnitude comparator
INPUT OUTPUT
A1 A0 B1 B0 A<B A=B A>B
0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0
For designing a 2-bit comparator using 1-bit comparator block, 2 1-bit comparator block, 3
AND gate and 2 OR gate is needed as shown in Fig.4.
Pin configuration of IC 74LS83:
Figure: 4-bit Full Adder IC pin configuration
Apparatus:
Serial No Name Image Model Quantity Remarks
1 Digital Trainer Board AL-E139 1 N/A
2 Integrated Circuits 7400, 7402,1 pcs each N/A
7404, 7408,
7432, 7486
3 Power supply TPR303-2D 1 N/A
4 Connecting Wires 10 N/A
Hardware Setup:
Figure 1: Full Adder
Figure 2 : full Adder (for different inputs)
Figure 03: Full Adder(for different inputs)
Figure 04: Full Adder (for different inputs)
Figure 05: Full adder (for different inputs)
Figure 06: full Adder (for different inputs)
Multisim Simulation:
Half Adder:
Fig 1: Half Adder Logic Circuit Diagram
Fig 2: Output for A=0, B=1 input combination
Fig 3: Output for A=1, B=1 input combination
Full Adder:
Fig 4: Full Adder Logic Circuit
Fig5: Output for A=0, B=0, Cin=1 input combination
Fig6: Output for A=1, B=1, Cin=0 input combination
Fig7: Output for A=1, B=1, Cin=1 input combination
1-bit Magnitude Comparator:
Fig 8: Output for A=0, B=0 input combination
Fig 9: Output for A=0, B=1 input combination
Fig 10: Output for A=1, B=0 input combination2-bit Comparator using 1-bit comparator block
Fig 11: Output for A=1, B=0 input combination2-bit Comparator using 1-bit comparator block 2-bit
Comparator using 1-bit comparator block:
Fig 12: Output for A=1 B=0, A1=1, B1=1 input combination
Fig 3.13: Output for A=0 B=0, A1=1, B1=1 input combination
Fig 14: Output for A=0, B=1, A1=0, B1=1 input combination
Fig 15: Output for A=0 B=1, A1=0, B1=1 input
combination
4. Discussion:
The design and implementation of adder and comparator circuits are fundamental in digital electronics. In
this experiment, the circuits for both were designed, simulated, and analyzed using NI Multisim software.
For the adder circuit, both half and full adders were considered. The half adder, which performs the
binary addition of two inputs (A and B), generates a Sum (S) using an XOR gate and a Carry (C) using an
AND gate. Extending this, the full adder incorporated a third input, Carry-in (C_in), and used a
combination of XOR and AND gates to calculate the Sum and Carry-out (C_out), allowing for cascaded
multi-bit additions. For the comparator circuit, the focus was on comparing binary inputs A and B to
determine whether A > B, A < B, or A = B. The design involved basic logic gates to implement Boolean
equations, where outputs like A>BA > B, A<BA < B, and A=BA = B were derived and verified. Multi-bit
comparators required cascading individual 1-bit comparators, starting with the most significant bit (MSB)
to ensure accuracy. The outputs were matched with the derived truth table. During simulating we faced
some difficulties but with the help of our course instructor we were able to troubleshoot all of them. We
learnt from our mistake that we can’t connect ground with digital constant, using probe instead of led
gives better result. Although the experiment was conducted in an online lab environment due to pandemic
restrictions, the hands-on experience with Multisim provided valuable insights into digital circuit design,
troubleshooting, and simulation techniques. By achieving accurate outputs and successfully addressing
the report questions, the experiment fulfilled its objective of familiarizing students with adder and
comparator circuits, making it a valuable learning experience.
[Link]:
In conclusion, the experiment successfully achieved its objective of designing, simulating, and analyzing
adder and comparator circuits using Boolean algebra and logic gates. Using NI Multisim software, both
half and full adders, as well as 1-bit and multi-bit comparators, were implemented and their functionality
validated against truth tables. Despite facing initial challenges with circuit connections and signal
visualization, these were resolved with troubleshooting and instructor guidance, enhancing the learning
experience. The experiment provided a comprehensive understanding of the design principles, practical
challenges, and solutions in digital circuit implementation. The accurate simulation results and the ability
to address all report questions indicate the experiment’s success in meeting its goals and reinforcing core
concepts of digital electronics.
[Link]:
[1] "Half Adder and Full Adder," [Link]. [Link]
(accessed Nov. 23, 2024)
