COMPUTER ORGANIZATION

Lecture 5. Sequential Logic

Clocks, Flip-Flops, Registers
COMP2020
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Anne Bracy,

Cornell University and Prof. Rudy Lauwereins, KU Leuven for
sharing their teaching materials.

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COVERED IN THIS COURSE

Application
Operating
System

Compiler Firmware
Instruction Set
Memory I/O system Architecture
system CPU

Datapath & Control

Digital Design This lecture
Circuit Design

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 CAN YOU DO IT?

A vending machine accepts nickels (5 cents), dimes (10 cents),

and quarters (25 cents) towards the purchase of a can of soda.
When the machine has received 40 cents or more, it dispenses
a can of soda and returns any money over 40 cents. For
example, if someone puts in two quarters, one after another,
the machine returns a can of soda and 10 cents.

Design a digital circuit to control the machine.

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COMBINATIONAL VS. SEQUENTIAL CIRCUITS

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 SEQUENTIAL CIRCUITS
❑ Outputs depend on inputs and state variables

❑ The state variables embody the past history of the circuit

▪ Storage elements hold the state variables

❑ A clock periodically advances the circuit

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 SEQUENTIAL CIRCUITS
❑ Definitions
▪ Asynchronous sequential circuits: outputs and state change as
soon as an input changes
▪ Synchronous sequential circuits: outputs and state change only
when a special input, the clock, gets a certain value

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 CLOCK
❑ An input to a sequential circuit that changes output and
state values at a predetermined rate

❑ Triggering edge: Transition of the clock that captures

input data
▪ We mostly use the positive rising edge (L -> H) as triggering edge in this class
▪ Clock tick: Occurrence of a triggering edge

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 CLOCK PERIOD AND FREQUENCY
❑ Clock Period (cycle time): Time between successive
transitions in the same direction (e.g., L-> H)
▪ e.g., 1ms, 2ns, 500ps
❑ Clock Frequency: 1/period
▪ e.g., 1kHz, 500MHz, 2GHz

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 EDGE TRIGGERED STATE CHANGES

State changes at clock edge

positive edge-triggered

negative edge-triggered
Need to design edge-triggered storage
DFF

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 POSITIVE EDGE-TRIGGERED D FLIP-FLOP
• Data captured when clock low D Q
• Output changes only on rising edge
clk DFF
(i.e., Q=D on rising edge)

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 POSITIVE EDGE-TRIGGERED D FLIP-FLOP
• Data captured when clock low D Q
• Output changes only on rising edge
clk DFF
(i.e., Q=D on rising edge)

clk

Q
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 NEGATIVE EDGE-TRIGGERED D FLIP-FLOP
• Data captured when clock high D Q
• Output changes only on falling edge
clk DFF
(i.e., Q=D on falling edge)

clk

Q
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 REGISTERS

DFF • D flip-flops in parallel

D0
• shared clock
• Additional (optional) inputs:
DFF writeEnable, reset, …
D1

… 32-bit
DFF 32 reg 32
D31
> 1000 transistors dedicated to
clk keeping track of which instruction
clk needs to be executed
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 REGISTER FILE

Register File Reg 0

• N read/write registers (here N==32) Reg 1
• Indexed by register number
….
Reg 30
Registers
Reg 31
• Numbered from 0 to 31.
• Can be referred by number: x0, x1, x2, … x31
• May also see $0, $1, $2 or r0, r1, r2
• Convention, each register also has a name:
• x16 - x23 → s0-s7 ("s registers")
• x8 - x15 → t0 - t7 ("t registers")
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 WRITING TO THE REGISTER FILE
32
Register File
D
Reg 0
• N read/write registers Reg 1
….

…
• Indexed by 5-to-32
register number decoder Reg 30
Reg 31
How to write to one register in the register file? 00001
• Need a decoder 5
• Write enable signal prevents unintended writes RW W

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 READING FROM THE REGISTER FILE
Register File 32
Reg 0
• N read/write registers Reg 1
• Indexed by register number …. ….
Reg 30
How to read from one register? Need: Reg 31
(A) Encoder
(B) Decoder
(C) OR Gate
(D) XOR Gate
(E) Multiplexor

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 READING FROM A REGISTER

Register File Reg 0

• N read/write registers Reg 1 M 32
• Indexed by …. …. U QA
register number X
Reg 30
Reg 31

How to read from one register?

• Need a multiplexor 5
RA
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 READ FROM TWO REGISTERS
Register File Reg 0
• N read/write registers Reg 1 M 32
• Indexed by …. …. U QA
register number X
Reg 30
Reg 31

How to read from two registers? …. M 32

U QB
• Need 2 multiplexors! 5 X

RA 5 RB
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 COMPLETE REGISTER FILE
Register File D 32 32
Reg 0
• N read/write registers Reg 1 M 32
…. …. U QA

…
• Indexed by 5-to-32
register number decoder X
Reg 30
Reg 31
Implementation:
• D flip flops to store bits 5
• Decoder for each write port …. M 32
RW 5 U QB
• Mux for each read port
X

W RA 5 RB
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 COMPLETE REGISTER FILE

Register File
• N read/write registers
QA
DW 32
• Indexed by 32 Dual-Read-Port
register number Single-Write-Port Q
B 32
32 x 32
Implementation: Register File
• D flip flops to store bits
• Decoder for each write port
W RW RA RB
• Mux for each read port 1 5 5 5

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