• The I/O cell will ensure that the data is correctly transmitted or received,

using a tri-state driver to avoid interference when the pin is not in use.

MODULE 2
1. Goals and Objectives of Floor Planning.
Goals of Floor Planning:
1. Arrange the blocks on the chip: Place different functional parts of the chip
in an efficient way to reduce wiring and improve performance.
2. Decide the location of the I/O pads: Place input/output pads at strategic
locations for easy communication with external devices.
3. Decide the location and number of power pads: Ensure proper placement
of power pads to evenly distribute power across the chip.
4. Decide the type of power distribution: Design an efficient power grid to
supply consistent voltage and minimize losses across the chip.
5. Decide the location and type of clock distribution: Plan how the clock
signal is distributed to all parts of the chip, ensuring synchronization and
reducing delay.

Objectives of Floor Planning:

1. Minimize chip area: Reduce the chip's physical size to cut costs and increase
chip yield from the wafer.
2. Minimize delay: Reduce the time it takes for signals to travel across the chip,
improving performance.
3. Area vs. delay: Balance the trade-off between reducing the chip's area and
minimizing delays for optimal design.

2. Explain the Measurement of Delay in Floorplanning.

In the ASIC design process we need to predict the performance of the final
layout. In floorplanning we wish to predict the interconnect delay before we
complete any routing.
To predict delay we need to know the parasitics associated with interconnect:
the interconnect capacitance (wiring capacitance or routing capacitance) as well
as the interconnect resistance. At the Floor planning stage, we know only the
fanout (FO) of a net (the number of gates driven by a net) and the size of the
block that the net belongs to. We cannot predict the resistance of the various
pieces of the interconnect path since we do not yet know the shape of the
interconnect for a [Link], we can estimate the total length of the
interconnect and thus estimate the total capacitance. We estimate interconnect
length by collecting statistics from previously routed chips and analyzing the
results. From these statistics we create tables that predict the interconnect
capacitance as a function of net fanout and block size. A Floor planning tool can
then use these predicted-capacitance tables (also known as interconnect-load
tables or wire-load tables).

Figure shows that both interconnect delay and gate delay decrease as we scale down feature
sizes but at different rates. This is because interconnect capacitance tends to a limit of about 2
pFcm1for a minimum-width wire while gate delay continues to decrease.

(a) Interconnect lengths as a function of fanout (FO) and circuit-block size. (b) Wire-load
table. There is only one capacitance value for each fanout (typically the average value).
(c) The wire-load table predicts the capacitance and delay of a net. Net A and net B both have
a fanout of 1, both have the same predicted net delay, but net B in fact has a much greater
delay than net A in the actual layout.
• Typically between 60 and 70 percent of nets have a FO = 1.
• The distribution for a FO = 1 has a very long tail, stretching to
interconnects that run from corner to corner of the chip.
• The distribution for a FO = 1 often has two peaks, corresponding to a
distribution for close neighbors in subgroups within a block,
superimposed on a distribution corresponding to routing between
subgroups.
• A twin-peaked distribution at the chip level also, corresponding to
separate distributions for interblock routing (inside blocks) and intrablock
routing (between blocks).
• The distributions for FO > 1 are more symmetrical and flatter than for
FO=1
• The wire-load tables can only contain one number, for example the
average net capacitance, for any one distribution. Many tools take a
worst-case approach and use the 80- or 90-percentile point instead of the
average. Thus a tool may use a predicted capacitance for which we know
90 percent of the nets will have less than the estimated capacitance.
• We need to repeat the statistical analysis for blocks with different sizes.
For example, a net with a FO = 1 in a 25 k-gate block will have a
different (larger) average length than if the net were in a 5 k-gate block.
• The statistics depend on the shape (aspect ratio) of the block (usually the
statistics are only calculated for square blocks).
• The statistics will also depend on the type of netlist. For example, the
distributions will be different for a netlist generated by setting a
constraint for minimum logic delay during synthesis which tends to
generate large numbers of two-input NAND gates than for netlists
generated using minimum-area constraints.
4. Explain Channel Definition process in Floor planning and its
importance.

Channel Definition Process in Floor Planning:

The channel definition process in floor planning refers to determining the
regions between the placed blocks where interconnects (wires) will be
routed. These channels are essential spaces for routing the electrical
connections between various functional blocks on the chip.

Figure shows a floorplan of a chip containing several blocks. Suppose we cut along the
block boundaries slicing the chip into two pieces a). Then suppose we can slice each of
these pieces into two. If we can continue in this fashion until all the blocks are separated,
then we have a slicing floorplan b). Figure (c) shows how the sequence we use to slice the
chip defines a hierarchy of the blocks. Reversing the slicing order ensures that we route
the stems of all the channel T-junctions first.

(INCLUDE OTHER NECESSARY DIAGRAMS)

The channel definition involves:
1. Determining Space for Routing:
o After placing the functional blocks on the chip, the remaining area
between them is defined as the "channel" where wires can be
routed.
o Channels must be wide enough to accommodate all the necessary
interconnections, including signal, power, and ground lines.
2. Adjusting Channel Size:
o The width of the channels can be adjusted during floor planning to
ensure there is enough room for the required interconnects without
causing congestion or excessive delays.
 o The channel size is often influenced by factors such as block size,
routing requirements, and technology limitations.
3. Identifying Routing Layers:
o Channels are typically used for routing on multiple layers of metal
(in modern IC designs), with different layers dedicated to
horizontal or vertical routing.
o This process defines how signals will flow between blocks in each
layer and ensures that layers are not overly congested.
Importance of Channel Definition:
1. Efficient Routing:
o Proper channel definition ensures that interconnects can be routed
with minimal delay and congestion, leading to better signal
integrity and performance.
2. Minimizing Chip Area:
o Optimizing the size and arrangement of channels helps minimize
the chip's overall area, making the design more compact and cost-
effective.
3. Avoiding Signal Interference:
o Well-defined channels prevent overlapping or tangled wires,
reducing the risk of signal interference and ensuring reliable data
transmission between blocks.
4. Facilitating Power and Ground Routing:
o Channels are also essential for power and ground routing, which
ensures that the chip receives stable power supply and grounding
connections throughout.

4. Discuss the steps involved in power planning during floor planning.

Steps Involved in Power Planning During Floor Planning:
Power planning is a crucial step during floor planning in VLSI design, as it
ensures the chip receives a stable and sufficient power supply while minimizing
power loss and ensuring reliable operation. Here are the key steps involved in
power planning:
1. Determine Power Requirements:
• Estimate the total power consumption of the chip based on the
functionality and expected activity of each block (logic, memory, etc.).
• Identify power hotspots—areas that will consume the most power, such
as high-performance modules or blocks with intensive logic operations.
2. Decide the Number and Location of Power Pads:
• Power pads are the points on the chip where external power (VDD) and
ground (GND) are supplied.
• The number and location of power pads should be optimized to ensure an
even distribution of power across the chip, minimizing the voltage drop
and IR losses.
• Place power pads near critical blocks to ensure short, efficient power
delivery paths.
3. Design the Power Distribution Network (PDN):
• Plan the power grid that connects all the power pads to the blocks on the
chip.
• The power grid design should include horizontal and vertical metal
layers to distribute power evenly. Proper sizing of metal layers is
necessary to handle the current requirements and reduce resistance.
• Use decap cells (decoupling capacitors) strategically placed across the
chip to stabilize the power supply and smooth out voltage fluctuations.
4. Ensure Voltage Integrity:
• Voltage drop (IR drop) must be kept to a minimum to ensure each block
receives the required voltage for proper operation.
• Analyze the current density and power dissipation to identify regions
where voltage drop might occur and design the power grid accordingly.
• Use power rings or grids to provide a uniform voltage across the chip
and reduce the effect of power congestion.
5. Plan for Clock Power Distribution:
 • The clock network is also an important part of power planning, as the
clock distribution consumes significant power.
• Design the clock distribution network to minimize power loss while
ensuring low skew and delay.
• Proper power routing for the clock network ensures that all blocks receive
the clock signal with minimal delay, while also reducing the overall
power consumption.
6. Power-Aware Routing:
• Ensure that routing for both signal lines and power lines is done
efficiently, minimizing the power consumed by long signal paths or
unnecessary interconnects.
• Minimize wire resistance for power and ground paths by using wider
metal layers or lower-resistance materials in critical regions.
7. Optimize for Power and Area:
• Ensure that the power distribution network does not unnecessarily
increase the chip area. Optimize the size and placement of power pads,
decoupling capacitors, and routing to balance power delivery and chip
area.
• Avoid excessive use of power-hungry features such as high-speed clocks
or unoptimized logic circuits in certain areas.
8. Consider Low Power Design Techniques (Optional):
• Low-power techniques, such as power gating, clock gating, and
dynamic voltage scaling (DVS), can be considered to reduce power
consumption further, especially in idle or low-activity states.
• Implement these techniques during power planning to reduce overall
energy consumption and extend the battery life of portable devices.

5. Explain the following in ASIC floor plan in brief: i) Power planning

ii) Clock Planning.
i) Power Planning in ASIC Floor Plan:
Power planning in ASIC (Application-Specific Integrated Circuit) floor
planning is essential for ensuring the chip receives sufficient, stable, and
efficient power while minimizing power loss and optimizing performance.
 1. Power Pad Placement:
o Strategically place power pads (VDD and GND) around the chip to
provide power to all blocks. The placement should minimize power
distribution paths and voltage drops.
2. Power Distribution Network (PDN):
o Design an effective power grid that connects power pads to
functional blocks. This grid should use multiple metal layers to
distribute power evenly and ensure minimal voltage drop (IR drop)
and resistance.
3. Decoupling Capacitors:
o Place decap cells (capacitors) near power-sensitive blocks to filter
out noise and stabilize the power supply, improving overall voltage
integrity.
4. Power Grid Design:
o Plan the grid to balance current flow and reduce hotspots. Ensure
the metal layers are sufficiently wide to handle the required current
and minimize resistance.
5. Minimize Power Losses:
o Ensure that the power distribution network does not lead to
unnecessary power losses by optimizing the routing of power and
ground lines.
Importance of Power Planning:
• Reliability: Ensures each block receives stable power, preventing voltage
fluctuations or power shortages.
• Efficiency: Reduces power consumption, helping to meet energy goals
and extend battery life in portable devices.
• Cost-Effective: Minimizes unnecessary use of power-hungry components,
optimizing chip performance while controlling manufacturing costs.

ii) Clock Planning in ASIC Floor Plan:

Clock planning in ASIC design involves organizing the distribution of the clock
signal to all parts of the chip in a way that minimizes clock skew, reduces delay,
and ensures all components are synchronized.
1. Clock Distribution Network:
o Design an effective clock network that delivers the clock signal to
all sequential elements (e.g., flip-flops, registers) while maintaining
synchronization.
2. Minimizing Clock Skew:
o Ensure that the clock signal reaches all parts of the chip at the same
time to avoid clock skew, which can cause timing errors. This is
achieved by carefully routing the clock signal using balanced paths
and buffers.
3. Clock Tree Synthesis (CTS):
o Clock tree synthesis involves creating a hierarchical structure for
the clock signal's distribution. A well-designed clock tree
minimizes delays and ensures even distribution.
4. Clock Power Management:
o Optimize the clock signal's power consumption by reducing
unnecessary clock routing and using clock gating techniques to
turn off the clock in inactive regions, thus saving power.
5. Clock Pin Assignment:
o Properly assign clock pins to different blocks so the clock
distribution can be routed effectively without excessive wiring or
congestion.
Importance of Clock Planning:
• Synchronization: Ensures that all components operate in sync with the
same clock signal, crucial for timing accuracy.
• Performance: Reduces delays due to inefficient clock routing, leading to
faster operation of the chip.
• Power Efficiency: Reduces unnecessary clock signal routing and employs
clock gating to save power.
(INCLUDE NECESSARY DIAGRAMS)
6. Goals and Objective of Placement
Goals of Placement:
1. Arrange Logic Cells within Flexible Blocks:
o The main goal of a placement tool is to arrange all the logic cells
within predefined or flexible blocks on the chip. This helps ensure
the design meets area constraints while facilitating efficient
routing.
2. Guarantee the Router Can Complete Routing:
o The placement must allow the routing tool to complete its job by
ensuring enough space and channels for routing signals between
the placed cells. This avoids routing congestion and ensures a
feasible physical design.
3. Minimize Critical Net Delays:
o Critical nets (signal paths that determine the chip's timing
performance) should be placed to minimize their delay, ensuring
that the timing requirements for the design are met and the chip
operates at the desired speed.
4. Maximize Chip Density:
o The placement should maximize the use of the available chip area.
A denser placement typically means more logic in a smaller area,
improving chip efficiency and reducing manufacturing costs.
5. Minimize Power Dissipation:
o Proper placement can help minimize power consumption by
reducing the length of power and ground connections and
optimizing the placement of high-power consuming blocks.
6. Minimize Crosstalk Between Signals:
o The placement should minimize crosstalk (unwanted interference
between adjacent signal lines) by appropriately spacing signal
wires and separating noisy nets, improving signal integrity.
Objectives of Placement:
While achieving the goals outlined above is complex, the objectives for
placement are typically more specific and achievable. The most commonly used
placement objectives include:
 1. Minimize Total Estimated Interconnect Length:
o Interconnect length refers to the total distance that wires must
travel between the logic cells. Minimizing this length reduces the
power consumption of the interconnects and minimizes signal
delay, leading to faster operation.
2. Meet Timing Requirements for Critical Nets:
o Placement tools aim to ensure that the critical nets (the longest
delay paths) meet the required timing constraints by positioning
the cells in such a way that the delays are minimized, allowing the
design to function within its specified time limits.
3. Minimize Interconnect Congestion:
o Congestion occurs when too many signal connections are placed
too closely, which makes routing difficult. The objective is to
minimize congestion by leaving adequate space for routing and
balancing the density of the placed cells.

7. Explain the following in Placement: i) Min-cut Placement ii) Iterative

placement improvement.
i) Min-Cut Placement in VLSI Design:
Min-Cut Placement is a technique used in VLSI design to optimize the
placement of logic cells by minimizing the cut-set between blocks. The idea is
to reduce the total "cost" associated with the interconnections (or cuts) between
different blocks of logic cells to minimize the wire length and interconnect
delay.
1. Objective:
o The main goal of min-cut placement is to divide the chip area into
regions (or partitions) such that the total number of
interconnections (or cuts) between these regions is minimized.
This helps to reduce routing congestion and improve the overall
layout efficiency.
2. Process:
o The placement starts by dividing the design into two groups of
cells, such that the number of nets (connections between the cells)
 crossing the boundary (cut) between these two groups is
minimized.
o This is typically done by using recursive bisectioning, where the
area is divided repeatedly until an acceptable placement is
achieved.
o Each recursive step involves minimizing the number of
connections (cuts) between two blocks by shifting the cells to
optimize their positions.

Min-cut placement algorithm (a) Divide the chip into bins using a grid. (b)
Merge all connections to the center of each bin. (c) Make a cut and swap logic
cells between bins to minimize the cost of the cut. (d) Take the cut pieces and
throw out all the edges that are not inside the piece. (e) Repeat the process with
a new cut and continue until we reach the individual bins.
3. Advantages:
o Reduces Wire Length: By minimizing the number of cuts, the
routing of interconnects is more efficient, reducing the total wire
length required for signal paths.
o Improves Performance: Shorter wire lengths help in reducing
signal delay and congestion.
4. Disadvantages:
o Min-cut placement may not always lead to optimal performance, as
it mainly focuses on the number of cuts rather than the actual wire
 length or timing constraints.

ii) Iterative Placement Improvement in VLSI Design:

Iterative Placement Improvement is an optimization technique used to refine
the placement of cells through a series of repeated adjustments. The goal is to
improve the initial placement by iteratively making small changes to minimize
certain design metrics like wire length, delay, and congestion.
1. Objective:
o The main aim is to refine the placement by iteratively improving
the positions of cells to achieve better wire length, reduced
congestion, or meeting timing constraints.
2. Process:
o Initially, a first-cut placement is generated using a placement
algorithm (e.g., min-cut or random placement).

(a) Swapping the source logic cell with a destination logic cell in pairwise
interchange. (b) Sometimes we have to swap more than two logic cells at a time
to reach an optimum placement, but this is expensive in computation time.
Limiting the search to neighborhoods reduces the search time. Logic cells
within a distance e of a logic cell form an e-neighbourhood. (c) A one-
neighbourhood. (d) A two-neighbourhood.

o The iterative process involves repeatedly adjusting the positions

of cells to improve the design. Common methods include:
▪ Cell Shifting: Move cells locally to reduce congestion or
improve timing.
 ▪ Cell Exchange: Swap the positions of two cells to improve
the overall layout.
▪ Legalization: Ensure that the moved cells remain within the
chip’s area and avoid overlaps.
▪ Global and Local Refinement: Perform global optimization
(involving large-scale changes) and local optimization
(focused on small, specific areas) to achieve a balance
between performance and layout density.
3. Advantages:
o Improves Design Quality: Iterative improvement refines the
placement by focusing on reducing delay, wire length, and
congestion over several iterations.
o Flexibility: It allows for continuous improvements without the
need for a complete redesign.
4. Disadvantages:
o Computationally Expensive: Iterative methods can be time-
consuming, especially for large designs, because many iterations
are needed to reach an optimal solution.
o Local Minima: The algorithm might get stuck in a local optimum,
not always achieving the global best solution.
(INCLUDE OTHER NECESSARY DIAGRAMS)

8. Goals and Objectives of Routing or Global Routing

Global routing is a key step in the physical design process of VLSI, where the
goal is to plan the overall path of signal interconnections (or nets) between the
placed cells. This stage provides the necessary guidance and instructions to the
detailed router, which will later perform the actual wire routing on specific
metal layers.
Goals of Routing (Global Routing):
The primary goal of global routing is to provide a comprehensive and feasible
routing plan to the detailed router, allowing it to effectively route all nets on the
chip.
Objectives of Routing (Global Routing):
 o Minimize Interconnect Length: Shorter interconnects lead to
reduced delay, power consumption, and chip area.
o Maximize Routing Feasibility: Ensure that the detailed router can
complete routing without congestion or errors.
o Minimize Critical Path Delay: Optimize routing to reduce delays
on the critical path, improving the chip's speed.
In essence, global routing optimizes the overall routing strategy, focusing on
minimizing interconnects, ensuring routing feasibility, and improving
performance by reducing critical path delay.

9. Explain Global Routing Methods with Example.

Two of the most important methods used in global routing are Sequential
Routing and Hierarchical Routing. These methods help in providing routing
solutions that are both efficient and manageable, especially for complex and
large-scale chip designs.

1. Sequential Routing
Sequential routing involves routing the nets one by one in a particular
sequence. Each net is routed independently, and the routing of one net is done in
a specific order based on the chosen strategy. The routing outcome can be
affected by the sequence in which the nets are routed.
Types of Sequential Routing:
• Order Dependent Sequential Routing: The order of routing affects the
final solution. If nets are routed in a particular sequence, it impacts the
routing of subsequent nets. The sequence is often based on the criticality
of the nets.
o Example: In a design, the most critical net (e.g., a clock signal)
would be routed first to ensure timing requirements are met, and
other nets would be routed based on available routing space after
the critical net.
• Order Independent Sequential Routing: The order of routing does not
impact the final result. Each net is routed independently without
considering the sequence in which they are processed. This approach is
more flexible and parallelizable.
 o Example: In a chip design, nets can be routed in any order as long
as they do not interfere with each other, making the routing process
faster and more efficient.
Advantages of Sequential Routing:
• It provides a clear and structured approach to routing, especially when
nets have different priorities (critical vs. non-critical).
• Easier to implement for small designs or designs with few critical nets.
Disadvantages of Sequential Routing:
• It can cause congestion if not managed properly, especially when routing
more complex or dense designs.
• Order-dependent routing can lead to suboptimal results, as later nets may
face routing blockages from earlier nets.

2. Hierarchical Routing
Hierarchical routing breaks down the design into smaller blocks or regions,
and routing is done at different levels of abstraction. This method is especially
useful for large and complex designs, as it reduces the complexity of the routing
process by addressing smaller subproblems in a hierarchical fashion. The
routing is done at the macro level first and refined at lower levels.
Types of Hierarchical Routing:
• Top-Down Hierarchical Routing: The routing starts at the highest level
of abstraction, such as the entire chip or large functional blocks. The main
interconnections between blocks are routed first, and then the routing is
progressively refined within each block.
o Example: In a large chip design, the routing of connections
between major blocks (e.g., CPU, memory) is done first. Once the
high-level routing is completed, detailed routing inside each block
(e.g., routing within a CPU block) is handled separately.
• Bottom-Up Hierarchical Routing: In this method, routing starts at the
lowest level of abstraction, such as the individual cells or gates, and
moves upward. Detailed routing is done first, and then the higher-level
interconnections between the blocks are routed.
 o Example: Individual gates within a block are routed first, followed
by interconnections between different blocks (e.g., connecting CPU
and memory blocks after routing inside each block).
• Multi-Level Hierarchical Routing: This method combines both top-
down and bottom-up approaches. It routes the design at multiple levels,
starting with the highest-level connections and refining the routing
progressively through intermediate and low levels.
o Example: A complex chip might be divided into various functional
blocks. First, the interconnections between these blocks are routed,
and then the detailed routing inside each block and sub-block is
done iteratively.
Advantages of Hierarchical Routing:
• It is highly scalable and effective for large and complex designs with
many cells or blocks.
• By treating blocks or regions as units, it simplifies routing by breaking
down the problem into smaller, more manageable parts.
Disadvantages of Hierarchical Routing:
• Can be computationally intensive, especially if multiple levels of
abstraction are involved.
• The initial coarse routing may lead to suboptimal solutions if detailed
refinement is not adequately handled at lower levels.

10. Explain Global Routing b/w blocks with diagram.

Global routing is very similar for cell-based ASICs and gate arrays, but there is
a very important difference between the types of channels in these ASICs. The
size of the channels in sea-of-gates arrays, channelless gate arrays, and cell-
based ASICs can be varied to make sure there is enough space to complete the
wiring. In channeled gate-arrays and FPGAs the size, number, and location of
channels are fixed. The good news is that the global router can allocate as many
interconnects to each channel as it likes, since that space is committed anyway.
The bad news is that there is a maximum number of interconnects that each
channel can hold. If the global router needs more room, even in just one channel
on the whole chip, the designer has to repeat the placement-and-routing steps
and try again (or use a bigger chip).
 a) A cell-based ASIC with numbered channels. b) The channels form the edges of a graph. (c) The
channel-intersection graph. Each channel corresponds to an edge on a graph whose weight
corresponds to the channel length.

Figure (a) shows an example of global routing for a net with five terminals, labelled A1 through F1,
for the cell-based ASIC. If a designer wishes to use minimum total interconnect path length as an
objective, the global router finds the minimum-length tree. (b). This tree determines the channels the
interconnects will use. For example, the shortest connection from A1 to B1 uses channels 2, 1, and 5.
This is the information the global router passes to the detailed router. (c) shows that minimizing the
total path length may not correspond to minimizing the path delay between two points.

11. Back Annotation

12. Explain how partitioning and back annotation are used in floor
planning to improve timing and reduce delays.
1. Partitioning in Floor Planning
Partitioning divides the chip into smaller blocks to minimize interconnections
and optimize routing.
How Partitioning Improves Timing and Reduces Delays:
• Minimizes Wire Length: Shorter interconnections between blocks
reduce signal propagation delays.
o Example: Placing logic and memory blocks close together reduces
routing delay.
• Reduces Routing Congestion: More space for routing prevents
congestion and delays.
o Example: Proper partitioning ensures sufficient space for wiring
between blocks.
• Improves Power Distribution: Efficient partitioning helps in better
power grid design, reducing voltage drops and timing issues.

2. Back Annotation in Floor Planning

Back annotation updates the floor plan based on timing, power, or signal
integrity feedback from simulations.
How Back Annotation Improves Timing and Reduces Delays:
• Timing Analysis Feedback: Adjusts layout based on timing violations,
optimizing critical paths.
o Example: Moving blocks closer to reduce delay in critical paths.
• Signal Integrity Adjustments: Mitigates crosstalk or noise by
repositioning signals.
o Example: Rerouting signals to avoid interference.
• Power and Thermal Considerations: Adjusts layout to address power
issues or thermal hotspots.
o Example: Moving blocks with high power consumption to cooler
regions.