CS3351 Digital Principles and Computer Organization

UNIT V MEMORY AND I/O

Memory Concepts and Hierarchy – Memory Management – Cache Memories: Mapping and
Replacement Techniques – Virtual Memory – DMA – I/O – Accessing I/O: Parallel and Serial Interface
– Interrupt I/O – Interconnection Standards: USB, SATA

The computer memory can be divided into 5 major hierarchies that are based on use as well as
speed. A processor can easily move from any one level to some other on the basis of its
requirements. These five hierarchies in a system’s memory are register, cache memory, main
memory, magnetic disc, and magnetic tape.

What are the Design and Characteristics of Memory Hierarchy?

Memory Hierarchy, in Computer System Design, is an enhancement that helps in organising
the memory so that it can actually minimise the access time. The development of the Memory
Hierarchy occurred on a behaviour of a program known as locality of references. Here is a
figure that demonstrates the various levels of memory hierarchy clearly:

Memory Hierarchy Design

This Hierarchy Design of Memory is divided into two main types. They are:

External or Secondary Memory

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It consists of Magnetic Tape, Optical Disk, Magnetic Disk, i.e. it includes peripheral storage
devices that are accessible by the system’s processor via I/O Module.

Internal Memory or Primary Memory

It consists of CPU registers, Cache Memory, and Main Memory. It is accessible directly by the
processor.

Characteristics of Memory Hierarchy

One can infer these characteristics of a Memory Hierarchy Design from the figure given above:

1. Capacity
It refers to the total volume of data that a system’s memory can store. The capacity increases
moving from the top to the bottom in the Memory Hierarchy.

2. Access Time
It refers to the time interval present between the request for read/write and the data availability.
The access time increases as we move from the top to the bottom in the Memory Hierarchy.

3. Performance
When a computer system was designed earlier without the Memory Hierarchy Design, the gap
in speed increased between the given CPU registers and the Main Memory due to a large
difference in the system’s access time. It ultimately resulted in the system’s lower performance,
and thus, enhancement was required. Such a kind of enhancement was introduced in the form
of Memory Hierarchy Design, and because of this, the system’s performance increased. One
of the primary ways to increase the performance of a system is minimising how much a memory
hierarchy has to be done to manipulate data.

4. Cost per bit

The cost per bit increases as one moves from the bottom to the top in the Memory Hierarchy,
i.e. External Memory is cheaper than Internal Memory.

Design of Memory Hierarchy

In computers, the memory hierarchy primarily includes the following:

1. Registers
The register is usually an SRAM or static RAM in the computer processor that is used to hold
the data word that is typically 64 bits or 128 bits. A majority of the processors make use of a
status word register and an accumulator. The accumulator is primarily used to store the data in
the form of mathematical operations, and the status word register is primarily used for decision
making.

2. Cache Memory
The cache basically holds a chunk of information that is used frequently from the main
memory. We can also find cache memory in the processor. In case the processor has a single-
core, it will rarely have multiple cache levels. The present multi-core processors would have
three 2-levels for every individual core, and one of the levels is shared.

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3. Main Memory
In a computer, the main memory is nothing but the CPU’s memory unit that communicates
directly. It’s the primary storage unit of a computer system. The main memory is very fast and
a very large memory that is used for storing the information throughout the computer’s
operations. This type of memory is made up of ROM as well as RAM.

4. Magnetic Disks
In a computer, the magnetic disks are circular plates that’s fabricated with plastic or metal with
a magnetised material. Two faces of a disk are frequently used, and many disks can be stacked
on a single spindle by read/write heads that are obtainable on every plane. The disks in a
computer jointly turn at high speed.

5. Magnetic Tape
Magnetic tape refers to a normal magnetic recording designed with a slender magnetizable
overlay that covers an extended, thin strip of plastic film. It is used mainly to back up huge
chunks of data. When a computer needs to access a strip, it will first mount it to access the
information. Once the information is allowed, it will then be unmounted. The actual access
time of a computer memory would be slower within a magnetic strip, and it will take a few
minutes for us to access a strip.

What is Memory Management?

Memory Management is the process of controlling and coordinating computer memory,
assigning portions known as blocks to various running programs to optimize the overall
performance of the system. It is the most important function of an operating system that
manages primary memory. It helps processes to move back and forward between the main
memory and execution disk. It helps OS to keep track of every memory location, irrespective
of whether it is allocated to some process or it remains free.
Swapping:
Swapping is a mechanism in which a process can be swapped temporarily out of main memory
(or move) to secondary storage (disk) and make that memory available to other processes. At
some later time, the system swaps back the process from the secondary storage to main
memory.
Benefits of Swapping
Here, are major benefits/pros of swapping:
It offers a higher degree of multiprogramming.
Allows dynamic relocation. For example, if address binding atexecution time is being used,
then processes can be swap indifferent locations. Else in case of compile and load time
bindings, processes should be moved to the same location.
It helps to get better utilization of memory.
Minimum wastage of CPU time on completion so it can easily be applied to a priority-based
scheduling method to improve its performance.
What is Memory allocation?
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Memory allocation is a process by which computer programs are assigned memory or space.
main memory is divided into two types of partitions
1. Low Memory - Operating system resides in this type of memory.
2. High Memory- User processes are held in high memory.
Partition Allocation
Memory is divided into different blocks or partitions. Each process is allocated according to
the requirement. Partition allocation is an ideal method to avoid internal fragmentation.
Below are the various partition allocation schemes :
First Fit: In this type fit, the partition is allocated, which is the first sufficient block from the
beginning of the main memory.
Best Fit: It allocates the process to the partition that is the first smallest partition among the
free partitions.
Worst Fit: It allocates the process to the partition, which is the largest sufficient freely
available partition in the main memory.
Next Fit: It is mostly similar to the first Fit, but this Fit, searches for the first sufficient
partition from the last allocation point.
What is Paging?
Paging is a storage mechanism that allows OS to retrieve processes from the secondary storage
into the main memory in the form of pages. In the Paging method, the main memory is divided
into small fixed-size blocks of physical memory, which is called frames. The size of a frame
should be kept the same as that of a page to have maximum utilization of the main memory
and to avoid external fragmentation. Paging is used for faster access to data, and it is a logical
concept.
What is Fragmentation?
Processes are stored and removed from memory, which creates free memory space, which are
too small to use by other processes. After sometimes, that processes not able to allocate to
memory blocks because its small size and memory blocks always remain unused is called
fragmentation. This type of problem happens during a dynamic memory allocation system
when free blocks are quite small, so it is not able to fulfill any request.
Two types of Fragmentation methods are:
1. External fragmentation
2. Internal fragmentation
External fragmentation can be reduced by rearranging memory contents to place all free
memory together in a single block.
The internal fragmentation can be reduced by assigning the smallest partition, which is still
good enough to carry the entire process.
What is Segmentation?
Segmentation method works almost similarly to paging. The only difference between the two
is that segments are of variable-length, whereas, in the paging method, pages are always of
fixed size. A program segment includes the program's main function, data structures, utility
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functions, etc. The OS maintains a segment map table for all the processes. It also includes a
list of free memory blocks along with its size, segment numbers, and its memory locations in
the main memory or virtual memory.
What is Dynamic Loading?
Dynamic loading is a routine of a program which is not loaded until the program calls it. All
routines should be contained on disk in a relocatable load format. The main program will be
loaded into memory and will be executed. Dynamic loading also provides better memory space
utilization.
What is Dynamic Linking?
Linking is a method that helps OS to collect and merge various modules of code and data into
a single executable file. The file can be loaded into memory and executed. OS can link system-
level libraries into a program that combines the libraries at load time. In Dynamic linking
method, libraries are linked at execution time, so program code size can remain small.
Difference Between Static and Dynamic Loading
Static Loading Dynamic Loading
Static loading is used when you want to
load your program statically. Then at the In a Dynamically loaded program,
time of compilation, the entire program will references will be provided and the loading
be linked and compiled without need of any will be done at the time of execution.
external module or program dependency.
Routines of the library are loaded into
At loading time, the entire program is
memory only when they are required in the
loaded into memory and starts its execution.
program.

Difference Between Static and Dynamic Linking

Static Linking Dynamic Linking
When dynamic linking is used, it does not
Static linking is used to combine all other
need to link the actual module or library
modules, which are required by a program
with the program. Instead of it use a
into a single executable code. This helps OS
reference to the dynamic module provided
prevent any runtime dependency.
at the time of compilation and linking.

Important Points to remember:

Memory management is the process of controlling and coordinating computer memory,
assigning portions called blocks to various running programs to optimize the overall
performance of the system.
It allows you to check how much memory needs to be allocated to processes that decide
which processor should get memory at what time.
In Single Contiguous Allocation, all types of computer's memory except a small portion
which is reserved for the OS is available for one application
Partitioned Allocation method divides primary memory into various memory partitions,
which is mostly contiguous areas of memory

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 Paged Memory Management method divides the computer's main memory into fixed-size
units known as page frames
Segmented memory is the only memory management method that does not provide the user's
program with a linear and contiguous address space.
Swapping is a method in which the process should be swapped temporarily from the main
memory to the backing store. It will be later brought back into the memory for continue
execution.
Memory allocation is a process by which computer programs are assigned memory or space.
Paging is a storage mechanism that allows OS to retrieve processes from the secondary
storage into the main memory in the form of pages.
Fragmentation refers to the condition of a disk in which files are divided into pieces scattered
around the disk.
Segmentation method works almost similarly to paging. The only difference between the
two is that segments are of variable length, whereas, in the paging method, pages are always
of fixed size.
Dynamic loading is a routine of a program which is not loaded until the program calls it.
Linking is a method that helps OS to collect and merge various modules of code and data
into a single executable file.
Cache Memories: Mapping and Replacement Techniques
Cache mapping refers to a technique using which the content present in the main memory is
brought into the memory of the cache. Three distinct types of mapping are used for cache
memory mapping.

What is Cache Mapping?

As we know that the cache memory bridges the mismatch of speed between the main
memory and the processor. Whenever a cache hit occurs,

• The word that is required is present in the memory of the cache.

• Then the required word would be delivered from the cache memory to the CPU.
And, whenever a cache miss occurs,

• The word that is required isn’t present in the memory of the cache.
• The page consists of the required word that we need to map from the main memory.
• We can perform such a type of mapping using various different techniques of cache
mapping.
Let us discuss different techniques of cache mapping.

Process of Cache Mapping

The process of cache mapping helps us define how a certain block that is present in the main
memory gets mapped to the memory of a cache in the case of any cache miss.
In simpler words, cache mapping refers to a technique using which we bring the main
memory into the cache memory. Here is a diagram that illustrates the actual process of
mapping:

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Now, before we proceed ahead, it is very crucial that we note these points:

Important Note:

• The main memory gets divided into multiple partitions of equal size, known as the
frames or blocks.
• The cache memory is actually divided into various partitions of the same sizes as that
of the blocks, known as lines.
• The main memory block is copied simply to the cache during the process of cache
mapping, and this block isn’t brought at all from the main memory.

Techniques of Cache Mapping

One can perform the process of cache mapping using these three techniques given as follows:

1. K-way Set Associative Mapping

2. Direct Mapping
3. Fully Associative Mapping

1. Direct Mapping
In the case of direct mapping, a certain block of the main memory would be able to map a
cache only up to a certain line of the cache. The total line numbers of cache to which any
distinct block can map are given by the following:

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Cache line number = (Address of the Main Memory Block ) Modulo (Total number of lines
in Cache)
For example,

• Let us consider that particular cache memory is divided into a total of ‘n’ number of
lines.
• Then, the block ‘j’ of the main memory would be able to map to line number only of
the cache (j mod n).

•
The Need for Replacement Algorithm
In the case of direct mapping,

• There is no requirement for a replacement algorithm.

• It is because the block of the main memory would be able to map to a certain line of
the cache only.
• Thus, the incoming (new) block always happens to replace the block that already
exists, if any, in this certain line.
Division of Physical Address
In the case of direct mapping, the division of the physical address occurs as follows:

2. Fully Associative Mapping

In the case of fully associative mapping,
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 • The main memory block is capable of mapping to any given line of the cache that’s
available freely at that particular moment.
• It helps us make a fully associative mapping comparatively more flexible than direct
mapping.
For Example
Let us consider the scenario given as follows:

Here, we can see that,

• Every single line of cache is available freely.

• Thus, any main memory block can map to a line of the cache.
• In case all the cache lines are occupied, one of the blocks that exists already needs to
be replaced.
The Need for Replacement Algorithm
In the case of fully associative mapping,

• The replacement algorithm is always required.

• The replacement algorithm suggests a block that is to be replaced whenever all the
cache lines happen to be occupied.
• So, replacement algorithms such as LRU Algorithm, FCFS Algorithm, etc., are
employed.
Division of Physical Address
In the case of fully associative mapping, the division of the physical address occurs as
follows:

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3. K-way Set Associative Mapping
In the case of k-way set associative mapping,

• The grouping of the cache lines occurs into various sets where all the sets consist of k
number of lines.
• Any given main memory block can map only to a particular cache set.
• However, within that very set, the block of memory can map any cache line that is
freely available.
• The cache set to which a certain main memory block can map is basically given as
follows:
Cache set number = ( Block Address of the Main Memory ) Modulo (Total Number of sets
present in the Cache)

For Example
Let us consider the example given as follows of a two-way set-associative mapping:

In this case,

• k = 2 would suggest that every set consists of two cache lines.

• Since the cache consists of 6 lines, the total number of sets that are present in the
cache = 6 / 2 = 3 sets.
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 • The block ‘j’ of the main memory is capable of mapping to the set number only (j
mod 3) of the cache.
• Here, within this very set, the block ‘j’ is capable of mapping to any cache line that is
freely available at that moment.
• In case all the available cache lines happen to be occupied, then one of the blocks that
already exist needs to be replaced.
The Need for Replacement Algorithm
In the case of k-way set associative mapping,

• The k-way set associative mapping refers to a combination of the direct mapping as
well as the fully associative mapping.
• It makes use of the fully associative mapping that exists within each set.
• Therefore, the k-way set associative mapping needs a certain type of replacement
algorithm.
Division of Physical Address
In the case of fully k-way set mapping, the division of the physical address occurs as follows:

Special Cases

• In case k = 1, the k-way set associative mapping would become direct mapping. Thus,
Direct Mapping = one-way set associative mapping

• In the case of k = The total number of lines present in the cache, then the k-way set
associative mapping would become fully associative mapping.

Two mark question on Cache memory:

What is cache mapping and its type?

Cache mapping refers to a technique using which the content present in the main memory is
brought into the memory of the cache. Three distinct types of mapping are used for cache
memory mapping: Direct, Associative and Set-Associative mapping.

Why do we need cache mapping?

The Cache Memory refers to a special, very high-speed memory that is used when we want to
speed up and synchronize with a high-speed CPU. The cache holds data and instructions that
are frequently requested so that they are available immediately to the CPU as and when
needed. The cache memory is used to reduce the overall average time that is required to
access data and information from the main memory.
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What is cache in simple terms?
A cache, in simpler words, refers to a block of memory used for storing data that is most
likely used again. The hard drive and CPU often make use of a cache, just like the web
servers and web browsers do. Any cache is made up of numerous entries, known as a pool.

What are the 3 types of cache memory?

The three types of general cache are:

• The L1 cache, also known as the primary cache, is very fast, but it is relatively small.
It is embedded usually in the processor chip in the form of the CPU cache.
• The secondary cache, also known as the L2 cache, is often comparatively more
capacious than the L1 cache.
• The Level 3 (or L3) cache refers to a specialized memory that is developed in order to
improve the actual performance of the L1 and L2.

Virtual Memory

Virtual Memory is a storage scheme that provides user an illusion of having a very big main
memory. This is done by treating a part of secondary memory as the main memory.

In this scheme, User can load the bigger size processes than the available main memory by
having the illusion that the memory is available to load the process.

Instead of loading one big process in the main memory, the Operating System loads the
different parts of more than one process in the main memory.

By doing this, the degree of multiprogramming will be increased and therefore, the CPU
utilization will also be increased.

How Virtual Memory Works?

In modern word, virtual memory has become quite common these days. In this scheme,
whenever some pages needs to be loaded in the main memory for the execution and the memory
is not available for those many pages, then in that case, instead of stopping the pages from
entering in the main memory, the OS search for the RAM area that are least used in the recent
times or that are not referenced and copy that into the secondary memory to make the space for
the new pages in the main memory.

Since all this procedure happens automatically, therefore it makes the computer feel like it is
having the unlimited RAM.

Demand Paging

Demand Paging is a popular method of virtual memory management. In demand paging, the
pages of a process which are least used, get stored in the secondary memory.

A page is copied to the main memory when its demand is made or page fault occurs. There are
various page replacement algorithms which are used to determine the pages which will be
replaced. We will discuss each one of them later in detail.

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Snapshot of a virtual memory management system

Let us assume 2 processes, P1 and P2, contains 4 pages each. Each page size is 1 KB. The main
memory contains 8 frame of 1 KB each. The OS resides in the first two partitions. In the third
partition, 1st page of P1 is stored and the other frames are also shown as filled with the different
pages of processes in the main memory.

The page tables of both the pages are 1 KB size each and therefore they can be fit in one frame
each. The page tables of both the processes contain various information that is also shown in
the image.

The CPU contains a register which contains the base address of page table that is 5 in the case
of P1 and 7 in the case of P2. This page table base address will be added to the page number
of the Logical address when it comes to accessing the actual corresponding entry.

Advantages of Virtual Memory

• The degree of Multiprogramming will be increased.

• User can run large application with less real RAM.
• There is no need to buy more memory RAMs.
• Disadvantages of Virtual Memory
• The system becomes slower since swapping takes time.
• It takes more time in switching between applications.
• The user will have the lesser hard disk space for its use.

Direct Memory Access (DMA) :

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DMA Controller is a hardware device that allows I/O devices to directly access memory with
less participation of the processor. DMA controller needs the same old circuits of an interface
to communicate with the CPU and Input/Output devices.
The block diagram of the DMA controller. The unit communicates with the CPU through data
bus and control lines. Through the use of the address bus and allowing the DMA and RS register
to select inputs, the register within the DMA is chosen by the CPU. RD and WR are two-way
inputs. When BG (bus grant) input is 0, the CPU can communicate with DMA registers. When
BG (bus grant) input is 1, the CPU has relinquished the buses and DMA can communicate
directly with the memory.
DMA controller registers :
The DMA controller has three registers as follows.
Address register – It contains the address to specify the desired location in memory. Word
count register – It contains the number of words to be transferred. Control register – It specifies
the transfer mode.
Note – All registers in the DMA appear to the CPU as I/O interface registers. Therefore, the
CPU can both read and write into the DMA registers under program control via the data bus.
Block Diagram

Explanation : The CPU initializes the DMA by sending the given information through the data
bus.
• The starting address of the memory block where the data is available (to read) or where
data are to be stored (to write).
• It also sends word count which is the number of words in the memory block to be read
or write.
• Control to define the mode of transfer such as read or write.
• A control to begin the DMA transfer.

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Suppose any device which is connected to input-output port wants to transfer data to memory,
first of all it will send input-output port address and control signal, input-output read to input-
output port, then it will send memory address and memory write signal to memory where
data has to be transferred. In normal input-output technique the processor becomes busy in
checking whether any input-output operation is completed or not for next input-output
operation, therefore this technique is slow. This problem of slow data transfer between input-
output port and memory or between two memory is avoided by implementing Direct Memory
Access (DMA) technique. This is faster as the microprocessor/computer is bypassed and the
control of address bus and data bus is given to the DMA controller.
• HOLD – hold signal

• HLDA – hold acknowledgment

• DREQ – DMA request

• DACK – DMA acknowledgment

Suppose a floppy drive that is connected at input-output port wants to transfer data to
memory, the following steps are performed:

• Step-1: First of all the floppy drive will send a DMA request (DREQ) to the
DMAC, it means the floppy drive wants its DMA service.

• Step-2: Now the DMAC will send a HOLD signal to the CPU.

• Step-3: After accepting the DMA service request from the DMAC, the CPU will
send hold acknowledgment (HLDA) to the DMAC, it means the microprocessor
has released control of the address bus the data bus to DMAC and the
microprocessor/computer is bypassed during DMA service.

• Step-4: Now the DMAC will send one acknowledgement (DACL) to the floppy
drive which is connected at the input-output port. It means the DMAC tells the

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 floppy drive be ready for its DMA service.

• Step-5: Now with the help of input-output read and memory write signal the
data is transferred from the floppy drive to the memory.

Modes of DMAC:
1. Single Mode – In this only one channel is used, means only a single DMAC is
connected to the bus system.

2. Cascade Mode – In this multiple channels are used, we can further cascade more number
of DMACs.

I/O Interface
The method that is used to transfer information between internal storage and external I/O
devices is known as I/O interface. The CPU is interfaced using special communication links
by the peripherals connected to any computer system. These communication links are used
to resolve the differences between CPU and peripheral. There exists special hardware
components between CPU and peripherals to supervise and synchronize all the input and
output transfers that are called interface units.
Mode of Transfer:
The binary information that is received from an external device is usually stored in the
memory unit. The information that is transferred from the CPU to the external device is
originated from the memory unit. CPU merely processes the information but the source and
target is always the memory unit. Data transfer between CPU and the I/O devices may be
done in different modes.
Data transfer to and from the peripherals may be done in any of the three possible ways
1. Programmed I/O.
2. Interrupt- initiated I/O.
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 3. Direct memory access( DMA).
Now let’s discuss each mode one by one.
1. Programmed I/O: It is due to the result of the I/O instructions that are written
in the computer program. Each data item transfer is initiated by an instruction in
the program. Usually the transfer is from a CPU register and memory. In this case
it requires constant monitoring by the CPU of the peripheral devices.
Example of Programmed I/O: In this case, the I/O device does not have direct
access to the memory unit. A transfer from I/O device to memory requires the
execution of several instructions by the CPU, including an input instruction to
transfer the data from device to the CPU and store instruction to transfer the data
from CPU to memory. In programmed I/O, the CPU stays in the program loop
until the I/O unit indicates that it is ready for data transfer. This is a time
consuming process since it needlessly keeps the CPU busy. This situation can be
avoided by using an interrupt facility. This is discussed below.

2. Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy
unnecessarily. This situation can very well be avoided by using an interrupt driven
method for data transfer. By using interrupt facility and special commands to
inform the interface to issue an interrupt request signal whenever data is available
from any device. In the meantime the CPU can proceed for any other program
execution. The interface meanwhile keeps monitoring the device. Whenever it is
determined that the device is ready for data transfer it initiates an interrupt request
signal to the computer. Upon detection of an external interrupt signal the CPU
stops momentarily the task that it was already performing, branches to the service
program to process the I/O transfer, and then return to the task it was originally
performing.

Note: Both the methods programmed I/O and Interrupt-driven I/O require the active
intervention of the processor to transfer data between memory and the I/O module,
and any data transfer must transverse a path through the processor. Thus both these
forms of I/O suffer from two inherent drawbacks.
• The I/O transfer rate is limited by the speed with which the processor can
test and service a device.
• The processor is tied up in managing an I/O transfer; a number of
instructions must be executed for each I/O transfer.
3. Direct Memory Access: The data transfer between a fast storage media such as
magnetic disk and memory unit is limited by the speed of the CPU. Thus we can
allow the peripherals directly communicate with each other using the memory
buses, removing the intervention of the CPU. This type of data transfer technique
is known as DMA or direct memory access. During DMA the CPU is idle and it
has no control over the memory buses. The DMA controller takes over the buses
to manage the transfer directly between the I/O devices and the memory unit.

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Bus Request : It is used by the DMA controller to request the CPU to relinquish the
control of the buses.
Bus Grant : It is activated by the CPU to Inform the external DMA controller that
the buses are in high impedance state and the requesting DMA can take control of
the buses. Once the DMA has taken the control of the buses it transfers the data.
This transfer can take place in many ways.
Types of DMA transfer using DMA controller:
Burst Transfer :
DMA returns the bus after complete data transfer. A register is used as a byte count,
being decremented for each byte transfer, and upon the byte count reaching zero, the
DMAC will release the bus. When the DMAC operates in burst mode, the CPU is
halted for the duration of the data transfer.
Steps involved are:
1. Bus grant request time.
2. Transfer the entire block of data at transfer rate of device because the
device is usually slow than the speed at which the data can be transferred
to CPU.
3. Release the control of the bus back to CPU So, total time taken to
transfer the N bytes = Bus grant request time + (N) * (memory transfer
rate) + Bus release control time.
Where,
X µsec =data transfer time or preparation time (words/block)
Y µsec =memory cycle time or cycle time or transfer time
(words/block)
% CPU idle (Blocked)=(Y/X+Y)*100
% CPU Busy=(X/X+Y)*100
Cyclic Stealing :
An alternative method in which DMA controller transfers one word at a time after

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 which it must return the control of the buses to the CPU. The CPU delays its
operation only for one memory cycle to allow the direct memory I/O transfer to
“steal” one memory cycle.
Steps Involved are:
4. Buffer the byte into the buffer
5. Inform the CPU that the device has 1 byte to transfer (i.e. bus grant
request)
6. Transfer the byte (at system bus speed)
7. Release the control of the bus back to CPU.
Before moving on transfer next byte of data, device performs step 1 again so
that bus isn’t tied up and the transfer won’t depend upon the transfer rate of
device. So, for 1 byte of transfer of data, time taken by using cycle stealing
mode (T).= time required for bus grant + 1 bus cycle to transfer data + time
required to release the bus, it will be N x T
In cycle stealing mode we always follow pipelining concept that when one byte is
getting transferred then Device is parallel preparing the next byte. “The fraction of
CPU time to the data transfer time” if asked then cycle stealing mode is used.
Where,
X µsec =data transfer time or preparation time
(words/block)
Y µsec =memory cycle time or cycle time or transfer
time (words/block)
% CPU idle (Blocked) =(Y/X)*100
% CPU busy=(X/Y)*100
Interleaved mode: In this technique , the DMA controller takes over the system bus
when the microprocessor is not using [Link] alternate half cycle i.e. half cycle DMA
+ half cycle processor.

Introduction to Input-Output Interface (Accessing I/O)

Input-Output Interface is used as an method which helps in transferring of information
between the internal storage devices i.e. memory and the external peripheral device . A
peripheral device is that which provide input and output for the computer, it is also called
Input-Output devices. For Example: A keyboard and mouse provide Input to the computer
are called input devices while a monitor and printer that provide output to the computer are
called output devices. Just like the external hard-drives, there is also availability of some
peripheral devices which are able to provide both input and output.

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In micro-computer base system, the only purpose of peripheral devices is just to
provide special communication links for the interfacing them with the CPU. To resolve the
differences between peripheral devices and CPU, there is a special need for communication
links.
The major differences are as follows:
1. The nature of peripheral devices is electromagnetic and electro-mechanical. The
nature of the CPU is electronic. There is a lot of difference in the mode of
operation of both peripheral devices and CPU.
2. There is also a synchronization mechanism because the data transfer rate of
peripheral devices are slow than CPU.
3. In peripheral devices, data code and formats are differ from the format in the
CPU and memory.
4. The operating mode of peripheral devices are different and each may be
controlled so as not to disturb the operation of other peripheral devices
connected to CPU.
There is a special need of the additional hardware to resolve the differences between CPU
and peripheral devices to supervise and synchronize all input and output devices.

Functions of Input-Output Interface:

1. It is used to synchronize the operating speed of CPU with respect to input-output

devices.
2. It selects the input-output device which is appropriate for the interpretation of
the input-output device.
3. It is capable of providing signals like control and timing signals.
4. In this data buffering can be possible through data bus.
5. There are various error detectors.
6. It converts serial data into parallel data and vice-versa.
7. It also convert digital data into analog signal and vice-versa.

Parallel and Serial Interface

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21
Universal Serial Bus (USB)

The universal serial bus (USB) is a standard interface for connecting a wide range of devices
to the computer such as keyboard, mouse, smartphones, speakers, cameras etc. The USB was
introduced for commercial use in the year 1995 at that time it has a data transfer speed of 12
megabits/s.

With some improvement, a modified USB 2 was introduced which is also called a highspeed
USB that transfers data at 480 megabits/s. With the evolution of I/O devices that require
highspeed data transfer also leads to the development of USB 3 which is also referred to
as Superspeed USB which transfers data at 5 gigabits/s. The recent version of USB can transfer
data up to 20 gigabits/s.

• The developed USB must be simple and a low-cost interconnection system that should
be easy to use.
• The developed USB must be compatible with all new I/O devices, their bit rates,
internet connections and audio, video application.
• The USB must support a plug-and-play mode of operation.
• The USB must support low power implementation.
• The USB must also provide support for legacy hardware and software.

USB Architecture

When multiple I/O devices are connected to the computer through USB they all are organized
in a tree structure. Each I/O device makes a point-to-point connection and transfers data using
the serial transmission format we have discussed serial transmission in our previous content
‘interface circuit’.

As we know a tree structure has a root, nodes and leaves. The tree structure connecting I/O
devices to the computer using USB has nodes which are also referred to as a hub. Hub is the
intermediatory connecting point between the I/O devices and the computer. Every tree has a
root here, it is referred to as the root hub which connects the entire tree to the hosting
computer. The leaves of the tree here are nothing but the I/O devices such as a mouse,
keyboard, camera, speaker.

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The USB works on the principle of polling. In polling, the processor keeps on checking
whether the I/O device is ready for data transfer or not. So, the devices do not have to inform
the processor about any of their statuses. It is the processor’s responsibility to keep a check.
This makes the USB simple and low cost.

Whenever a new device is connected to the hub it is addressed as 0. Now at a regular interval
the host computer polls all the hubs to get their status which lets the host know of I/O devices
that are either detached from the system or are attached to the system.

When the host becomes aware of the new device it gets to know about the capabilities of the
device by reading the information present in the special memory of the device’s USB
interface. So that the host can use the appropriate device driver to communicate with the
device.

The host then assigns an address to this new device, this address is written to the register of
the device interface register. With this mechanism, USB serves plug-and-play capability.

The plug and play feature let the host recognize the existence of the new I/O device
automatically when the device is plugged in. The host software determines the capabilities of
the I/O devices and if it has any special requirement.

The USB is hot-pluggable which means the I/O device can

be attached or removed from the host system without
performing any restart or shutdown. That means your system
can keep running while the I/O device is plugged or
removed.

Isochronous Traffic on USB

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USB also supports the isochronous traffic where the data is transferred at a fixed timed
interval, where the intervals are regular and of very short time. The isochronous data
transmission is comparatively faster than asynchronous and synchronous data transfer.

To accommodate the isochronous traffic, the root hub sends a sequence of bits over the USB
tree this indicates the start of isochronous data and after this sequence of bits, the actual data
is transmitted.

As USB support the isochronous data transmission the audio-video signals are transferred in
a precisely timely manner.

Types of USB Connectors

The USB has different types of ports and connectors. Usually, the upstream port and
connector are always the USB type A the downstream port and connector differ depending on
the type of device connected. We will discuss all types of the USB connector.

USB Type A: This is the standard connector that can be found at one end of the USB cable
and is also known as upstream. It has a flat structure and has four connecting lines as you can
see in the image below.

USB Type B: This is an older standard cable and was used to connect the peripheral devices
also referred to as downstream. It is approximately a square as you can see in the image
below. This is now been replaced by the newer versions.

Mini USB: This type of USB is compatible with mobile devices. This type of USB is now
superseded your micro-USB still you will get it on some devices.

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Micro USB: This type of USB is found on newer mobile devices. It has a compact 5 pin
design.

USB Type C: This type of USB is used for transferring both data and power to the attached
peripheral or I/O device. The USB C does not have a fixed orientation as it is reversible i.e.
you can plug it upside down or in reverse.

USB 3.0 Micro B: This USB is a superspeed USB. This USB is used for a device that
requires high-speed data transfer. You can find this kind of USB on portable hard drives.

Electrical Characteristics of USB

The standard USB has four lines of connection among which two carry power (one carry +5
V and one is for Ground). The other two lines of connection are for data transfer. USB also
supply power to connected I/O device that requires very low power.

Transferring of data over USB can be divided into two categories i.e., transferring data at low
speed and transferring data at high speed.

The low-speed transmission uses single-ended signalling where varying high voltage is
transmitted over one of the two data lines to represent the signal bit 0 or 1. The other data line
is connected to the reference voltage i.e., ground. The single-ended signalling is prone to
noise.

The high-speed data transmission uses the approach differential signalling. Here, the signal
is transmitted over the two data lines that are twisted together. Here both the data lines are
involved in carrying the signal no ground wire is required. The differential signalling is not
prone to noise and uses low voltages as compared to single-ended transmission.

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SATA
SATA is an interface that connects various storage devices such as hard disks, optical
drives, SSD’s, etc to the motherboard. SATA was introduced in the year 2000 to replace
the long-standing PATA (Parallel ATA) interface. We all know, in serial mode, data is
transferred bit by bit and in parallel, there are several streams that carry the data. Despite
knowing this fact, there is a drawback in PATA. PATA is highly susceptible to outside
interferences and hence allows SATA to operate at high speeds than PATA. SATA cables are
thinner, more flexible and compact as compared to the PATA cables.

A SATA controller is a device that is used to connect the computer’s motherboard to

the storage drives.
SATA operates on two modes –
1. IDE mode: IDE stands for Integrated Drive Electronics. This is a mode which is
used to provide backward compatibility with older hardware, which runs on
PATA, at the cost of low performance.
2. AHCI mode: AHCI is abbreviation for Advanced Host Controller Interface.
AHCI is a high-performance mode that also provides support for hot-swapping.
Characteristics of SATA
• Low Voltage Requirement: SATA operates on 500mV (0.5V) peak-to-peak
signaling. This help in promoting a much low interference and crosstalk between
conductors.
• Simplified construction: PATA cables had 40-pin/80-wire ribbon cable. This
was complex in construction. In comparison, SATA had a single 7 pin data cable
and a 15 pin power cable. This cable resulted in a higher signaling rate, which
translates to faster throughput of data.
• Differential Signaling: SATA uses differential signaling. Differential signaling is
a technology which uses two adjacent wires to simultaneously the in-phase and
out-of-phase signals. Thus, it is possible to transfer high-speed data with low
operating voltage and low power consumption by detecting the phase difference
between the two signals at the receiver’s end.
• High data transfer rate: SATA has a high data transfer rate of 150/300/600
MBs/second. This capability of SATA allows for faster program loading, better
picture loading and fast document loading.
Advantages of SATA
• Faster data transfer rate as compared to PATA.
• SATA cable can be of length upto 1 meter, whereas PATA cable can only have
length of maximum 18 inches.
• SATA cables are smaller in size.
• Since, they are smaller in size, they take up less space inside the computer and
increase the internal air flow. Increased air flow can decrease heat build-up and
therefore increases the overall life of computer.
• Most modern computer motherboards today have SATA ports more than PATA
ports.
• Low power consumption (0.5V).
Disadvantages of SATA
• Special device drivers are required sometimes to recognize and use the drive.
However, a SATA hard drive can behave as a PATA
drive. This eliminates the need for a specific driver to be installed.
• SATA cable supports only one hard drive to connect at a time, whereas PATA
cable allows up to two PATA drives per cable.
• SATA is costlier as compared to PATA.

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 Anna University Previous year question bank
PART- A (2 MARKS)
1. What is Memory system?
Memory is a device or system that is used to store information for immediate
use in a computer or related computer hardware and digital electronic devices.
2. Give classification of memory.
There are four types of primary storage:
• read only memory (ROM)
• random access memory (RAM)
• flash memory.
• cache memory.

3. Define cache.
In computing, a cache is a high-speed data storage layer which stores a subset
of data, typically transient in nature, so that future requests for that data are
served up faster than is possible by accessing the data's primary storage
location.
4. What is Read Access Time?
With computer memory, access time is the amount of time it takes the
computer processor to read data from the memory. When looking at the access
time of memory it may be represented in either ns (nanoseconds), MHz, or
GHz.
5. Define Random Access Memory.
RAM (random access memory) is a computer's short-term memory, where the
data that the processor is currently using is stored. Your computer can access
RAM memory much faster than data on a hard disk, SSD, or other long-term
storage device, which is why RAM capacity is critical for system performance
6. What are PROMS?
A programmable read-only memory (PROM) is a form of digital memory
where the contents can be changed once after manufacture of the device. The
data is then permanent and cannot be changed. It is one type of read-only
memory (ROM).
7. Define Memory refreshing.
It is a background maintenance process that is necessary for operation of
DRAMs. When in operation, each of the memory cells needs to be refreshed
repeatedly. However, the maximum interval between two refreshes is defined
by the manufacturer of the memory and lies in the millisecond segment.
8. What is SRAM and DRAM?
SRAM stands for Static Random Access Memory ,
DRAM stands for Dynamic Random Access Memory.
SRAM:
SRAM is made up of flipflops ,
It stores the data in latch.
It is more expensive then DRAM ,
It is faster then DRAM ,
It doesn’t need any Refreshment after some period ,
It is used as Cache Memory .
Data is stored as long as Power is there
DRAM:

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 DRAM is made up of Capacitors ,
It stores the data in Separate Capacitors ,
It is cheaper than SRAM ,
It is Slower than SRAM ,
It need Periodically Refreshment to maintain the data,
It is used as Main Memory.
Data is Stored it is deleted after Shutdown.
9. What is volatile memory?
Volatile memory is a type of memory that maintains its data only while the
device is powered. If the power is interrupted for any reason, the data is lost.
10. Define data transfer or band width.
Bandwidth is the amount of data that can be transferred at one time. Data
transfer is the actual amount of data transferred.
11. What is flash memory?
Flash memory is a low-cost, high-density, non-volatile computer storage chip
that can be electrically erased and reprogrammed. Flash memory can be either
NOR-Flash or NAND-Flash. NOR-Flash allows a single word to be written or
read independently. It can be used for storing boot code.
12. What is multi level memories?
multilevel memory A memory system containing at least two memory
subsystems with different capacity and access-time attributes.
13. What is associate memory?
Associative memory is also known as content addressable memory (CAM) or
associative storage or associative array.
14. Define Seek time and latency time.
Seek Time is measured defines the amount of time it takes a hard drive's
read/write head to find the physical location of a piece of data on the disk.
Latency is the average time for the sector being accessed to rotate into position
under a head, after a completed seek.
15. Define memory cycle time.
Cycle time is the time, usually measured in nanosecond s, between the start of
one random access memory ( RAM ) access to the time when the next access
can be started
16. What is static memories?
When the allocation of memory performs at the compile time, then it is known
as static memory. In this, the memory is allocated for variables by the
compiler.
17. What is locality of reference?
locality of reference, also known as the principle of locality, is the tendency of
a processor to access the same set of memory locations repetitively over a
short period of time.
18. Define set associative cache.
Set associative caches are a. compromise between fully associative caches and
direct-mapped caches. In a set associative cache, there are a fixed number of
locations (called a set) that a given address may be stored in. The number of
locations in each set is the associative of the cache.
19. Give formula to calculate average memory access time.
Tavg = h*Tc +(1-h)*M

where h = hit rate

(1-h) = miss rate
Tc = time to access information from cache

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 M = miss penalty (time to access main memory)
20. What is memory interleaving?
Memory Interleaving is an abstraction technique which divides memory into a
number of modules such that successive words in the address space are placed
in the different module.
21. Give the features of ROM cell.
Features of ROM (Read-Only Memory):
ROM is a non-volatile memory.
Information stored in ROM is permanent.
Information and programs stored on it, we can only read.
Information and programs are stored on ROM in binary format.
It is used in the start-up process of the computer.
22. List the difference between static RAM and dynamic RAM.
SRAM DRAM

It stores information as long as the

It stores information as long as the power power is supplied or a few milliseconds
is supplied. when power is switched off.

Transistors are used to store information in Capacitors are used to store data in
SRAM. DRAM.

To store information for a longer time,

Capacitors are not used hence no contents of the capacitor need to be
refreshing is required. refreshed periodically.

SRAM is faster compared to DRAM. DRAM provides slow access speeds.

It does not have a refreshing unit. It has a refreshing unit.

These are expensive. These are cheaper.

SRAMs are low-density devices. DRAMs are high-density devices.

In this bits are stored in the form of

In this bits are stored in voltage form. electric energy.

These are used in cache memories. These are used in main memories.

Consumes less power and generates less Uses more power and generates more
heat. heat.

PART-B (16 MARKS)

1. Illustrate the characteristics of some common memory technologies.
2. Describe in detail about associative memory.

29
3. Discuss the concept of Memory interleaving and give its advantages.
4. Discuss the different mapping techniques used in cache memories and their relative merits
and demerits.
5. Comparing paging and segmentation mechanisms for implementing the virtual memory.
6. What do you mean by virtual memory? Discuss how paging helps in implementing virtual
memory.
7. Discuss any six ways of improving the cache performance.
8. Explain the virtual memory translation and TLB with necessary diagram.
9. Explain the organization of magnetic disk and magnetic tape in detail.
10. Explain with the block diagram the DMA transfer in a computer system.
11. Describe in detail about IOP Organization.
12. Describe the data transfer method using DMA.
13. Discuss the design of a typical input or output interface.
14. What are interrupts? How are they handled?
15. Give comparison between memory mapped I/O and I/O mapped I/O.
16. Explain the action carried out by the processor after occurrence of an interrupt.
17. What is DMA? Describe how DMA is used to transfer data from peripherals.
18. Explain various data transfer modes used in DMA.
19. Explain SCSI bus standards.
20. Describe the working principle of USB.

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