RajaRajeswari College of Engineering

(An Autonomous Institute, Affiliated Visvesvaraya Technological University, Belagavi ,

Approved by AICTE, UGC &GoK, Accredited by ISO 9001-2015 Certified Institution)
Sponsored by: MOOGAMBIGAI CHARITABLE AND EDUCATIONAL TRUST
Department of Electrical and Electronics Engineering
Course Code BEE403 CIE Marks 50
Teaching Hours/Week [Link] SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 8-10 Lab slots Total Marks 100
Credits 04 Exam Hours 03 HOURS

MODULE–I
8051 MICROCONTROLLER BASICS
Criteria for Choosing a Microcontroller
 Meeting the computing needs of the task at hand efficiently and cost effectively
o Speed
o Packaging
o Power consumption
o The amount of RAM and ROM on chip
o The number of I/O pins and the timer on chip
o How easy to upgrade to higher performance or lower power-consumption versions
o Cost per unit
 Availability of software development tools, such as compilers, assemblers, and debuggers
 Wide availability and reliable sources of the microcontroller
 The8051familyhasthelargestnumberofdiversified(multiplesource)suppliers
o Intel(original)
o Atmel
o Philips/Signetics
o AMD
o Infineon (formerly Siemens)
o Matra
o Dallas Semiconductor/Maxim
Difference between Microprocessor and Microcontroller

Microprocessor Microcontroller
Micro Controller is the heart of an embedded
Microprocessor is the heart of Computer system.
system.
It is only a processor, so memory and I/O Micro Controller has a processor along with
components need to be connected externally internal memory and I/O components.
Memory and I/O has to be connected externally, so Memory and I/O are already present, and the
the circuit becomes large. internal circuit is small.
You can’t use it in compact systems You can use it in compact systems.
As external components are low, total power
Due to external components, the total power
consumption is less. So it can be used with
consumption is high. Therefore, it is not ideal for the
devices running on stored power like
devices running on stored power like batteries.
batteries.
Most of the microprocessors do not have power Most of the microcontrollers offer power-
saving features. saving mode.
 Microprocessor Microcontroller
It is used mainly in a washing machine, MP3
It is mainly used in personal computers.
players, and embedded systems.
Microprocessor has a smaller number of registers, so Microcontroller has more register. Hence the
more operations are memory-based. programs are easier to write.
Micro controllers are based on Harvard
Microprocessors are based on Von Neumann model
architecture
It is a byproduct of the development of
It is a central processing unit on a single silicon-based
microprocessors with a CPU along with other
integrated chip.
peripherals.
It has no RAM, ROM, Input-Output units, timers, and It has a CPU along with RAM, ROM, and other
other peripherals on the chip. peripherals embedded on a single chip.
It uses an external bus to interface to RAM, ROM, and
It uses an internal controlling bus.
other peripherals.
Microcontroller based systems run up to
Microprocessor-based systems can run at a very high
200MHz or more depending on the
speed because of the technology involved.
architecture.
It’s used for general purpose applications that allow
It’s used for application-specific systems.
you to handle loads of data.
It’s complex and expensive, with a large number of It’s simple and inexpensive with less number
instructions to process. of instructions to process.

Difference between RISC and CISC

[Link]. RISC CISC

It stands for Reduced Instruction Set It stands for Complex Instruction Set
1.
Computer. Computer.

It is a microprocessor architecture
This offers hundreds of instructions of
2. that uses small instruction set of
different sizes to the users.
uniform length.

This architecture has a set of special purpose

These simple instructions are
3. circuits which help execute the instructions at
executed in one clock cycle.
a high speed.

These chips are relatively simple to

4. These chips are complex to design.
design.
 Arithmetic and logical operations can be
Arithmetic and logical operations only
5. applied to both memory and register
use register operands.
operands.

Registers are used for procedure The stack is used for procedure arguments
6.
arguments and return addresses. and return addresses.

7. It has less number of instructions. It has more number of instructions.

It has fixed-length encodings for It has variable-length encodings of

8.
instructions. instructions.

Simple addressing formats are The instructions interact with memory using
9.
supported. complex addressing modes.

Implementation programs exposed to Implementation programs are hidden from

machine-level programs. Few RISC machine-level programs. The ISA provides a
10.
machines do not allow specific clean abstraction between programs and how
instruction sequences. they get executed.

11. It doesn't use condition codes. Condition codes are used.

Difference between Von Neumann and Harvard Architecture

Parameters Von Neumann Architecture Harvard Architecture

Block
diagram

Definition The Von Neumann Architecture is an Harvard Architecture is a modern type

ancient type of computer architecture of computer architecture that follows
that follows the concept of a stored- the concept of the relay-based model
program computer. by Harvard Mark I.

Physical It uses one single physical address for It uses two separate physical addresses
Address accessing and storing both data and for storing and accessing both
instructions. instructions and data.

Buses (Signal One common signal path (bus) helps It uses separate buses for the transfer
Paths) in the transfer of both instruction and of both data and instructions.
data.

Number of It requires two clock cycles for It executes any instruction using only
Cycles executing a single instruction. one single cycle.

Cost It is comparatively cheaper in cost It is comparatively more expensive

than Harvard Architecture. than the Von Neumann Architecture.
 Access to The CPU is not able to read/write data The CPU can easily read/write data as
CPU and access instructions at the same well as access the instructions at any
time. given time.

Uses This method comes to play in the case This architecture is best for signal
of small computers and personal processing as well as microcontrollers.
computers.

Requirement As compared to Harvard Architecture, This one requires more hardware. It is

of Hardware Von Neumann Architecture requires because it requires separate sets of
lesser architecture. It is because it data as well as address buses for
only needs to reach one common individual memory.
memory.

Requirement This architecture basically requires This architecture comparatively

of Space less space. requires more space.

Usage of This architecture does not waste any This type of architecture can result in
Space space. It is because the instruction space wastage. It is because the
memory can utilize the left space of instruction memory cannot utilize the
the data memory leftover space in the data memory.

Execution The speed of execution of the Von The overall speed of execution of
Speed Neumann Architecture is Harvard Architecture is comparatively
comparatively slower. It is because it faster. It is because the processor, in
is not capable of fetching the this case, is capable of fetching both
instructions and data both at the same instructions and data at the very same
time. time.

Controlling The process of controlling becomes The process of controlling becomes

comparatively simpler with this comparatively complex with this
architecture. architecture.
DIFFERENCE BETWEEN MICROCONTROLLER AND EMBEDDED SYSTEM
Feature Microcontroller Embedded System
A single-chip computer with a A system designed to perform a dedicated function,
Definition processor, memory, and I/O which may include a microcontroller/microprocessor
peripherals. along with other hardware and software components.
May include a microcontroller/microprocessor,
CPU, RAM, ROM, I/O ports, timers,
Components sensors, actuators, power supply, communication
ADC, DAC, etc. (all on a single chip).
modules, and custom software.
Can be simple (e.g., microwave controller) or complex
Complexity Simpler, self-contained.
(e.g., automotive ECU).
Flexibility Limited by its fixed hardware. More flexible, as it can integrate multiple components.
Acts as the brain of an embedded
Purpose A complete system designed for a specific application.
system.
ATmega328 (Arduino), PIC16F877A, Washing machine controller, Smart thermostat,
Examples
STM32. Automotive infotainment system.
Typically programmed in C/C++ or Involves both hardware and software development (C,
Programming
Assembly. C++, RTOS, etc.).
Power Low power consumption. Depends on the system (can range from ultra-low to
Feature Microcontroller Embedded System
Consumption high power).
Varies (can be low-cost or expensive depending on
Cost Generally inexpensive.
complexity).

8051 Architecture

Salient features of 8051 microcontroller are given below.

 Eight bit CPU
 On chip clock oscillator
 4Kbytes of internal program memory (code memory) [ROM]
 128bytes of internal data memory [RAM]
 64Kbytes of external program memory address space.
 64 Kbytes of external data memory address space.
 32 bi directional I/O lines(can be used as four 8bit ports or 32 individually
addressable I/O lines)
 Two16BitTimer/Counter:T0, T1
 Full Duplex serial data receiver/transmitter
 Four Register banks with 8 registers in each bank.
 Sixteen bit Program counter (PC)and a data pointer (DPTR)
 8Bit Program Status Word (PSW)
 8 Bit Stack Pointer
 Five vectors interrupt structure (RESET not considered as an interrupt.)
 8051CPUconsists of 8bit ALU with associated registers like accumulator‘A’,B register, PSW,
SP, 16 bit program counter, stack pointer.
 ALU can perform arithmetic and logic functions on 8bit variables.
 8051 has 128 bytes of internal RAM which is divided into
o Working registers [00–1F]
o Bit address able memory area [20–2F]
o General purpose memory area (Scratch pad memory)[30-7F]
8051MicrocontrollerArchitecture

 8051 has 4 KBytes of internal ROM. The address space is from 0000 to 0FFFh. If the program
size is more than 4 KBytes, 8051 will fetch the code automatically from external memory.
 Accumulator is an 8-bit register widely used for all arithmetic and logical operations.
Accumulator is also used to transfer data between external memory. B register is used along
with Accumulator for multiplication and division. A and B registers together are also called
MATH registers.
 PSW (Program Status Word). This is an 8-bit register which contains the arithmetic status of
ALU and the bank select bits of register banks.
 The heart of the 8051 is the circuitry that generates the clock pulses by which all
internal operations are synchronized.
 Pins XTAL1 and XTAL2 are provided for connecting a resonant network to form an
oscillator.
 The 8051 requires an external oscillator circuit. The oscillator circuit usually runs
around 12 MHz. The crystal generates 12 million pulses in one second. The pulse is used
to synchronize the system operation in a controlled pace
 A machine cycle is the minimum amount of time a simplest machine instruction must
take
 An 8051 machine cycle consists of 12 crystal pulses (ticks).
 Instructions with a memory operand need multiple memory accesses (machine cycles).

A and B CPU Registers

• The 8051 contains 34 general-purpose, or working, registers. Two of
these ,registers A and B.

 The other 32 are arranged as part of internal RAM in four banks, B0–B3, of
eight registers each, named R0 to R7.
 The A (accumulator) register is used for many operations, including addition,
subtraction, integer multiplication and division, and Boolean bit
manipulations.
 The A register is also used for all data transfers between the 8051 and any
external memory.
 The B register is used with the A register for multiplication and division
operations.
 Program Counter (PC) and Data Pointer (DPTR)
 Program instruction bytes are fetched from locations in memory that are
addressed by the PC.
 The PC is automatically incremented after every instruction byte is fetched
and may also be altered by certain instructions.
 The PC is the only register that does not have an internal address.
 The DPTR register is made up of two 8-bit registers, named DPH and DPL.
 They are used to furnish memory addresses for internal and external code
access and external data access.
 The DPTR is under the control of program instructions.
 It can be specified by its 16-bit name, DPTR, or by each individual byte name,
DPH and DPL.
 DPTR does not have a single internal address; DPH and DPL are each assigned
an address.

Flags and the Program Status Word (PSW)

 Flags are 1-bit registers provided to store the results of certain program
instructions.
 Other instructions can test the condition of the flags and make decisions based
upon the flag states.
 The 8051 has four math flags that respond automatically to the outcomes of
math operations, and three general-purpose user flags that can be set to 1 or
cleared to 0 by the programmer as desired The math flags include carry (C),
auxiliary carry (AC), overflow (OV), and parity (P).
 User flags are named F0, GF0, and GF1; they are general-purpose flags.

Note that all of the flags can be set and cleared by the programmer.

7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV - P
The Stack and the Stack Pointer
• The stack refers to an area of internal RAM that is used in conjunction with certain opcodes to
store and retrieve data quickly.

• The 8-bit Stack Pointer (SP) register is used by the 8051 to hold an internal RAM address that
is called the "top of the stack."

• The top of the stack is the location in internal RAM where the last byte of data was stored by a
stack operation.

• The SP increments before storing data on the stack so that the stack grows upward as data is
stored.

• As data is retrieved from the stack, the byte is read from the stack, and then the SP decrements
to point to the next available byte of stored data.

• The SP is set to 07h when the 8051 is reset and can be changed to any internal RAM address by
the programmer.

Special Function Registers (SFRs)

 The 8051 has a group of specific internal registers, each called a Special Function Register
(SFR), which may be addressed much like internal RAM, using addresses from 80h to FFh.
  Some SFRs (marked with an asterisk *) are also bit-addressable; this feature allows the
programmer to change only what needs to be altered, leaving the remaining bits in that
SFR unchanged.
 Not all of the addresses from 80h to FFh are used for SFRs, and attempting to use an
address that is not defined or "empty" results in unpredictable behavior.
 SFRs are named in certain opcodes by their functional names, such as A or TH0, and are
referenced by other opcodes by their addresses, such as 0E0h or 8Ch.
 Note that any address used in the program must start with a number; thus, address E0h
for the A SFR begins with 0.
 Failure to use this number convention will result in an assembler error when the program
is assembled.

Pin Diagram
Pin out Description
Pins 1–8: PORT1
Each of these pins can be configured as an input or an output.

Pin 9: RESET
A logic one on this pin disables the microcontroller and clears the contents of most registers. In
other words, the positive voltage on this pin resets the microcontroller. By applying logic zero to
this pin, the program starts execution from the beginning.

Pins 10–17: PORT3

Similar to Port 1, each of these pins can serve as general input or output. Besides, all of them
have alternative functions:

 Pin 10: RXD – Serial asynchronous communication input or serial synchronous

communication output.
 Pin 11: TXD – Serial asynchronous communication output or serial synchronous
communication clock output.
 Pin 12: INT0 – External Interrupt 0 input.
 Pin 13: INT1 – External Interrupt 1 input.
 Pin 14: T0 – Counter 0 clock input.
 Pin 15: T1 – Counter 1 clock input.
 Pin 16: WR – Write to external (additional) RAM.
 Pin 17: RD – Read from external RAM.

Pins 18 & 19: XTAL2, XTAL1

Internal oscillator input and output. A quartz crystal which specifies operating frequency is
usually connected to these pins.

Pin 20: GND

Ground.

Pins 21–28: PORT2

If there is no intention to use external memory, then these port pins are configured as general
inputs/outputs. In case external memory is used, the higher address byte (i.e., addresses A8–
A15) will appear on this port. Even if memory with a capacity of 64KB is not used, meaning that
not all eight port bits are used for addressing, the rest of them are not available as
inputs/outputs.

Pin 29: PSEN

If external ROM is used for storing the program, then a logic zero (0) appears on it every time the
microcontroller reads a byte from memory.

Pin 30: ALE

Prior to reading from external memory, the microcontroller puts the lower address byte (A0–
A7) on P0 and activates the ALE output. After receiving the signal from the ALE pin, the external
latch latches the state of P0 and uses it as a memory chip address. Immediately after that, the
ALE pin returns to its previous logic state and P0 is now used as a Data Bus.

Pin 31: EA
By applying logic zero to this pin, P2 and P3 are used for data and address transmission with no
regard to whether there is internal memory or not. It means that even if there is a program
written to the microcontroller, it will not be executed. Instead, the program written to external
ROM will be executed. By applying logic one to the EA pin, the microcontroller will use both
memories — first internal, then external (if it exists).

Pins 32–39: PORT0

Similar to P2. If external memory is not used, these pins can be used as general inputs/outputs.
Otherwise, P0 is configured as:

 Address output (A0–A7) when the ALE pin is driven high (1), or
 Data output (Data Bus) when the ALE pin is driven low (0).

Pin 40: VCC

+5V power supply.

Internal Memory Organization

 A functioning computer must have:
o Memory for program code bytes, commonly in ROM.
o RAM memory for variable data that can be altered as the program runs.
 Additional memory can be added externally using suitable circuits.
 The 8051 has a Harvard architecture, which uses the same address in different
memories for code and data.
o Internal circuitry accesses the correct memory based upon the nature of the
operation in progress.
Internal RAM
 Thirty-two bytes from address 00h to 1Fh make up 32 working registers,
organized as four banks of eight registers each:
o Bank 0 – Bank 3 (with each bank having registers R0–R7)
 Each register can be addressed:
o By name (when its bank is selected)
o Or by its RAM address
 For example:
o R0 of Bank 3 is called R0 if Bank 3 is currently selected
o Or it can be accessed via address 18h, regardless of the selected bank
 The RS0 and RS1 bits in the PSW (Program Status Word) determine which bank
is currently in use
 Register banks that are not selected can be used as general-purpose RAM

 Bank 0 is selected upon reset.

 A bit-addressable area of 16 bytes occupies RAM addresses 20h to 2Fh, forming a
total of 128 addressable bits.
o Each bit can be referenced by:
 Its bit address (00h to 7Fh), or
 As bits in a byte (addresses 20h to 2Fh).
o Example: Bit address 4Fh is also bit 7 of byte address 29h.
 Bit-addressable areas are useful for tracking binary events (e.g., switch on/off, LED
status).
 The RAM area from 30h to 7Fh is general-purpose RAM, byte-addressable only.

Internal ROM
 The 8051 is designed such that data memory and program code memory are in
separate physical spaces but have the same address range.
 A block of internal ROM holds program code at addresses 0000h to 0FFFh.
 The Program Counter (PC) typically addresses program bytes in the 0000h–
0FFFh range.
 If the program exceeds 0FFFh, the 8051 automatically fetches code from
external program memory.
 If the EA pin (Pin 31) is connected to ground, the entire code is fetched from
external memory (0000h to FFFFh).
 The PC doesn’t care where the code resides; it’s up to the circuit designer to:
o Use only internal ROM
o Use only external ROM
o Or use a combination of both

Input/Output Pins, Ports, and Circuits

 Ports can be accessed directly by instructions during program execution.
 I/O ports are memory-mapped, so they are treated as memory locations.
 All ports are bit-addressable.
 Each pin consists of:
o A D latch
o An input buffer
 o An output driver
 Each port’s SFR is made of 8 latches.
 Ports can be accessed by their:
o SFR address
o Port name (e.g., P0, P1)
 The 8051 has four 8-bit I/O ports: P0, P1, P2, and P3, using 32 pins in total.
 Upon RESET, all ports are configured as output:
o When a 0 is written to a port, it acts as an output.
o To configure a port as input, a 1 must be written to the port.
 This enables input use of the corresponding pin.

External Memory (ROM & RAM) Interfacing with 8051

Example:
Interfacing 16KB of RAM and 32KB of EPROM to the 8051 Microcontroller

Memory Size & Address Lines Required:

Memory Type Size Address Lines Required Address Range
RAM 16 KB 14 lines 0000h – 3FFFh
EPROM 32 KB 15 lines 8000h – FFFFh (example)
 16 KB = 2^14 ⇒ 14 address lines
 32 KB = 2^15 ⇒ 15 address lines

Address Bus and Data Bus:

 Lower Address (A0–A7):
o Shared with Port 0
o Requires external latch to de multiplex address and data
 Higher Address (A8–A15):
o Provided through Port 2
 Data Bus:
o Also through Port 0
o After latching the lower address using ALE, Port 0 is used for data transfer
Control Signals from 8051:
 /RD (Read): Connected to RAM’s read enable pin
 /WR (Write): Connected to RAM’s write enable pin
 /PSEN (Program Store Enable): Connected to EPROM’s output enable pin
 ALE (Address Latch Enable): Used to latch the lower byte of address (A0–A7)

Typical Address Map Example:

Address Range Memory
0000h – 3FFFh RAM (16 KB)
8000h – FFFFh EPROM (32 KB)
Note: Address ranges can vary depending on how decoding is implemented in your
hardware.

Block Diagram Description (for visualization):

 8051
o Port 0 ↔ Multiplexed Address/Data Bus
o Port 2 ↔ Higher Address Lines (A8–A15)
o ALE → Controls Latch (e.g., 74LS373) for A0–A7
o /RD, /WR → RAM control
o /PSEN → EPROM control
 External Latch (e.g., 74LS373)
o Holds A0–A7 when ALE is high
 RAM & EPROM chips
o Connected with address, data, and control lines

Multiplexed Address/Data Bus and De-Multiplexing in 8051

Multiplexed Bus Concept:
 In the 8051 microcontroller, Port 0 is multiplexed to carry both:
o Lower-order address lines (A0–A7)
o Data lines (D0–D7)
 This technique saves microcontroller pins but requires external de-multiplexing.

De-Multiplexing Using Latch (e.g., 74LS373):

 Initially, the lower byte of the address appears on Port 0.
 ALE (Address Latch Enable) signal from the microcontroller becomes high, which:
 o Enables the latch to capture the lower byte of the address.
o The output of the latch is connected directly to A0–A7 of the memory.
 After address latching, Port 0 switches to carry data.

Connection Summary:
Signal Purpose Connected To
Port 0 Multiplexed A0–A7 / D0–D7 Data Bus + Latch
Port 2 Higher address lines (A8–A15) Connected directly to memory
Controls latch for lower address
ALE Latch enable pin
byte
/RD Read signal for data memory (RAM) RAM's Read Enable
/WR Write signal for data memory (RAM) RAM's Write Enable
Read signal for code memory
/PSEN EPROM's Output Enable
(EPROM)
Ground (GND) if only external memory is
EA (pin 31) External Access pin (active low)
used
EA (External Access) Pin Behavior:
 EA = 0 (connected to GND):
o Microcontroller uses only external memory for program code.
 EA = 1 (connected to Vcc):
o Microcontroller uses internal ROM first.
o If program exceeds internal ROM size, it switches to external ROM
automatically.

Memory Chip Organization and Capacity

1. Chip Capacity
 The chip capacity of a semiconductor memory is the total number of bits it can
store.
 Capacity is commonly expressed in:
o Kbits (Kilobits = 1024 bits)
o Mbits (Megabits = 1,048,576 bits)
o Gbits (Gigabits = 1,073,741,824 bits)

2. Memory Organization
 A memory chip is organized into a number of locations (or words).
 Each location can store:
o 1 bit, 4 bits, 8 bits, 16 bits, etc., depending on the chip design.

3. Role of Address and Data Pins

 The number of address pins (x) determines how many unique locations the chip
can have.
o A chip with x address lines can access 2ˣ memory locations.
 The number of data pins (y) determines how many bits each location can hold.

4. Memory Size Formula

 If a memory chip has:
 o x address pins ⇒ it can address 2ˣ locations
o y data pins ⇒ each location stores y bits
 🧠 Total chip capacity = 2ˣ × y bits

Example:
 A chip with 14 address pins and 8 data pins:
o Number of locations = 2¹⁴ = 16,384 (16K)
o Data per location = 8 bits (1 byte)
o Chip capacity = 2¹⁴ × 8 = 131,072 bits = 16 KB

ADDRESSING MODES IN 8051 MICROCONTROLLER

The 8051 microcontroller supports several addressing modes, which define how
operands (data) are accessed in instructions. Below is a tabular summary followed by a
detailed explanation:

Addressing Modes in 8051

Example Operand
Addressing Mode Description
Instruction Type
Immediate Data is given directly in the Constant
MOV A, #25H
Addressing instruction. value
Register Operands are in registers (R0-R7, A,
MOV A, R2 Register
Addressing B).
Operand is in an internal Memory
Direct Addressing MOV A, 30H
RAM/register. location
Register Indirect Uses a register (R0/R1 or DPTR) as a Pointer-based
MOV A, @R0
Addressing pointer to memory. access
Indexed Uses DPTR or PC + A to access code MOVC A, Lookup table
Addressing memory. @A+DPTR access

1. Immediate Addressing Mode

 The operand is a constant value provided in the instruction itself.

 Uses # symbol before the value.

 Example:
MOV A, #40H ; Loads 40H (hex) into the accumulator
MOV R3, #0FFH ; Loads FFH into Register R3
2. Register Addressing Mode
 Operands are registers (R0-R7, A, B, etc.).

 Faster than memory access.

 Example:
MOV A, R5 ; Copies value from R5 to A
ADD A, R2 ; Adds R2 to A
3. Direct Addressing Mode
 Operand is a memory location (internal RAM or SFR).

 Uses an 8-bit address (00H–FFH).

 Example:
MOV A, 30H ; Copies data from RAM location 30H to A
MOV 40H, A ; Stores A’s value in RAM location 40H
4. Register Indirect Addressing Mode
 A register (R0 or R1) holds the address of the operand.

 Used for accessing external RAM or internal RAM indirectly.

 Example:
MOV @R0, A ; Stores A’s value at the address in R0
MOV A, @R1 ; Loads A from the address in R1
5. Indexed Addressing Mode
 Used with lookup tables in code memory (ROM).

 Combines DPTR (Data Pointer) or PC (Program Counter) with A (Accumulator).

 Example:
MOVC A, @A+DPTR ; Reads from ROM at (A + DPTR)
MOVC A, @A+PC ; Reads from ROM at (A + PC)

3. Comparison of Addressing Modes

Mode Speed Memory Access Usage
Immediate Fast None (constant) Loading constants
Arithmetic
Register Fastest None (register)
operations
Direct Medium Internal RAM/SFR Accessing variables
Indirect Slow External/Internal RAM Pointers, arrays
Indexed Slow ROM (code memory) Lookup tables