Module-2

Combinational Logic
Syllabus:
Combinational Logic: Introduction, Combinational Circuits, Design Procedure,
Binary Adder- Subtractor, Decoders, Encoders, Multiplexers. HDL Models of
Combinational Circuits – Adder, Multiplexer, Encoder.
Sequential Logic: Introduction, Sequential Circuits, Storage Elements: Latches, Flip-
Flops.

Combinational Logic: Introduction, Combinational Circuits, Design Procedure, Binary

Adder- Subtractor, Decoders, Encoders, Multiplexers. HDL Models of Combinational
Circuits – Adder, Multiplexer, Encoder. Sequential Logic: Introduction, Sequential Circuits,
Storage Elements: Latches, Flip-Flops.
Introduction
Logic circuits for digital systems may be combinational or sequential.
• A combinational circuit consists of logic gates whose outputs at any time are determined
from only the present combination of inputs.
• A combinational circuit performs an operation that can be specified logically by a set
of Boolean functions.
• sequential circuits employ storage elements in addition to logic gates. Their outputs are
a function of the inputs and the state of the storage elements
• Because the state of the storage elements is a function of previous inputs, the outputs
of a sequential circuit depend not only on present values of inputs, but also on past
inputs, and the circuit behavior must be specified by a time sequence of inputs and
internal states.
combinational circuit
A combinational circuit consists of an interconnection of logic gates.
• Combinational logic gates react to the values of the signals at their inputs and produce
the value of the output signal, transforming binary information from the given input
data to a required output data.

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 The n input binary variables come from an external source; the m output variables are produced
by the internal combinational logic circuit and go to an external destination.
Each input and output variable exists physically as an analog signal whose values are
interpreted to be a binary signal that represents logic 1 and logic 0.

• If the registers are included with the combinational gates, then the total circuit must be
considered to be a sequential circuit.
• For n input variables, there are 𝟐𝒏 possible combinations of the binary inputs.
• For each possible input combination, there is one possible value for each output
variable. Thus, a combinational circuit can be specified with a truth table that lists the
output values for each combination of input variables.
Design procedure
The procedure to design combinational circuits involves the following steps:
1. From the specifications of the circuit, Determine the required number of inputs and
outputs and assign a symbol to each.
2. Derive the truth table that defines the required relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for each output as a function of the input
variables.
4. Draw the logic diagram and verify the correctness of the design (manually or by
simulation).
Example for design Procedure
Code Conversion (Convert BCD to Excess-3 Code)

• A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code.
• Since each code uses four bits to represent a decimal digit, there must be four input
variables and four output variables. We designate the four input binary variables by the
symbols A, B, C, and D, and the four output variables by w, x, y and z.
• ADD 3 to BCD to get Excess -3 Code

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 Note that four binary variables ay have 16-bit combinations, but only 10 are listed in the truth
table. The six-bit combinations not listed for the input variables are don’t- care combinations.

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 Binary Adder- Subtractor
• A combinational circuit that performs the addition of two bits is called a half adder.
• The addition of three bits (two significant bits and a previous curry) is a full adder.
• A binary adder–subtractor is a combinational circuit that performs the arithmetic
operations of addition and subtraction with binary numbers.
• The half-adder design is carried out first, from which we develop the full adder.
• Connecting full adders in cascade produces a binary adder for two n -bit numbers.
Half Adder

• Half Adder circuit needs two binary inputs and two binary outputs.
• output variables produce the sum and carry. We assign symbols x and y to the two inputs
and S (for sum) and C (for carry) to the outputs.
• The C output is 1 only when both inputs are 1. The S output represents the least
significant bit of the sum.
• The truth table for the half adder is listed in Table 4.3.

The simplified Boolean functions for the two outputs can be obtained directly from
the truth table. The simplified sum-of-products expressions are

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 The logic diagram of the half adder implemented in sum of products is shown in Fig. 4.5(a).
It can be also implemented with an exclusive-OR and an AND gate as shown in Fig. 4.5(b)

Full Adder
• A full adder is a combinational circuit that forms the arithmetic sum of three bits. It
consists of three inputs and two outputs.
• Two of the input variables, denoted by x and y , represent the two significant bits to be
added. The third input, z , represents the carry from the previous lower significant
position. The two outputs are designated by the symbols S for sum and C for carry.

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 • The logic diagram for the full adder implemented in sum-of-products form is shown in
Fig. 4.7

Implementation of Full adder using 2 half adder:

We know that
S=xy’z’ + x’yz’ + xyz + x’y’z C=xy+xz+yz
=z’(xy’+x’y)+z(xy+x’y’) =xy+xz(y+y’)+yz(x+x’)
=z’(xy’+x’y)+z(x’y+xy’)’ =xy+xyz+xy’z+xyz+x’yz
=z’(x ⊕ y)+z(x ⊕ y)’ =xy+xyz+z(xy’+x’y)
=z’A+zA’ =xy(1+z)+z(x^y)
=z ⊕ A C=xy+z(x⊕y)
S=z ⊕ x ⊕y

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 Binary Adder:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers.
It can be constructed with full adders connected in cascade, with the output carry from
each full adder connected to the input carry of the next full adder in the chain.
• n-bit numbers require a chain of n full adders or a chain of one-half adder and n-1 full
adders.
• Eg:4bit numbers require a chain of 4 full adders or one HA and 3FAs.
• interconnection of four full-adder (FA) circuits to provide a four-bit binary ripple carry
adder
• The augend bits of A and the addend bits of B are designated by subscript numbers from
right to left, with subscript 0 denoting the least significant bit. The carries are connected
in a chain through the full adders. The input carry to the adder is C0, and it ripples
through the full adders to the output carry C4.

The input carry C0 in the least significant position must be 0.

The value of Ci+1 in a given significant position is the output carry of the full adder.
The carry propagation time is an important attribute of the adder because it limits the speed
with which two numbers are added.

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 1. write Verilog code for 4 bit parallel adder using full adder as component.

2. Write Verilog code for 4 bit adder.

There are several techniques for reducing the carry propagation time in a parallel adder. The
most widely used technique employs the principle of carry lookahead logic.
Carry Propagation
• Carry Propagation The addition of two binary numbers in parallel implies that all the
bits of the augend and addend are available for computation at the same time.
• Consider the circuit of the full adder shown in Fig. 4.10 . If we define two new binary
variables.
• Gi is called a carry generate , and it produces a carry of 1 when both Ai and Bi are 1,
regardless of the input carry Ci .
• Pi is called a carry propagate , because it determines whether a carry into stage i will
propagate into stage i + 1

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 •

Binary ADDER-Subtractor
The addition and subtraction operations can be combined into one circuit with one common
binary adder by including an exclusive-OR gate with each full adder.

A four-bit adder–subtractor circuit is shown in Fig. 4.13 . The mode input M controls the
operation. When M = 0, the circuit is an adder, and when M = 1, the circuit becomes a
subtractor. Each exclusive-OR gate receives input M and one of the inputs of B.

When M = 0, we have B ⊕0 = B. The full adders receive the value of B , the input carry is 0,
and the circuit performs A plus B . When M = 1, we have B ⊕ 1 = B’ and C0 = 1. The B inputs
are all complemented and a 1 is added through the input carry. The circuit performs operation
A plus the 2’s complement of B . (The exclusive-OR with output V is for detecting an overflow.)

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 Binary Addition Example:

Binary Subtraction Example:

DECODERS
• A Decoder is a combinational circuit that converts binary information from n input lines
to a maximum of 2𝑛 unique output lines.
• The decoders presented here are called n -to- m -line decoders, where m … 2𝑛 . Their
purpose is to generate the 2n (or fewer) minterms of n input variables.
• Each combination of inputs will assert a unique output. The name decoder is also used
in conjunction with other code converters, such as a BCD-to-seven-segment decoder.
2:4 decoder (1 of 4 decoder)
A 2 to 4 decoder is a combinational logic circuit that takes two input lines, typically labeled
A and B, and generates four output lines, usually labeled Q0, Q1, Q2, and Q3. The decoder
analyzes the input combination and activates the corresponding output line

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 3:8 Decoder
• A 3 to 8 decoder has three inputs (x,y,z) and eight outputs (D0 to D7).
• Based on the 3 inputs one of the eight outputs is selected.
• The truth table for 3 to 8 decoder is shown in the below table.
• From the truth table, it is seen that only one of eight outputs (D0 to D7) is selected
based on three select inputs.  From the truth table, the logic expressions for
outputs can be written as follows:

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 Decoders with enable inputs can be connected together to form a larger decoder circuit.
Implement 4:16 decoder using 2 3:8 decoder.
two 3-to-8-line decoders with enable inputs connected to form a 4-to-16-line decoder.
When w =0, the top decoder is enabled and the other is disabled. The bottom decoder outputs
are all 0’s, and the top eight outputs generate minterms 0000 to 0111.
When w =1, the enable conditions are reversed: The bottom decoder outputs generate minterms
1000 to 1111.

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 Combinational Logic Implementation
Implement the following boolean function using 3:8 decoder

S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
Since there are three inputs and a total of eight minterms, we need a three-to-eight-line decoder.

The decoder generates the eight minterms for x , y , and z . The OR gate for output S
forms the logical sum of minterms 1, 2, 4, and 7. The OR gate for output C forms the
logical sum of minterms 3, 5, 6, and 7.
Exemplify (Implement) the following function using 3:8 decoder
i) f(a,b, c,d)=Σm (L,2, 3,4)
ii) ii) f(a,b, c, d)=Σm (3,5,7 )

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 Encoder

An encoder is a digital circuit that performs the inverse operation of a decoder.

• An encoder has 2𝑛 (or fewer) input lines and n output lines.
• 4:2 Encoder(n=2)

4:2 Encoder

8:3 Encoder

• An encoder is the octal-to-binary encoder whose truth table is given in Table 4.7
• It has eight inputs (one for each of the octal digits) and three outputs that generate the
corresponding binary number. It is assumed that only one input has a value of 1 at any
given time.
• The encoder can be implemented with OR gates whose inputs are determined directly
from the truth table
• Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7.
• Output y is 1 for octal digits 2, 3, 6, or 7, and
• output x is 1 for digits 4, 5, 6, or 7.

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 • The encoder defined in Table 4.7 has the limitation that only one input can be active at any
given time. If two inputs are active simultaneously, the output produces an undefined
combination. For example, if D3 and D6 are 1 simultaneously, the output of the encoder
will be 111 because all three outputs are equal to 1.
• To resolve this ambiguity, encoder circuits must establish an input priority to ensure that
only one input is encoded.
• The output 111 does not represent either binary 3 or binary 6. To resolve this ambiguity,
encoder circuits must establish an input priority to ensure that only one input is encoded. If
we establish a higher priority for inputs with higher subscript numbers, and if both D3 and
D6 are 1 at the same time, the output will be 110 because D6 has higher priority than D3.
Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is generated
when all the inputs are 0; but this output is the same as when D0 is equal to 1. The
discrepancy can be resolved by providing one more output to indicate whether at least one
input is equal to 1.

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 Priority Encoder

• A priority encoder is an encoder circuit that includes priority function.

• The operation of the priority encoder is such that if two or more inputs are equal to 1 at the
same time, the input having the highest priority will take precedence.
• The truth table of a four-input priority encoder is given in Table 4.8

• In addition to the two outputs x and y , the circuit has a third output designated by V ; this
is a valid bit indicator that is set to 1 when one or more inputs are equal to 1.
• If all inputs are 0, there is no valid inut and V is equal to 0. The other two outputs are not
inspected when V equals 0 and are specified as don’t-care conditions.
• Input D3 has the highest priority, so, regardless of the values of the other inputs, when this
input is 1, the output for xy is 11 (binary 3).
• D2 has the next priority level. The output is 10 if D2 = 1, provided that D3 = 0, regardless
of the values of the other two lower priority inputs. The output for D1 is generated only if
higher priority inputs are 0.

0 0 1 1 1 1 1

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 0 1 0 0 0 1 1

0 1 0 1 1 1 1

0 1 1 0 1 0 1

0 1 1 1 1 1 1

1 0 0 0 0 0 1

1 0 0 1 1 1 1

1 0 1 0 1 0 1

1 0 1 1 1 1 1

1 1 0 0 0 1 1

1 1 0 1 1 1 1
1 1 1 0 1 0 1

1 1 1 1 1 1 1

Multiplexer
A multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line
• The selection of a particular input line is controlled by a set of selection lines
• Normally, there are 2𝑛 input lines and n selection lines whose bit combinations
determine which input is selected.

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 Design 2:1 Multiplexer

𝑦 = 𝑠′𝐼0 + 𝑠𝐼1

Boolean Expression

A 2-to-1 multiplexer consists of two inputs, I0 and I1, one select input S and one output Y.
Depending on the select signal, the output is connected to either of the inputs. Since there are
two input signals, only two ways are possible to connect the inputs to the outputs, so one select
is needed to do these operations.

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 4:1 Multiplexer

Above figures represents block diagram ,truth table and implementation using basic gates of
4:1 multiplexer.
4x1 Multiplexer has four data inputs I0, I1, I2 & I3, two selection lines S0 & S1 and one
output Y. One of these 4 inputs will be connected to the output based on the combination of
inputs present at these two selection lines.
8:1 multiplexer

• Multiplexer circuits can be combined with common selection inputs to provide

multiple-bit selection logic. As an illustration, a quadruple 2-to-1-line multiplexer is
shown in Fig. 4.26. The circuit has four multiplexers, each capable of selecting one of two

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 input lines. Output Y0 can be selected to come from either input A0 or input B0. Similarly,
output Y1 may have the value of A1 or B1, and so on. Input selection line S selects one of
the lines in each of the four multiplexers. The enable input E must be active (i.e., asserted)
for normal operation.
• As shown in the function table, the unit is enabled when E = 0. Then, if S = 0, the four A
inputs have a path to the four outputs. If, by contrast, S = 1, the four B inputs are applied
to the outputs. The outputs have all 0’s when E = 1, regardless of the value of S.

Design 4:1 MUX using only 2:1 MUX

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 Implement 8:1 Mux using 4:1mux and 2:1mux

8:1 MUX Truth Table

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 Implement using multiplexer F (x, y, z) = (1, 2, 6, 7)

n=3 n- 1=2 select lines

𝟐𝒏−𝟏 =4 data inputs

Implement using multiplexer F
(A, B, C, D) = (1, 3, 4, 11, 12, 13,
14, 15)

Three-State Gates

• A multiplexer can be constructed with three-state gates—digital circuits that exhibit

three states.
• Two of the states are signals equivalent to logic 1 and logic 0 as in a conventional gate.
• The third state is a high-impedance state in which
(1) the logic behaves like an open circuit, which means that the output appears to be
disconnected,
(2) the circuit has no logic significance, and
(3) the circuit connected to the output of the three-state gate is not affected by the inputs
to the gate. Three-state gates may perform any conventional logic, such as AND or
NAND. However, the one most commonly used is the buffer gate.

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 • The graphic symbol for a three-state buffer gate is

The buffer has a normal input, an output, and a control input that determines the state of the
output. When the control input is equal to 1, the output is enabled and the gate behaves like a
conventional buffer, with the output equal to the normal input. When the control input is 0, the
output is disabled and the gate goes to a high-impedance state, regardless of the value in the
normal input. The high-impedance state of a three-state gate provides a special feature not
available in other gates. Because of this feature, a large number of three-state gate outputs can
be connected with wires to form a common line without endangering loading effects.

• The construction of multiplexers with three-state buffers is demonstrated in Fig. 4.30.

Figure 4.30(a) shows the construction of a two-to-one-line multiplexer with 2 three-
state buffers and an inverter. The two outputs are connected together to form a single
output line. (Note that this type of connection cannot be made with gates that do not
have three- state outputs.) When the select input is 0, the upper buffer is enabled by its
control input, and the lower buffer is disabled. Output Y is then equal to input A . When
the select input is 1, the lower buffer is enabled, and Y is equal to B.

Y=AS’+BS

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 HDL models of combinational circuits
• The logic of a module can be described in any one (or a combination) of the following
modeling styles:
• Behavioral modeling using procedural assignment statements with the keyword
always.
• Gate-level (structural) modeling describes a circuit by specifying its gates and how
they are connected with each other. Gate-level modeling using instantiations of
predefined and user-defined primitive gates
• Dataflow modeling is used mostly for describing the Boolean equations of
combinational logic, Dataflow modeling using continuous assignment statements with
the keyword assign.

Write a Verilog Program for Binary Adder(4bit )

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 Write a Verilog code for 2:1 mux(multiplexer)
Using Conditional Operator

𝑦 = 𝑠′𝐼0 + 𝑠𝐼1

Using Data flow Model

Behavioral modelling for 2:1 Mux

Using Case Statement using If else statement

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 Write Verilog program for 4:1mux using CASE STATEMENT

Timing Diagram

Write a Verilog code for below figure

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 Sequential Logic

➢ Sequential logic refers to a type of digital logic circuit that uses memory elements
to store information.
➢ It consists of a combinational circuit to which storage elements are connected to
form a feedback path. The storage elements are devices capable of storing binary
information.
➢ sequential circuit is specified by a time sequence of inputs, outputs, and internal
states.

Differentiate between combinational logic and sequential logic

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 ➢ The storage elements (memory) used in clocked sequential circuits are called
flipflops.
➢ A flip-flop is a binary storage device capable of storing one bit of information.

Storage Elements:
1) Latches:
➢ Latches are digital circuits that serve as basic building blocks in the
construction of sequential logic circuits.
➢ They are bistable, meaning they have two stable states and can be used to
store binary information. Latches are often used for temporary storage of
data within a digital system.
➢ There are several types of latches, with the most common being the
1)SR latch (Set-Reset latch), 2)D latch (Data latch),3) JK latch.
• Storage elements that operate with signal levels (rather than signal
transitions) are referred to as latches; those controlled by a clock
transition are [Link] are said to be level sensitive devices; flip-
flops are edge-sensitive [Link] two types of storage elements are
related because latches are the basic circuits from which all flip- flops are
constructed.

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 SR Latch (Set-Reset Latch):

• The SR latch has two inputs, S (Set) and R (Reset).It has two outputs, Q and
~Q (complement of Q).
• When S is asserted, Q is set to 1, and when R is asserted, Q is reset to [Link]
SR latch is sensitive to the input conditions, and having both S and R asserted
simultaneously can lead to unpredictable behavior.

SR Latch with nor gates

where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR
logic gates. The stored bit is present on the output marked Q.

While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant
state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then
the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high
while S is held low, then the Q output is forced low, and stays low when R returns to low.

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 SR latch with controlinput

It consists of the basic SR latch and two additional NAND gates. The control input En acts as
an enable signal for the other two inputs. The output of the NAND gates stays at the logic-1
level as long as the enable signal remains at 0. This is the quiescent condition for the SR latch.
When the enable input goes to 1, information from the S or R input is allowed to affect the
latch. The set state is reached with S = 1, R = 0, and En = 1 active-high enabled). To change to
the reset state, the inputs must be S = 0, R = 1, and En = 1. In either case, when En returns to
0, the circuit remains in its current state. The control input disables the circuit by applying 0 to
En, so that the state of the output does not change regardless of the values of S and R. Moreover,
when En = 1 and both the S and R inputs are equal to 0, the state of the circuit does not change.
These conditions are listed in the function table accompanying the diagram.

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 D latch (transparent latch)
A D latch can store a bit value, either 1 or 0. When its Enable pin is HIGH, the value on the
D pin will be stored on the Q output.
The D Latch is a logic circuit most frequently used for storing data in digital systems. It is
based on the S-R latch, but it doesn’t have an “undefined” or “invalid” state problem.

One way to eliminate the undesirable condition of the indeterminate state in the SR latch
is to ensure that inputs S and R are never equal to 1 at the same time. This is done in the
D latch, shown in Fig. 5.6. This latch has only two inputs: D (data) and En (enable). The D
input goes directly to the S input, and its complement is applied to the R input. If the
enable input is at 0, the cross-coupled SR latch has both inputs at the 1 level, and the
circuit cannot change state regardless of the value of D. The D input is sampled when En
= 1.

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 If D = 1, the Q output goes to 1, placing the circuit in the set state. If D = 0, output Q
goes to 0, placing the circuit in the reset state.

The graphic symbols for the various latches are shown in Fig. 5.7 . A latch is
designated by a rectangular block with inputs on the left and outputs on the right. One
output designates the normal output, and the other (with the bubble designation)
designates the complement output

STORAGE ELEMENTS: FLIP – FLOPS

▶ Flip-flops are fundamental building blocks in digital electronics and sequential

logic circuits.

▶ They are bistable multivibrators, like latches, but they are edge- triggered and

use a clock signal to control the timing of state changes.

▶ Flip-flops are widely used for storing binary information in electronic systems.

Edge triggered DFF

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 The construction of a D flip-flop with two D latches and an inverter is shown in Fig. 5.9.
The first latch is called the master and the second the slave. The circuit samples the D
input and changes its output Q only at the negative edge of the synchronizing or
controlling clock (designated as Clk ). When the clock is 0, the output of the inverter is 1.
The slave latch is enabled, and its output Q is equal to the master output Y. The master
latch is disabled because Clk = 0. When the input pulse changes to the logic-1 level, the
data from the external D input are transferred to the master. The slave, however, is
disabled as long as the clock remains at the 1 level, because it enable input is equal to 0.
Any change in the input changes the master output at Y but cannot affect the slave output.
When the clock pulse returns to 0, the master is disabled and is isolated from the D input.
At the same time, the slave is enabled, and the value of Y is transferred to the output of
the flip-flop at Q . Thus, a change in the output of the flip-flop can be triggered only by and
during the transition of the clock from 1 to 0.

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 Comparison between Latch and Flipflop

construction of an positive edge-triggered D flip-flop uses three SR latches

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 JK FLIPFLOP

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.

When both J = K = 1 and D = Q, the next clock edge complements the output.

When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

T Flipflop

T Flipflop using JK Flipflop

T = 0 (J = K = 0), a clock edge does not change the output. When T = 1 (J = K = 1), a
clock edge complements the output. Complementing flip-flop is useful for esigning
binary counters.

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 Implementation of TFF using DFF

The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gate as shown in
Fig. (b). The expression for the D input is D = T ⊕ Q = T’Q + TQ’ When T = 0, D = Q and
there is no change in the output. When T = 1, D = Q’ and the output complements.

D=T^Q

D=T’Q+TQ’

➢ Characteristic table characteristic table defines the logical properties of a flip-flop by

describing its operation in tabular form. They define the next state (i.e., the state that
results from a clock transition) as a function of the inputs and the present state
➢ Q (t) denotes the state of the flip-flop immediately before the clock edge, and
➢ Q (t + 1) denotes the state that results from the clock transition.

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 Characteristic equation
▶ It is the Boolean expression in terms of its input and output which determines

the next state of the flipflop.

T FF

DFF

JKFF

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 Write Verilog code for Flipflops

SR flipflop JK Flipflop

D flipflop T Flipflop

**************************************************

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