TRANSISTOR CHARACTERISTICS

BJT:

Junction transistor,

Transistor current components,

Transistor equation,

Transistor configurations,

Transistor as an amplifier,

Characteristics of transistor in Common Base,

Common Emitter and Common Collector configurations,

Ebers-Moll model of a transistor,

Punch through/ reach through,

Photo transistor,

Typical transistor junction voltage values

FET:

FET types, construction, operation, characteristics, parameters,

MOSFET-types, construction, operation, characteristics,

Comparison between JFET and MOSFET.

Transistor:
A bipolar junction transistor (BJT) is a three terminal device in which operation
depends on the interaction of both majority and minority carriers and hence the name bipolar.
It is used in amplifier and oscillator circuits, and as a switch in digital circuits. It has wide
applications in computers, satellites and other modern communication systems.

Transistor = Trans + istor

Trans means signal transfer property of the device and istor means belong to the
family of resistors. A transistor consists of 3 terminals. They are,

1. Emitter (E)
2. Base (B) and
3. Collector (C).

Emitter which emits the charge carriers, collector collects the charge carriers through
base. In order to emit the charge carriers emitter is heavily doped, collector is moderately
doped and base is lightly doped. The width of collector is more compared to base and emitter.
Base width is very small compared to emitter. Collector width is made wider than emitter in
order to dissipate the heat produced whenever it collects the charge carriers.

BJT‟s are classified into two types. They are

1. NPN transistor
2. PNP transistor

NPN Transistor:

The semi conductor representation and symbolic representation of an npn transistor is

shown in the following figure.

Figure: Semi conductor representation of npn transistor Figure: Symbolic representation of

npn transistor

From the diagram an npn transistor is constructed by sandwiching a p type semi

conductor between two n-type semi conductors. Here we have two n-type semi conductors
and one p type semi conductor, hence the majority charge carriers in npn transistor is
electrons and minority charge carriers are holes. Current is produced by both majority and
minority charge carriers. The arrow mark in the symbol represents the conventional current
direction.

Biasing:

On order to emit the charge carriers, emitter is always forward biased and to collect
the charge carriers collector is connected in reverse bias. The biasing of npn transistor is
shown below.

Figure: Biasing of npn transistor

Working:

Figure: Working of npn transistor

If the transistor is connected as per the above biasing. Charge carriers (electrons) from
emitter will move towards collector. N-type emitter is connected to the negative terminal of
the battery, the charge carriers will repel from that moves towards base and attracted towards
n-type collector is connected to positive terminal of the battery. If we take emitter base
junction, it is forward biased. The conventional current direction is shown in the above
figure. Means in the transistor symbol arrow represents the conventional current direction.

The total emitter current is the sum of base and collector currents.

IE = IB + IC

If we assume emitter current is 100%, then base current is 10% and collector current is 90%.
PNP Transistor:

The semi conductor representation and symbolic representation of an npn transistor is

shown in the following figure.

Figure: Semi conductor representation of pnp transistor Figure: Symbolic representation of

pnp transistor

From the diagram an pnp transistor is constructed by sandwiching a n type semi

conductor between two p-type semi conductors. Here we have two p-type semi conductors
and one n type semi conductor, hence the majority charge carriers in pnp transistor is holes
and minority charge carriers are electrons. Current is produced by both majority and minority
charge carriers. The arrow mark in the symbol represents the conventional current direction.

Biasing:

On order to emit the charge carriers, emitter is always forward biased and to collect
the charge carriers collector is connected in reverse bias. The biasing of pnp transistor is
shown below.

Figure: Biasing of npn transistor

Working:

If the transistor is connected as per the above biasing. Charge carriers (holes) from
emitter will move towards collector. p-type emitter is connected to the positive terminal of
the battery, the charge carriers will repel from that moves towards base and attracted towards
p-type collector is connected to negative terminal of the battery. If we take emitter base
junction, it is forward biased. The conventional current direction is shown in the above
figure. Means in the transistor symbol arrow represents the conventional current direction.

Figure: Working of pnp transistor

The total emitter current is the sum of base and collector currents.

IE = IB + IC

If we assume emitter current is 100%, then base current is 10% and collector current is 90%.

Transistor Current components:

The current components in a transistor when emitter is forward biased and collector is
reverse biased. The emitter current is the sum of hole current IpE (holes from emitter to base)
and electron current InE (electrons from base to emitter). The ratio of hole to electron current
IpE/InE is proportional to the conductivity of p type to n type material.

Figure: Current components in a transistor

IpE and InE are the diffusion currents. Then the minority carrier diffusion currents crossing the
junction is represented as IpE(0) and InE(0).

The total current crossing the junction is I=IpE+InE

When the holes moves towards the collector junction, they will recombine with the electrons
in the base. The current because of holes after recombination is IpC1. The recombination hole
current is IpE - IpC1.

Let us consider the emitter is open circuited, collector junction remains reverse
biased. Then the reverse saturation current ICO flows and it consists of two components, InCO
and IpCO.

- ICO = InCO + IpCO

Since, IE=0, no holes reaches to collector, then IpCO results from the small concentration of
holes generated thermally in the base.

IC = ICO – IpC1 =ICO - αIE

α is defined as the fractional of the total emitter current.

Large Signal Current gain (α):

It is defined as the ratio of the negative of the collector-current increment from cutoff
to the emitter current change from cutoff.

𝐼𝐶 − 𝐼𝐶𝑂
𝛼=−
𝐼𝐸 − 0

α is called as the large signal current gain. It lie in the range 0.9 to 0.95.

Transistor Equation:
The generalized transistor, replace ICO with the current in the diode.

𝐼𝐶 = −𝛼𝐼𝐸 + 𝐼𝐶𝑂 1 − 𝑒 𝑉𝐶 𝑉𝑇

In the above equation, IO is replaced with - ICO and V is replaced with VC.

If VC is very large, then 𝑒 𝑉𝐶 𝑉𝑇

is very small and neglected.

𝐼𝐶 = −𝛼𝐼𝐸 + 𝐼𝐶𝑂

We know that, IE= - (IC+IB)

𝐼𝐶 = −𝛼 (−(𝐼𝐶 + 𝐼𝐵 )) + 𝐼𝐶𝑂

𝐼𝐶 = 𝛼𝐼𝐶 + 𝛼𝐼𝐵 + 𝐼𝐶𝑂

𝐼𝐶 1 − 𝛼 = 𝛼𝐼𝐵 + 𝐼𝐶𝑂
𝛼
𝐼𝐶 = 𝐼 + 𝐼𝐶𝑂
1−𝛼 𝐵
 1
𝐼𝐶 = 𝛽𝐼𝐵 + 𝐼
1 − 𝛼 𝐶𝑂

𝐼𝐶 = 𝛽𝐼𝐵 + (1 + 𝛽)𝐼𝐶𝑂
𝛼
𝑆𝑖𝑛𝑐𝑒, 𝛽 =
1−𝛼

Transistor Configurations:
In order to construct a circuit, we need two input and two output terminals. Whereas a
transistor has only 3 terminals. Hence, one terminal is made as common to input and output.
Accordingly, we have three terminals, so we have three types of configurations. They are

1. Common Base configuration

2. Common Emitter configuration
3. Common Collector configuration

If we consider a simple two port network, we have input current, input voltage, output
current and output voltage. Out of the four parameters, two are taken as independent and two
are taken as dependent parameters for the convenience.

Dependent Parameters: Input Voltage, Output Current

Independent Parameters: Input Current, Output Voltage

Input Voltage = f(Input Current, Output Voltage)-------------(1)

Output Current=f(Input Current, Output Voltage)------------(2)

Equation 1 is helpful for obtaining the input characteristics and 2 for output characteristics.

Common Base (CB) configuration:

In common base configuration, base is common to input and output. The circuit
diagram for CB configuration is shown below.

Figure: Circuit Diagram of CB configuration

Here the input is applied between the base and emitter terminals and the corresponding output
signal is taken between the base and collector terminals with the base terminal grounded.
Here the input parameters are VEB and IE and the output parameters are VCB and IC. The input
current flowing into the emitter terminal must be higher than the base current and collector
current to operate the transistor, therefore the output collector current is less than the input
emitter current.

The input parameters are VEB, IE and the output parameters are VCB and IC.

VEB = f(IE, VCB) ---------(1)

IC = f(IE, VCB) ---------(2)

Input Characteristics

Equation1 is used for plotting input characteristics. Input characteristics are obtained
between input current and input voltage with constant output voltage. First keep the output
voltage VCB constant and vary the input voltage VEB for different points then at each point
record the input current IE value. Repeat the same process at different output voltage levels.
Now with these values we need to plot the graph between IE and VEB parameters. The below
figure show the input characteristics of common base configuration.

Figure: Input Characteristics of CB configuration

If reverse bias voltage of C-B junction is keep on increasing, a situation arises where
E-B and C-B space charge regions touch each other, and the width of the quasi-neutral base
region becomes zero, Known as base punch through.

As there is an increase in collector voltage, depletion width increases, this in turn decreases
effective base width. This is called as early effect.

Output Characteristics

Equation2 is used for plotting output characteristics. The output characteristics of

common base configuration are obtained between output current and output voltage with
constant input current. First keep the emitter current constant and vary the VCB value for
different points, now record the IC values at each point. Repeat the same process at different
IE values. Finally we need to draw the plot between VCB and IC at constant IE. The below
figure show the output characteristics of common base configuration.

Figure: Output characteristics of CB configuration

Input Bias Output Bias Region of operation Application

Reverse Reverse Cut off OFF Switch

Forward Reverse Active Amplifier

Forward Forward Saturation ON Switch

Reverse Forward Inverse Active Attenuator

Transistor parameters:
∆𝑉𝐸𝐵
1. Input Resistance: 𝑟𝑖 = 𝑉𝐶𝐵 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐸
∆𝑉𝐸𝐵
𝑕𝑖𝑏 = 𝑉 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐸 𝐶𝐵
Input resistance in Common Base is in the order of few ohms.
∆𝑉𝐶𝐵
2. Output Resistance: 𝑟𝑜 = 𝐼𝐸 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐶
∆𝐼𝐶
𝑕𝑜𝑏 = 𝐼 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝑉𝐶𝐵 𝐸
 Output resistance in Common Base is in the order of hundred of kilo ohms.
∆𝐼𝐶
3. Current Gain: 𝐴𝐼 = 𝑉𝐶𝐵 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐸
∆𝐼𝐶
𝛼 = 𝑕𝑓𝑏 = 𝑉 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐸 𝐶𝐵
Current gain is always less than unity.
∆𝑉𝐶𝐵
4. Voltage Gain: 𝐴𝑉 = 𝐼𝐸 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝑉𝐸𝐵
∆𝑉𝐸𝐵
𝑕𝑟𝑏 = 𝐼 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝑉𝐶𝐵 𝐸
Voltage gain in common base configuration is high.

Common Emitter (CE) Configuration:

In common emitter configuration, emitter is common to input and output. The circuit
diagram for CE configuration is shown below.

Figure: Circuit diagram for CE configuration

The input to the CE is applied to the base-emitter circuit and the output is taken from
the collector-emitter circuit, making the emitter the element "common" to both input and
output. The CE is set apart from the other configurations, because it is the only configuration
that provides a phase reversal between input and output signals. This configuration is mostly
used one among all the three configurations. It has medium input and output impedance
values.

The input voltage and input current are VBE and IB. Output voltage and output current
are VCE and IC. Then the equations used for plotting input and output characteristics are

VBE = f(IB, VCE) ---------------(1)

IC = f(IB, VCE) ---------------(2)

Input Characteristics:

Using equation1, the input characteristics of common emitter configuration are

obtained between input current IB and input voltage VBE with constant output voltage VCE.
Keep the output voltage VCE constant and vary the input voltage VBE for different points, now
record the values of input current at each point. Now using these values we need to draw a
graph between the values of IB and VBE at constant VCE.

Figure: Input characteristics of CE configuration

Output Characteristics

Using equation2, the output characteristics of common emitter configuration are

obtained between the output current IC and output voltage VCE with constant input current IB.
Keep the base current IB constant and vary the value of output voltage VCE for different
points, now note down the value of collector IC for each point. Plot the graph between the
parameters IC and VCE in order to get the output characteristics of common emitter
configuration.

Figure: Output characteristics of CE configuration

Transistor parameters:
∆𝑉𝐵𝐸
1. Input Resistance: 𝑟𝑖 = 𝑉𝐶𝐸 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐵
∆𝑉𝐵𝐸
𝑕𝑖𝑒 = 𝑉 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐵 𝐶𝐸
Input resistance in Common Emitter is moderate.
∆𝑉𝐶𝐸
2. Output Resistance: 𝑟𝑜 = 𝐼𝐵 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐶
∆𝐼𝐶
𝑕𝑜𝑒 = 𝐼 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝑉𝐶𝐸 𝐵
Output resistance in Common Emitter is moderate.
∆𝐼𝐶
3. Current Gain: 𝐴𝐼 = 𝑉𝐶𝐸 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐵
∆𝐼𝐶
𝛽 = 𝑕𝑓𝑒 = 𝑉 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐵 𝐶𝐸
Current gain in Common Emitter configuration is high.
∆𝑉𝐶𝐸
4. Voltage Gain: 𝐴𝑉 = 𝐼𝐵 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝑉𝐵𝐸
∆𝑉𝐵𝐸
𝑕𝑟𝑒 = 𝐼 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝑉𝐶𝐸 𝐵
Voltage gain in common Emitter configuration is high.

Common Collector (CC) Configuration:

In common collector configuration, collector is common to input and output. The
circuit diagram for CC configuration is shown below.

This configuration is also known as emitter follower configuration because the emitter
voltage follows the base voltage. This configuration is mostly used as a buffer. These
configurations are widely used in impedance matching applications because of their high
input impedance.

The input voltage and input current are VBC and IB. Output voltage and output current
are VEC and IE. Then the equations used for plotting input and output characteristics are
 VBC = f(IB, VEC) ---------------(1)

IE = f(IB, VEC) ---------------(2)

Input Characteristics:

The input characteristics of a common collector configuration are quite different from
the common base and common emitter configurations because the input voltage VBC is
largely determined by VEC level. The input characteristics of a common-collector
configuration are obtained between inputs current IB and the input voltage VCB at constant
output voltage VEC. Keep the output voltage VEC constant at different levels and vary the
input voltage VBC for different points and record the IB values for each point. Now using
these values we need to draw a graph between the parameters of VBC and IB at constant VEC.

Figure: Input characteristics of CC Configuration

Output Characteristics:

The operation of the common collector circuit is same as that of common emitter
circuit. The output characteristics of a common collector circuit are obtained between the
output voltage VEC and output current IE at constant input current IB. In the operation of
common collector circuit if the base current is zero then the emitter current also becomes
zero. As a result no current flows through the transistor. If the base current increases then the
transistor operates in active region and finally reaches to saturation region. To plot the graph
first we keep the IB at constant value and we will vary the VEC value for various points, now
we need to record the value of IE for each point. Repeat the same process for different
IB values. Now using these values we need to plot the graph between the parameters of IE and
VCE at constant values of IB. The below figure show the output characteristics of common
collector.

Figure: Output characteristics of CC Configuration

Transistor parameters:
∆𝑉𝐵𝐶
1. Input Resistance: 𝑟𝑖 = 𝑉𝐸𝐶 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐵
∆𝑉𝐵𝐶
𝑕𝑖𝑐 = 𝑉 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐵 𝐸𝐶
Input resistance in Common collector is High.
∆𝑉𝐸𝐶
2. Output Resistance: 𝑟𝑜 = 𝐼𝐵 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐸
∆𝐼𝐸
𝑕𝑜𝑐 = 𝐼 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝑉𝐸𝐶 𝐵
Output resistance in Common collector is low.
∆𝐼𝐸
3. Current Gain: 𝐴𝐼 = 𝑉𝐸𝐶 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐵
∆𝐼𝐸
𝛾 = 𝑕𝑓𝑐 = 𝑉 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝐼𝐵 𝐸𝐶
Current gain in Common collector configuration is high.
∆𝑉𝐸𝐶
4. Voltage Gain: 𝐴𝑉 = 𝐼𝐵 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝑉𝐵𝐶
∆𝑉𝐵𝐶
𝑕𝑟𝑐 = 𝐼 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝑉𝐸𝐶 𝐵
Voltage gain in common collector configuration is less than unity.

Amplification Factors:
∆𝐼
In common Base configuration, 𝛼 = ∆𝐼𝐶
𝐸

∆𝐼
In common Emitter configuration, 𝛽 = ∆𝐼 𝐶
𝐵

∆𝐼
In common Collector configuration, 𝛾 = ∆𝐼𝐸
𝐵

Relationship between α, β, and γ:

(i) Between α, β: We know that ∆𝐼𝐸 = ∆𝐼𝐵 + ∆𝐼𝐶

∆𝐼𝐶 ∆𝐼𝐶 ∆𝐼𝐶 ∆𝐼𝐵 (∆𝐼𝐶 ∆𝐼𝐵 ) 𝛽

𝛼= = = = =
∆𝐼𝐸 ∆𝐼𝐵 + ∆𝐼𝐶 ∆𝐼𝐵 + ∆𝐼𝐶 ∆𝐼𝐵 1 + (∆𝐼𝐶 ∆𝐼𝐵 ) 1 + 𝛽
𝛼
𝛽=
1−𝛼
(ii) Between β and γ:

∆𝐼𝐶 ∆𝐼𝐸 − ∆𝐼𝐵 ∆𝐼𝐸

β= = = −1=γ−1
∆𝐼𝐵 ∆𝐼𝐵 ∆𝐼𝐵

γ= 1+β
(iii) Between γ and α:

∆𝐼𝐶 ∆𝐼𝐸 − ∆𝐼𝐵 ∆𝐼𝐵 1 𝛾−1

𝛼= = =1− = 1− =
∆𝐼𝐸 ∆𝐼𝐸 ∆𝐼𝐸 𝛾 𝛾

1
𝛾=
1−𝛼

Comparison of transistor configurations:

Parameter CB CE CC
Input Resistance Low Moderate High
Output Resistance High Moderate Low
Current Gain Less than unity High High
Voltage Gain High High Less than unity
Amplification factor ∆𝐼𝐶 ∆𝐼𝐶 ∆𝐼𝐸
𝛼= β= 𝛾=
∆𝐼𝐸 ∆𝐼𝐵 ∆𝐼𝐵
Application Multi stage amplifier Audio signal amplifier Impedance matching

Transistor as an Amplifier:
Transistor acts as an amplifier in active region. Let us see that how the transistor
configuration acts as an amplifier.

Let us consider the voltage gain

𝑉𝑜
𝐴𝑉 =
𝑉𝑖

𝑏𝑢𝑡 𝑉𝑜 = 𝐼𝐶 𝑅𝐶 ----------- (1)

𝐼𝐶
𝛼=
𝐼𝐸
 𝐼𝐶 = 𝛼 𝐼𝐸 ------------ (2)

Substituting eq.2 in 1, we get,

𝑉𝑜 = 𝛼 𝐼𝐸 𝑅𝐶

From the circuit, input voltage is 𝑉𝑖 = 𝐼𝐸 𝑟𝑒

Where 𝑟𝑒 𝑖𝑠 𝑡𝑕𝑒 𝑖𝑛𝑡𝑒𝑟𝑛𝑎𝑙 𝑒𝑚𝑖𝑡𝑡𝑒𝑟 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒

𝑉𝑜 𝛼 𝐼𝐸 𝑅𝐶 𝛼𝑅𝐶
𝐴𝑉 = = =
𝑉𝑖 𝐼𝐸 𝑟𝑒 𝑟𝑒

Let us consider, α = 0.98, 𝑟𝑒 = 40Ω 𝑎𝑛𝑑 𝑅𝐶 = 4𝐾Ω

𝛼𝑅𝐶 0.98 ∗ 4000

𝐴𝑉 = = = 98
𝑟𝑒 40

Input signal applied to the amplifier is 𝑉𝑖 = 10𝑚𝑉

𝑉𝑜
𝐴𝑉 =
𝑉𝑖

𝑉𝑜 = 𝐴𝑉 𝑉𝑖 = 98 ∗ 10𝑚𝑉 = 0.98 𝑉𝑜𝑙𝑡𝑠

Transistor Junction voltages:

Material VBE(Cutoff) VBE(Cutin) VBE(Act) VBE(Sat) VCE(Sat)
Si 0V 0.5 V 0.6 V 0.7 V 0.3 V
Ge -0.1 V 0.1 V 0.2 V 0.3 V 0.1 V

Field Effect Transistor (FET):

Advantages of FET over BJT:

1. In FET, current conduction is because of majority charge carriers. Hence, FET is

called as uni-polar device.
2. FET is a voltage controlled device, where as BJT is a current controlled device.
3. FET has high input resistance compared with BJT.
4. FET provides better thermal stability.
5. It produces low noise during its operation.
Classification of FET:

FET‟s are classified into two types, they are

1. JFET (Junction Field Effect Transistor)

2. MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or IGFET (Insulated
Gate Filed Effect Transistor).

JFETs consist of three terminals namely, Source (S), Gate (G) and Drain (D). These
devices are also called voltage controlled devices as the voltage applied at the gate terminal
determines the amount of current flowing in-between the drain and the source terminals.

n-Channel JFET:

Figure: Semiconductor and symbolic representation of n channel JFET

The basic structure and symbol for n channel JFET is shown in the above figure. In n
channel JFET, current conduction is because of electrons. Charge carriers flows from source
to drain. The flow of charge carriers from source to drain is controlled by gate terminal. Gate
is normally reverse biased. The polarity of source and drain terminals depends on the channel
type. Here, charge carriers moving from source to drain are controlled by varying the gate
voltage, and hence it is called as voltage current controlled device.

Biasing and working of n channel JFET:

Figure: VGS is made equal to „0‟

Figure: VGS is slightly increased

 Figure: VGS is increased more

The internal diagram for N-channel JFET transistor is shown above. This is a transistor
with N-type of channel and with P-type materials of the region. If the gate is diffused into the
N-type channel, then a reverse biased PN-junction is formed which results a depletion region
around the gate terminal when no external supply is applied to the transistor. Generally the
JFETs are called as depletion mode devices.

Gate is normally reverse biased. The biasing between source to drain is arranged in such a
way that charge carriers moves from source to drain. Because of the biasing arrangement
depletion width is more between drain and source, because drain to gate is more reverse
biased compared to source to gate. Initially VGS is made equal to zero; hence maximum
channel width is available between source and drain. When VDS is increased, number of
charge carriers flows from source to drain increases and hence maximum drain current (ID)
will flow. If we will increase more negative voltage at the gate terminal then it reduces the
channel width until no current flows through the channel. Now at this condition the JFET is
said to be “pinched-off”. The applied voltage at which the channel of FET closes is called as
“pinched-off voltage (VP)”.

If the drain to source voltage (VDS) is high enough, then the channel of the JFET breaks
down and in this region uncontrolled maximum current passes through the device.
 Figure: V-I Characteristics of FET

The JFET has different characteristics at different stages of operation depending on the input
voltages and the characteristics of JFET at different regions are explained below. Mainly the
JFET operates in ohmic, saturation, cut-off and break-down regions.

Ohmic Region: If VGS = 0 then the depletion region of the channel is very small and in this
region the JFET acts as a voltage controlled resistor.

Pinched-off Region: This is also called as cut-off region. The JFET enters into this region
when the gate voltage is large negative, then the channel closes [Link] current flows through
the channel.

Saturation or Active Region: In this region the channel acts as a good conductor which is
controlled by the gate voltage (VGS).

Breakdown Region: If the drain to source voltage (VDS) is high enough, then the channel of
the JFET breaks down and in this region uncontrolled maximum current passes through the
device.
The transfer characteristics of n channel JFET is shown is shown below.
 Transfer characteristics shows that, at zero gate voltage, maximum drain current will
flow and is represented with IDSS and if the gate voltage is increased, drain current decreases
and becomes zero at a particular voltage and this voltage is represented with VGS (OFF).

The drain current ID flowing through the channel is zero when applied voltage V GS is
equal to pinch-off voltage VP. In normal operation of JFET the applied gate voltage V GS is in
between 0 and VP, In this case the drain current ID flowing through the channel can be
calculated as follows.

ID = IDSS (1-(VGS/VP))2

Where, ID = Drain current

IDSS = maximum saturation current
VGS = gate to source voltage
VP = pinched-off voltage

The working of P channel JFET is similar to n channel except that the gate voltage is
positive.

JFET parameters:
1. Drain resistance (rd):
∆𝑉𝐷𝑆
𝑟𝑑 = / 𝑉𝐺𝑆 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 𝑜𝑕𝑚𝑠
∆𝐼𝐷
2. Trans conductance (or) Mutual Conductance (gm):
∆𝐼𝐷
𝑔𝑚 = / 𝑉𝐷𝑆 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 𝑚𝑕𝑜𝑠
∆𝑉𝐺𝑆
3. Amplification factor (µ):
∆𝑉𝐷𝑆
µ= / 𝐼𝐷 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝑉𝐺𝑆

µ = 𝑔𝑚 𝑟𝑑

Applications of JFET:
1. It is used as voltage variable resistor.
2. It is used in RF amplifiers.
3. JFET is used as an oscillator.
4. JFETs are popularly used in digital circuits like computers and memory elements
because of small size.
Metal Oxide Semiconductor FET or Insulated Gate FET (MOSFET or IGFET):

The IGFET or MOSFET is a voltage controlled field effect transistor that differs
from a JFET in that it has a “Metal Oxide” Gate electrode which is electrically insulated from
the main semiconductor n-channel or p-channel by a very thin layer of insulating material
usually silicon dioxide, commonly known as glass.
MOSFET‟s are classified into two types, they are
(1) Enhancement MOSFET
(2) Depletion MOSFET
In enhancement MOSFET channel does not exist from source to drain and is created.
Whereas in depletion MOSFET, available channel is depleted. Again these MOSFET‟s are
classified based on n channel or p channel.
(a) n channel enhancement MOSFET
(b) p channel enhancement MOSFET
(c) n channel depletion MOSFET
(d) p channel depletion MOSFET

n channel enhancement MOSFET:

In this MOSFET, channel doesn‟t exist between source and drain. This results in the
device being normally “OFF” (non-conducting) when the gate bias voltage, VGS is equal to
zero. The circuit diagram and its symbol are shown below. Broken channel line to signify a
normally open non-conducting channel between source and drain.

Figure: Basic diagram for n channel enhancement MOSFET and its symbol
 Figure: Working of n channel MOSFET
For the n-channel enhancement MOS transistor a drain current will only flow when a
gate voltage (VGS) is applied. The application of a positive (+ve) gate voltage to a n-type
MOSFET attracts more electrons towards the oxide layer around the gate thereby increasing
or enhancing (hence its name) the thickness of the channel allowing more charge carriers to
flow from source to drain and hence drain current to flow. Because of this operation, the
transistor is called an enhancement mode device as the application of a gate voltage enhances
the channel.
Increasing this positive gate voltage will cause the channel resistance to decrease
further causing an increase in the drain current, ID through the channel. In other words, for an
n-channel enhancement mode MOSFET: +VGS turns the transistor “ON”, while a zero
or negative VGS turns the transistor “OFF”. Then, the enhancement-mode MOSFET is
equivalent to a “normally-open” switch.
V-I characteristics of n channel enhancement MOSFET is shown in the following
figure.

Figure: V-I characteristics of n channel enhancement MOSFET

n channel Depletion MOSFET:
In this MOSFET, n channel exists between source and drain. This results in the device
being normally “ON” (conducting), VGS is equal to zero. The circuit diagram and its symbol
are shown below. Solid channel line to signify a normally closed conducting channel between
source and drain.

Figure: Basic diagram for n channel depletion MOSFET and its symbol

Figure: Working of n channel depletion MOSFET

For the n-channel depletion MOS transistor a drain current is maximum when gate
voltage (VGS) is zero. Under this condition the available channel width is maximum between
source and drain. The application of a positive (-ve) gate voltage to a n-type MOSFET
creates a positive charge in the n channel as a result, its width decreases. If the gate voltage is
further increased, correspondingly channel width decreases, which reduce the carrier flow
from source to drain causing drain current to decrease. Because of this operation, the
transistor is called a depletion mode device as the application of a gate voltage depletes the
channel.
 Increasing this negative gate voltage will cause the channel resistance to increase
further causing an decrease in the drain current, ID through the channel. In other words, for an
n-channel depletion mode MOSFET: -VGS turns the transistor “OFF”. Then, the depletion-
mode MOSFET is equivalent to a “normally-closed” switch.
V-I characteristics of n channel depletion MOSFET is shown in the following figure.

Figure: V-I characteristics of n channel depletion MOSFET

Figure: Combination of depletions and enhancement mode of MOSFET

The transfer characteristics of MOSFET is shown below
 Figure: transfer characteristics of MOSFET

Comparison between JFET and MOSFET:

1. JFET is operated only in depletion mode, where as MOSFET can be operated in
depletion as well as in enhancement mode.
2. Fabrication of MOSFETs is easier compared to JFETs.
3. JFET has high input impedance compared with MOSFET.
4. In JFET, electric field is created across reverse biased PN junction, where as in
MOSFET electric field is created between gate and semiconductor.
5. If MOSFET is not handled properly, there is a possibility for damage when compared
with JFET.

Ebers – Moll model of a transistor:

The general expression for collector current is given by
𝐼𝐶 = −𝛼𝑁 𝐼𝐸 − 𝐼𝐶𝑂 𝑒 𝑉𝐶 𝑉𝑇
−1
𝐼𝐸 = −𝛼𝐼 𝐼𝐶 − 𝐼𝐸𝑂 𝑒 𝑉𝐸 𝑉𝑇
−1
 𝐼𝐶 = −𝛼𝑁 𝐼𝐸 + 𝐼
𝐼𝐶 = −𝛼𝑁 𝐼𝐸 + 𝐼𝑜 𝑒 𝑉 𝑉𝑇
−1
𝐼𝐶 = −𝛼𝑁 𝐼𝐸 − 𝐼𝑜 𝑒 𝑉𝐶 𝑉𝑇
−1

Photo Transistor:

Figure: Symbol for photo transistor

The base of the photo transistor would only be used to bias the transistor so that
additional collector current was flowing and this would mask any current flowing as a result
of the photo-action. For operation the bias conditions are quite simple. The collector of an n-
p-n transistor is made positive with respect to the emitter or negative for a p-n-p transistor.
The light enters the base region of the phototransistor where it causes hole electron
pairs to be generated. This mainly occurs in the reverse biased base-collector junction. The
hole-electron pairs move under the influence of the electric field and provide the base current,
causing electrons to be injected into the emitter. The V-I characteristics of phototransistor is
shown below.

Figure: V-I Characteristics of Photo transistor