UNIT-V SEQUENTIAL LOGIC IC'S AND MEMORIES

Familiarity with commonly available 74XX & CMOS 40XX

series ICs-All Types of Flip-flops, Conversion of Flip flops,
Synchronous Counters , Decade Counters ,Shift Registers ,
MEMORIES - ROM Architecture, Types of ROMS &
Applications RAM Architecture, Static & Dynamic RAMs.
 Flip Flops

Latches:

Flip Flop:
S-R Flip Flop:
D-Flip Flop:
PROCEDURE FOR CONVERSION

1. Draw the block diagram of the destination flip flop from the given
problem.

2. Write truth table for the destination flip-flop.

3. Write excitation table for the source flip- flop.

4. Draw k-map for destination flip-flop.

5. Draw the block diagram.

SR to JK FF:

Truth Table/Characteristic table:

Excitation table:-

Qp Qp+1 S R
Input input

0 0 0 ×

0 1 1 0

1 0 0 1

1 1 × 0
TT:

Excitation table:
SR(Source) to T(Destination)FF:

SR(Source) to T(Destination)
Conversion Table
K- MAP
SIMPLIFICATION
Prese
Input Next state Flip flop Inputs
nt
state

T Qn Qn+1 S R

0 0 0 0 X

0 1 1 X 0

1 0 1 1 0

1 1 0 0 1

Logic Diagram (SR to T)

Logic Diagram(D to T)
 T (Source) to D(Destination) Flip-
flop Table
Conversion

Prese Flip flop K- MAP SIMPLIFICATION

Input Next state
nt Inputs
state

D Qn Qn+1 T

0 0 0 0

0 1 0 1

1 0 1 1

1 1 1 0

Logic Diagram:
Characteristic table and excitation table of FFs:
Synchronous Counters:
 Synchronous Counters can be made from Toggle or D-type flip-flops.

 Synchronous counters are easier to design than asynchronous counters.

 They are called synchronous counters because the clock input of the flip-flops
are all clocked together at the same time with the same clock signal.

 Due to this common clock pulse all output states switch or change
[Link] all clock inputs wired together there is no inherent
propagation delay.

 Synchronous counters are sometimes called parallel counters as the clock is fed in
parallel to all flip-flops.

 The inherent memory circuit keeps track of the counters present state.

 The count sequence is controlled using logic gates.

 Overall faster operation may be achieved compared to Asynchronous counters.

2 bit synchronouscounter:
Sequence of States:
Binary 4-bit Synchronous Up Counter:

It can be seen above, that the external clock pulses (pulses to be counted) are fed
directly to each of the J-K flip-flops in the counter chain and that both
the J and K inputs are all tied together in toggle mode, but only in the first flip-
flop, flip-flop FFA (LSB) are they connected HIGH, logic “1” allowing the flip-flop to
toggle on every clock pulse. Then the synchronous counter follows a
predetermined sequence of states in response to the common clock signal,
advancing one state for each pulse.

The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-
flop FFA, but the J and K inputs of flip-flops FFC and FFD are driven from
separate AND gates which are also supplied with signals from the input and
output of the previous stage. These additional AND gates generate the required
logic for the JK inputs of the next stage.

If we enable each JK flip-flop to toggle based on whether or not all preceding flip-
flop outputs (Q) are “HIGH” we can obtain the same counting sequence as with
the asynchronous circuit but without the ripple effect, since each flip-flop in this
circuit will be clocked at exactly the same time.
Then as there is no inherent propagation delay in synchronous counters, because
all the counter stages are triggered in parallel at the same time, the maximum
operating frequency of this type of frequency counter is much higher than that for
a similar asynchronous counter circuit.

4-bit Synchronous Counter Waveform Timing Diagram

Binary 4-bit Synchronous Down Counter

As synchronous counters are formed by connecting flip-flops together and any number of
flip-flops can be connected or “cascaded” together to form a “divide-by-n” binary counter,
the modulo’s or “MOD” number still applies as it does for asynchronous counters so a
Decade counter or BCD counter with counts from 0 to 2n-1 can be built along with truncated
sequences. All we need to increase the MOD count of an up or down synchronous counter is
an additional flip-flop and AND gate across it.
UP/DOWN COUNTER USING IC 74HC190:
Applications of Counters:
Some of the applications of counters in a sequential circuits are as follows:

 To count the number of occurances

 Generating Timing sequences

 Count up or down

 Increment or decrement count

 Sequence events

 Divide frequency

 Address memory

 As temporary memory

Flip Flop ICs:

Pin Diagram of IC MC74HC73A-JK FF 74HC112-DUAL JK FF:
IC7474-JK FF:

SR FF IC-74HC00N 7474-D FF
 DECADE COUNTERS
(BCD COUNTER OR MOD-10/ASYNCHRONOUS COUNTER)

A decade counter is one that counts in decimal digits, rather than binary. It counts from 0 to
9 and then resets to zero. The counter output can be set to zero by pulsing the reset line
low. The count then increments on each clock pulse until it reaches 1001 (decimal 9).

Decade counter”. A BCD counter can count 0000, 0001, 0010, 1000, 1001, 1010, 1011, 1110,
1111, 0000, and 0001 and so on.

Decade Counter Operation:

When the Decade counter is at REST, the count is equal to 0000. This is first stage of the
counter cycle. When we connect a clock signal input to the counter circuit, then the circuit
will count the binary sequence. The first clock pulse can make the circuit to count up to 9
(1001). The next clock pulse advances to count 10 (1010).

Then the ports A and C will be high. As we know that for high inputs, the NAND gate output
will be low. The NAND gate output is connected to clear input, so it resets all the flip flop
stages in decade counter. This means the pulse after count 9 will again start the count from
count 0.

State Diagram of Decade Counter

The state diagram of Decade counter is given below.

TRUTH TABLE:
The above table describes the counting operation of Decade counter. It represents the
count of circuit for decimal count of input pulses. The NAND gate output is zero when the
count reaches 10 (1010).
The count is decoded by the inputs of NAND gate A and C. After count 10, the logic gate
NAND will trigger its output from 1 to 0, and it resets all flip flops.

LOGIC DIAGRAM:

Timing Diagram:
IC 7490 is a 4-bit, ripple-type decade counter. It consists of four master/slave flip-flops,
which are internally connected to form a divide-by-two section and a divide-by-five section.

Each section has a separate clock input to change the output states of the counter on a
high-to-low clock transition.
It is a simple counter which can count from 0 – 9. As it is a 4 bit binary decade
counter, it has 4 output ports QA, QB, QC and QD. When the count reaches 10, the
binary output is reset to 0 (0000), every time and another pulse starts at pin number
9. The Mod of the IC 7490 is set by changing the RESET pins R1, R2, R3, R4.
If any one of R1 & R2 is at high or R3 & R4 are at ground, the counter will reset all
the outputs QA, QB, QC and QD to 0. If the pins R3 & R4 are high, then the count on
QA, QB, QC and QD is 1001.
As we studied earlier, we can increase the counting capability of a Decade number
by connecting more ICs n series; we can count 99 with two 7490 ICs connected in
series. This 7490 IC has inbuilt Divide by 2 and Divide by 5 counters in it.
It can also be used as divide by 10 counter by connecting by connecting clock input
2 and QA and connecting all rest pins to ground and giving pulse input to 1. It is used
as divide by 6 counter by supplying pulse at input 1 and grounding reset pins R3 and
R4 and connecting QA with input 2. 7490 IC can work like bi –quinary counter,
which is used to store decimal digits in the form of 4 bit binary numbers.
4017 CMOS decade counter IC description

Applications of BCD Counter or Decade Counters:

The key advantages and benefits if BCD counters are

 Clock generation

 Clock division

 Integrated oscillator

 Low power cmos

 TTL compatible inputs

 In frequency counting circuits

 SHIFT REGISTERS
Shift Registers are devices that store and move data bits in serial (to the left or the right),
Each stage (flip-flop) in a shift register represents one bit of storage, and the shifting
capability of a register permits the movement of data from stage to stage within the
register, or into or out of the register upon application of clock pulses.

 A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each
data bit.

 The output from each flip-Flop is connected to the D input of the flip-flop at its right.

 Shift registers hold the data in their memory which is moved or “shifted” to their
required positions on each clock pulse.

 Each clock pulse shifts the contents of the register one bit position to either the left or
the right.

 The data bits can be loaded one bit at a time in a series input (SI) configuration or be
loaded simultaneously in a parallel configuration (PI).

 Data may be removed from the register one bit at a time for a series output (SO) or
removed all at the same time from a parallel output (PO).

 One application of shift registers is in the conversion of data between serial and
parallel, or parallel to serial.

 Shift registers are identified individually as SIPO, SISO, PISO, PIPO, or as a Universal
Shift Register with all the functions combined within a single device.
Basic data movement in shift registers (four bits are used for illustration).

Types of Shift Registers:

 SISO: Serial In, Serial Out

 SIPO: Serial In, Parallel Out
 PISO: Parallel In, Serial Out
 PIPO: Parallel In, Parallel Out
Serial In/Serial Out Shift Registers:
The serial in/serial out shift register accepts data serially – that is, one bit
at a time on a single line. It produces the stored information on its output
also in serial form.

A basic four-bit shift register can be constructed using four D flip-flops,

as shown in Figure

The operation of the circuit is as follows.

 The register is first cleared, forcing all four outputs to zero.

 The input data is then applied sequentially to the D input of the
 first flip-flop on the left (FF0).
 During each clock pulse, one bit is transmitted from left to right.
 Assume a data word to be 1001.
 The least significant bit of the data has to be shifted through the
register from FF0 to FF3.

Timing Pulse Shift register A Shift register B Serial output of B

Initial value 1 0 1 1 0 0 1 0 0
After T1 1 1 0 1 1 0 0 1 1
After T2 1 1 1 0 1 1 0 0 0
After T3 0 1 1 1 0 1 1 0 0
After T4 1 0 1 1 1 0 1 1 1
Serial In/Parallel Out Shift Registers

Data bits are entered serially in the same manner as discussed in the last section. The
difference is the way in which the data bits are taken out of the register. Once the data are
stored, each bit appears on its respective output line, and all bits are available
simultaneously. A construction of a four-bit serial in - parallel out register is shown below.

In the table below, we can see how the four-bit binary number 1001 is shifted
to the Q outputs of the register.
Parallel In/Serial Out Shift Registers

A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-flops
and AND gates for entering data (ie writing) to the register.
The parallel-in/ serial-out shift register stores data, shifts it on a clock by clock basis, and
delays it by the number of stages times the clock period.
In addition, parallel-in/ serial-out really means that we can load data in parallel into all
stages before any shifting ever begins. This is a way to convert data from a parallel format to
a serial format. By parallel format we mean that the data bits are present simultaneously on
individual wires, one for each data bit as shown below. By serial format we mean that the
data bits are presented sequentially in time on a single wire or circuit as in the case of the
“data out” on the block diagram below.
Now from above 4 bit parallel in serial out shift register we can see, A, B, C, and D are the
four parallel data input lines and SHIFT / LOAD (SH / LD) is a control input that allows the
four bits of data at A, B, C, and D inputs to enter into the register in parallel or shift the data
in serial. When SHIFT / LOAD is HIGH, AND gates G1, G3, and G5 are enabled, allowing the
data bits to shift right from one stage to the next. When SHIFT / LOAD is LOW, AND gates
G2, G4, and G6 are enabled, allowing the data bits at the parallel inputs. When a clock pulse
is applied, the flip-flops with D = 1 will be set and the flip-flops with D = 0 will be reset,
thereby storing all the four bits simultaneously. The OR gates allow either the normal
shifting operation or the parallel data-entry operation, depending on which of the AND
gates are enabled by the level on the SHIFT / LOAD input.

 74HC595 is a shift register which works on PArallel In and Serial OUT Protocol.
 It has 8 input pins where you can connect different sensors etc. and then it has 1
Serial Output Pin, which should be connected to the Microcontroller.
 With the help of Clock Pin, we can receive all these parallel 8 inputs serially from
a single output into the microcontroller.
 We can also connect multiple 74HC165 in parallel to increase the input pins.
 Let's say if I have connected 3 shift registers in parallel then the input pins will
increase by 8 x 3 = 24.
 So, we can control 24 digital sensors by a single Arduino Pin.
 Let's have a look at the 74HC595 Pinout:
Parallel In - Parallel Out Shift Registers

For parallel in - parallel out shift registers, all data bits appear on the parallel outputs
immediately following the simultaneous entry of the data bits. The following circuit is a four-
bit parallel in - parallel out shift register constructed by D flip-flops.

The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is
clocked, all the data at the D inputs appear at the corresponding Q outputs simultaneously.
Bidirectional Shift Registers:
Each right shift operation has the effect of successively dividing the binary number by two. If
the operation is reversed (left shift), this has the effect of multiplying the number by two.
With suitable gating arrangement a serial shift register can perform both operations. A
bidirectional, or reversible, shift register is one in which the data can be shift either left or
right. A four-bit bidirectional shift register using D flip-flops is shown [Link] a set of
NAND gates are configured as OR gates to select data inputs from the right or left adjacent
bistables, as selected by the LEFT/RIGHT control line.
Shift Registers are an important Flip-Flopconfiguration with a wide range of applications,
including:

 Computer and Data Communications

 Serial and Parallel Communications
 Multi-bit number storage
 Sequencing
 Basic arithmetic such as scaling (a serial shift to the left
or right will change the value of a binary number a power
of 2)
 Logical operations
 MEMORY
Memory is the portion of a system for storing binary data in large [Link]
memories consist of arrays of storage elements that are generally either latches or
[Link] of Binary data: Bits, Bytes, Nibbles, and Words.

Terms:
• Memory Cell – A device or an electrical circuit used to store a single bit (0 or 1)
• Memory Word – A group of bits in a memory (word sizes typically range from 4 to
64).
• Byte – a group of 8 bits
• Address – a number that identifies the location of a word in memory
• Read Operation – the operation whereby a word stored in a specified memory
location is sensed and then transferred to another device.
 • Write Operation – the operation whereby a new word is placed or stored into a
particular memory location.
• Volatile Memory – any type of memory that requires the application of electrical
power in order to store information. If the electrical power is removed, all
information stored in the memory will be lost.

ROM Definition: Read Only Memory (ROM) is an integrated circuit which is pre-
programmed with specific functional data at manufacturing time. It is an example of
nonvolatile memory. It is a class of storage medium used in computers and other electronic
devices. Read Only Memory (ROM), also known as firmware, The instructions for starting
the computer are housed on Read only memory chip.

Why Need ROM?

ROM chips are used not only in computers, but in most other electronic items as well.
Because data is fully incorporated at the ROM chip's manufacture, data stored can neither
be erased nor replaced. This means permanent and secure data storage. However, if a
mistake is made in manufacture, a ROM chip becomes unusable. The most expensive stage
of ROM manufacture, therefore, is creating the template.

If a template is readily available, duplicating the ROM chip is very easy and affordable. A
ROM chip is also non volatile so data stored in it is not lost when power is turned off. ROM is
a semiconductor memory that is capable of operating at electronics speed.

Difference between RAM and ROM

ROM can hold data permanently and RAM cannot.

ROM chip is a non-volatile and RAM chip is volatile in nature.
Block Diagram of Memory:

Block diagram of a memory showing address bus, address decoder, bidirectional data bus,
and read/write inputs, Every memory system requires I/O lines to provide the following
functions:

Select memory address being accessed for Read or Write operation,Select either a Read or
Write operation Supply input data to be stored during a Write,Hold output data from
memory during a Read Enable or disable memory so that it will or will not respond to
read/write commands
System bus functions:
Address bus – unidirectional, carries address outputs from CPU to memory
Data bus – bi-directional, carries data between CPU and memory ICs
Control bus – unidirectional, carries controls signals (such as R/W) from CPU to memory
16*8 ROM:

16 8-bit words can be stored.

(a) Typical ROM block symbol: (b) table showing binary data at each address location;
(c) the same table in hex.
Architecture of a 16  8 ROM

Three basic parts

 Register array – stores data programmed into the ROM
 Address decoders – determines which register will be enabled by row and column
 Output buffers - pass data to the external data outputs
 CS – chip select, tri-state output buffers
 2D memory example – 4 words (8 bits each) on a row (32 bit lines) and 4 word lines

32 X 8 ROM consists of 32 words and of 8 bits each. This means there are 8 output lines
and that there are 32 distinct words stored in the unit, each of which may be applied to
the output lines.
There are 5 input lines in a 32 X 8 ROM because 25 = 32, and with 5 variables, we can
specify 32 addresses or minterms.
If the input address is 00000, word number 0 is selected and appears on the output
lines. If the input address is 11111, word number 31 is selected and appears on the
output [Link] are 30 other addresses that can select the other 30 words.
 Internal logic of a 32× 8 ROM
The five inputs are decoded into 32 distinct outputs by means of a 5 32 decoder. Each
output of the decoder represents a memory address. The 32 outputs of the decoder are
connected to each of the eight OR gates. Each OR gate must be considered as having 32
inputs. Each output of the decoder is connected to one of the inputs of each OR gate. Since
each OR gate has 32 input connections and there are 8 OR gates, the ROM contains 32 x 8 =
256 internal connections.
A programmable connection between two lines is logically equivalent to a switch that can
be altered to be either closed (meaning that the two lines are connected) or open (meaning
that the two lines are disconnected). The programmable intersection between two lines is
sometimes called a cross point.
For example, programming the ROM according to the truth table given by table. Every 0
listed in the truth table specifies the absence of a connection and every 1 listed specifies a
path that is obtained by a connection.

256  4 ROM:
ROM FAMILY:

Types of Read Only Memory (ROM)

ROM is differentiated on the basis of methods used to write data on ROM chips and the
number of times they can be written. It can be classified into following types : –
1. Mask Read-Only Memory (MROM)
2. Programmable Read-Only Memory (PROM)
3. Erasable Programmable Read-Only Memory (EPROM)
4. Electrically Erasable Programmable Read-Only Memory (EEPROM)
5. Flash Read-Only Memory (Flash ROM)
Mask Read Only Memory (MROM):
The very first ROMs were hard-wired devices that contained a pre-programmed set of data
or instructions. These kind of ROMs are known as masked ROMs. It is inexpensive ROM.
Applications of Mask Read Only Memory (MROM)
The Mask Read-Only Memory (MROM) are used for:
 Network Operating Systems.
 Server Operating Systems.
 Storing fonts for laser printers.
 Storing sound data in electronic musical instruments.
Advantage of Mask Read Only Memory (MROM)
The main advantage of Mask Read-Only Memory (MROM) is its low production cost. The
cost of IC depends on its size, per bit. Mask ROM is more compact. It is significantly cheaper
than any other kind of secondary memory when large quantities of same ROM are
manufactured.
Disadvantage of Mask Read Only Memory (MROM)
Design errors are costly i.e. if an error in the code is detected, the MROM is useless and
must be replaced in order to change the code. The life expectancy of MROM is also short,
hence requires frequent replacement.

Programmable Read Only Memory (PROM)

PROM stands for Programmable Read Only Memory. PROM is manufactured as a blank
memory. And as its name suggests Programmable, it is programmed after manufacturing.
The user buys a blank memory and enters the desired contents using a PROM program.

The process of programming a PROM is called burning the PROM. There are tiny fuses in a
PROM chip which are burnt open during programming. The data can be programmed only
once and cannot be altered. So it is called one- time programming device.
Applications of Programmable Read Only Memory (PROM)
The Programmable ROM (PROM) are used in:
 Mobile Phones for providing User Specific Selections.
 Video game consoles
 Implantable Medical devices.
  Radio-Frequency Identification (RFID)tags.
 High definition Multimedia Interfaces(HDMI)
Advantages of Programmable Read Only Memory (PROM)
The advantages of Programmable ROM (PROM) are: –
 The programming can be done using many types of software and does not rely on
hard wiring of the program to the chip.
 Since it is not possible to un-blow the fuse, so the authenticity of the data remains
intact and it is impossible to remove or alter the contents.
Disadvantage of Programmable Read Only Memory (PROM)
The biggest disadvantage of PROM is that the data once burnt cannot be erased or changed
when detected with errors.

Erasable Programmable Read Only Memory (EPROM)

EPROM stands for Erasable Programmable Read-Only Memory. It is a non volatile memory
i.e. it can retain data even if the power supply is cut off. The basic limitation being
encountered in PROM is that once it is programmed, it cannot be changed or altered. This
limitation has been overcame by EPROM.
EPROM can be erased by exposing it to ultra violet light for a particular length of time using
an EPROM eraser. After exposing, the chip returns to its initial state and can be
reprogrammed.
This procedure can be carried out many times but repeated erasing and rewriting can
eventually render the chip useless. Once written, data can be retained for about 10 years.
Applications of Erasable Programmable Read Only Memory (EPROM)
The applications of Erasable Programmable ROM (EPROM) includes:
 As program storage chip in Micro controllers.
 For debugging.
 For program development.
 As BIOS chip in computers.
 As program storage chip in modem, video card and many electronic gadgets.
Advantages of Erasable Programmable Read Only Memory (EPROM)
The advantages of Erasable Programmable ROM (EPROM) are:
 It is non-volatile.
 It can be erased and re -programmed.
 It is cost effective as compared to PROM.
Disadvantages of Erasable Programmable Read Only Memory (EPROM)
The disadvantages of Erasable Programmable ROM (EPROM) are:
 The static power consumption is high as the transistors used have higher resistance.
 It is not possible for a particular byte to be erased, instead the entire content is
erased.
 UV based EPROM takes time to erase the content.

Electrically Erasable Programmable Read Only Memory (EEPROM)

EEPROM is the short form for Electrically Erasable Programmable Read Only Memory. It is
similar to EPROM and thus developed to overcome the drawbacks of EPROMs. It is erased
and programmed electrically i.e. it uses electrical signals instead of ultra violet rays.
The erasing and programming of data takes 4 to 10 milliseconds. Any byte can be erased at
a time instead of the entire chip. The chip can be erased and re programmed for around ten
thousand times, though the process is flexible but slow.
Applications of Electrically Erasable Programmable Read Only Memory (EEPROM)
The applications of Electrically Erasable Programmable ROM (EPROM) includes:
 As BIOS chip in computers
 As storage for re-programmable calibration information in test-equipment.
 As storage for in-built self learning functionality in remote operated transmitters.
Advantages of Electrically Erasable Programmable Read Only Memory (EEPROM)
The advantages of Electrically Erasable Programmable ROM (EEPROM) are:
 The method of erasing is electrical and instant.
 Chip can be reprogrammed infinite number of times.
 Byte wise data can be erased instead of entire content on the board.
 To change the data, additional devices are not required.
Disadvantages of Electrically Erasable Programmable Read Only Memory (EEPROM)
The disadvantages of Electrically Erasable Programmable ROM (EEPROM) are:
 Different voltages are required for erasing, reading and writing the data.
 The data retention period of EEPROM is limited i.e 10 years approx.
 EEPROM devices are expensive compared to others.
Flash Read Only Memory (Flash ROM)
It is a universal flash programming non volatile utility, used in computer as a storage
medium. It can be electrically erased and reprogrammed. In this, memory blocks of data
(512 bytes) can be deleted and written at a particular time.

• High density than EEPROM

• Faster erase and write time than EEPROM
• 2 mode of erase
– bulk erase: erase all cell
– sector erase: specified part of cell to erase e.g. 512 bytes
• Typical 10 usec write time
• Example 28F256A

Has the in-circuit electrical erase-ability of an EEPROM and the high density and low cost of
an EPROM (a single transistor is used at each cell location just like an EPROM).
Blocks or sectors of the memory array are erased at one time. Thereby, only a sector of the
memory is erased and written to.
Example: USB FLASH cartridges or “sticks”. 1 GB or more is ~$30 (Fall 2007).
Applications of Flash Read Only Memory (Flash ROM)
The applications of Flash Read-Only Memory (Flash ROM) are:
 The latest technology computers use BIOS stored on a flash memory chip, called as
flash BIOS.
 Modems, pen drives, small cards use flash ROM.
Advantages of Flash Read Only Memory (Flash ROM)
The Advantages of Flash Read-Only Memory (Flash ROM) are:
 High transferring speed.
 It saves data when turns OFF, preserve its state without power.
 Less prone to damage.
 Comparatively economical to other drives in small storage capacities.
Disadvantages of Flash Read Only Memory (Flash ROM)
The disadvantages of Flash Read-Only Memory (Flash ROM) are:
 Comparatively costly than hard disk.
 Number of read/writes are limited.

ROM Applications:
• Firmware: OS programs and language interpreters
• Bootstrap Memory: when the computer is powered on, it will execute the
instructions that are in bootstrap program
• Data Tables
• Data Converter
• Function Generator
• Auxiliary Storage
 RANDOM ACCESS MEMORY(RAM)

• RAM(Random Access Memory) is a part of computer’s Main Memory which is

directly accessible by CPU.
• RAM is used to Read and Write data into it which is accessed by CPU randomly.
• RAM is volatile in nature, it means if the power goes off, the stored information is
lost.
• RAM is used to store the data that is currently processed by the CPU. Most of the
programs and data that are modifiable are stored in RAM.

Block diagram of RAM:

CS WR Memory operation
0 x None
1 0 Read selected word
1 1 Write selected word

This block diagram introduces the main interface to RAM.

 A Chip Select, CS, enables or disables the RAM.
 ADRS specifies the address or location to read from or write to.
 WR selects between reading from or writing to the memory.
 To read from memory, WR should be set to 0.
 OUT will be the n-bit value stored at ADRS.
 To write to memory, we set WR = 1.
 DATA is the n-bit value to save in memory.
Construction of a 4 x 3 RAM (with decoder and OR gates):

 There is a need for decoding circuits to select the memory word specified by the
input address.
 During the read operation, the four bits of the selected word go through OR gates to
the output terminals.
 During the write operation, the data available in the input lines are transferred into
the four binary cells of the selected word.
 A memory with 2k words of n bits per word requires k address lines that go into kx2k
decoder.
RAM architecture:

• Set the address code at address bus

• Activate /CS (Chip Select)
• When Write
– set Data to Data bus
– R/-W set low
• When Read
– R/-w set high
– Data comes out to data bus
– /OE
 TYPES OF RAM

RAM is of two types

 Static RAM (SRAM)

 Dynamic RAM (DRAM)

Static RAM (SRAM):

 The word static indicates that the memory retains its contents as long as power is
being supplied. However, data is lost when the power gets down due to volatile
nature.
 SRAM chips use a matrix of 6-transistors and no capacitors. Transistors do not
require power to prevent leakage, so SRAM need not be refreshed on a regular
basis.
 There is extra space in the matrix, hence SRAM uses more chips than DRAM for the
same amount of storage space, making the manufacturing costs higher. SRAM is
thus used as cache memory and has very fast access.

Characteristic of Static RAM

 Long life

 No need to refresh

 Faster

 Used as cache memory

 Large size

 Expensive

 High power consumption

Design Of SRAM
 A typical SRAM cell is made up of six MOSFETs. Each bit in an SRAM is stored on
four transistors (M1, M2, M3, M4) that form two cross- coupled inverters.
 This storage cell has two stable states which are used to denote 0 and 1.
 Two additional access transistors serve to control the access to a storage cell during
read and write operations.
 An SRAM cell has three different states. It can be in: standby (the circuit is idle),
reading (the data has been requested) and writing (updating the contents).

Depending on the function performed by SRAM, it can be divided into the following types-

1. Asynchronous SRAM (ASRAM) – It performs its operations without the use of

system clock. It makes use of three signals for working, namely, chip select (CS),
write enable (WE) and output enable (OE). The CS signal enables the processor to
select the memory for performing read and write operations. If CS = 0, then the
memory is enabled to perform the operations. If CS = 1, then the memory is disabled
and operations, such as reading and writing, cannot be performed. The WE signal
makes the decisions related to data, i.e., whether it should be read from or write to
the memory. If WE =0, then no data can be read from or written to the memory. The
 OE signal is an active low signal. It enables the processor to give the output for the
data. If OE = 0, then only it will output the data.

2. Burst SRAM (BSRAM) – It works in association with the system clock and is also
called synchronous SRAM. BSRAM is most commonly used with high-speed
application because the read and write cycles are synchronized with the clock cycles
of the processor. The accessed – waiting time gets reduced after the read and write
cycles are synchronized with the clock cycles. The speed and the cost of BSRAM
increases or decreases simultaneously.

3. Pipeline Burst SRAM (PBSRAM) – It uses pipeline technology in which a large

amount of data is broken up in the form of different packets containing data. These
packets are arranged in a sequential manner in the pipeline and are sent to the
memory simultaneously. PBSRAM can handle a large amount of data at a very high
speed. It is the fastest type of SRAM, since it can operate at bus rates as high as 66
MHz

Dynamic RAM (DRAM):

 In DRAM , the binary data is stored as charge in capacitor where the presence and
absence of charge determines the value of stored bit .

 But data in capacitor cannot be stored for a long time because a capacitor holds an
electrical charge for a limited amt. of time as the charge gradually drains away.

 DRAM cells require a periodic refreshing of the stored data .

 The use of capacitor as the primary storage device generally enables the DRAM cell
to be realized on a much smaller area.

 Access devices or switches are used for RD/WR

Characteristics of Dynamic RAM:
 Short data lifetime
 Needs to be refreshed continuously
 Slower as compared to SRAM
 Used as RAM
 Smaller in size
 Less expensive
 Less power consumption
The DRAM can be divided into the following types-
1. Synchronous DRAM (SDRAM) – SDRAM performs its operations in the synchronous
mode, i.e., in association with the clock cycle of the processor bus. It has two internal
memory banks such that if the address lines are sent from the first bank, then the
address can be read by using the second bank. The internal banks are used since the
row and column address lines need to be charged for reading an address. SDRAM
provides a synchronous interface in which it waits for a clock signal before
responding to a control input. In general, it is used with the processors for storing
the data in a continuous manner. The continuous form of data storage helps in
processing more number of instructions per unit time that increases the speed of
data access.
2. Rambus DRAM (RDRAM) – It is designed by Rambus Inc. it work at a faster speed, as
compared to SDRAM. It is compact in size and uses 16-bit address bus. It provides
the facility to transfer data at a maximum speed of 800 MHz. it contains multiple
address and data lines that help in increasing the speed of data access. These
multiple address and data lines help in performing different read and write
operations simultaneously. It is not famous among users because of its high cost and
low compatibility.
3. Extended Data Out DRAM (EDODRAM) – It can access more than one bit of data at
one time which helps in achieving faster data access rates. It provides the facility to
perform various operations at one time such as reading, writing, etc. it starts
accepting the next bit of data immediately after getting the first bit of data for
performing read or write operating.
 4. Fast Page Mode DRAM (FPMDRAM) – It makes use of paging in which read or write
operation is performed by selecting the address of the data from the rows and the
columns of a matrix. Once the data is read, the address of the particular column is
incremented to read the next part of the data. The paging concept in FPDRAM does
not allow to work with the buses at the memory speed more than 66 MHz.
consequently, a lot of time is consumed in reading and writing the data from the
matrix.
Difference between SRAM & DRAM:
 Code No: R20A0410 R20

MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY

(Autonomous Institution – UGC, Govt. of India)
II [Link] I Semester Examinations
Linear and Digital Integrated Circuits
(EEE)
MODEL PAPER I
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 SECTIONS (One SECTION for each UNIT). Answer FIVE
Questions, Choosing ONE Question from each SECTION and each Question carries 14marks
******
SECTION – I
1.a) Explain the operation of non-inverting Op-amp and derive the expression for
output voltage? [10M]
b)If the differential voltage gain and common mode voltage gain of a differential
amplifier are 48dB and 2 dB respectively then calculate the CMRR. [4M]
(OR)
2.a)Explain the Working of Instrumentation Amplifier withsuitable diagram. [7M]
b)Calculate the hysteresis voltage for the schmitt trigger from the given
specification:
R2 =56kΩ , R1 = 100Ω ,Vref = 0v & Vsat = ±14v. [7M]

SECTION-II
3.a) Draw the circuit and explain the operation of 1st order LPF Butterworth filter. [7M]
b) Design a wide band reject filter having fH= 400 Hz and fL= 2KHz with a
pass band gain of 2. [7M]
4.a) Draw the block diagram ofAstable multivibrator operations using IC 555 and derive
its time constant. [10M]
b)Write the applications of PLL 565. [4M]
SECTION-III

5. Explain the operation of successive approximation ADC and discuss its merits and de-merits.
[14M]
(OR)
6. Explain the R-2R ladder DAC and Inverted R-2R DAC with neat diagram. [14M]
SECTION-IV
7. Design binary to Gray code converter using gates. [14M]
(OR)
8. Design a 32 to 1 multiplexer using four 74×151 multiplexers and 74×139 decoder. [14M]

SECTION-V
9. Explain Decade Binary Counter. [14M]
(OR)
10.a) Explain the functional behavior of Static RAM cell? Show the internal structure
of 8X4 static RAM. [10M]
b) List out the applications of ROM. [4M]
 Code No: R20A0410 R20
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II [Link] I Semester Examinations
Linear and Digital Integrated Circuits
(EEE)
MODEL PAPER II
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 SECTIONS (One SECTION for each UNIT). Answer FIVE
Questions, Choosing ONE Question from each SECTION and each Question carries 14marks
******
SECTION – I
1.a) Using IC7812, design a circuit to generate +5V output [7M]
b) An adder-subtractor circuit designed using operational amplifier is shown below
Determine the output voltage for the given combinations of the inputs. Assume ideal
Op-amp [7M]

(OR)

2.a) Define the term CMRR, Input offset voltage, input offset current, input bias current
out offset voltage with reference to OPAMPs [7M]
b) Explain the operation of Schmitt trigger with the help of neat sketches [7M]

SECTION-II
3.a) Design first order Butterworth low pass filter with high cutoff frequency fH = 1.59 KHz and pass
band gain of 10. Compute the gain at cutoff frequency. Plot the frequency response of the designed
filter [7M]
b) Compare and contrast, minimum any four features of active filters with
passive filters [7M]
 (OR)
4.a) Explain mono-stable multi vibrator using IC 555 [7M]
b) If RA = 6.8 K, RB = 3.3 K, C = 0.1 µF in a 555 based astable multivibrator, calculate
the following
1) thigh 2) tlow 3) Free running frequency 4) Duty cycle [7M]
SECTION-III
5.a) Calculate the number of bits required to represent a full scale voltage of 10V with a
resolution of 5mV approximately [7M]
b) List out different types of A/D converters [7M]
(OR)
6. Explain the operation of weighted resistor DAC with neat circuit diagram [14M]
SECTION-IV
7. a) Explain 4 bit parallel adder [7M]
b) Explain 4-bit magnitude comparator [7M]

(OR)
8. Explain Decoders [14M]

SECTION-V
9. Explain 3 bit asynchronous counter with neat diagram [14M]
(OR)
10.a) Assume the propagation delay of each flip-flop is 12 ns. What is the total propagation
delay and the max clock frequency of a 3 bit asynchronous Binary counter [7M]
b) Explain the 2-bit synchronous binary counter [7M]
 Code No: R20A0410 R20
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II [Link] I Semester Examinations
Linear and Digital Integrated Circuits
(EEE)
MODEL PAPER III
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 SECTIONS (One SECTION for each UNIT). Answer FIVE
Questions, Choosing ONE Question from each SECTION and each Question carries 14marks
******
SECTION – I
[Link] the operation of inverting & non-inverting amplifier and derive the
expression for output voltage [14M]
(OR)
2.a) Explain the operation of Schmitt trigger [7M]
b) Explain the features of 723 regulators [7M]

SECTION-II
3. Draw and explain the frequency response of all filters based on frequency range [14M]
(OR)
4. Explain the functional diagram of IC 555 timer [14M]
SECTION-III

5. Explain the operation of ladder type DAC with neat diagram [14M]
(OR)
6. Explain the operation of counter type ADC [14M]
SECTION-IV
7. Explain Encoders [14M]
(OR)
8. Explain an 8-input Data Selector / Multiplexer [14M]

SECTION-V
9. Explain the synchronous BCD decade counter [14M]
(OR)
[Link] is the shift register? Explain different kinds of shift Register [14M]
 Code No: R20A0410
R20
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
II [Link] I Semester Examinations
Linear and Digital Integrated Circuits
(EEE)
MODEL PAPER IV
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 SECTIONS (One SECTION for each UNIT). Answer FIVE
Questions, Choosing ONE Question from each SECTION and each Question carries 14marks
******
SECTION – I
1. Explain the operation of inverting and non-inverting Comparator [14M]

(OR)
2. Explain the working of an ideal & practical differentiator [14M]
SECTION-II
3. With a neat diagram explain about triangular wave generator and derive the frequency
of oscillation [14M]
(OR)
4. Explain the operation ofAstable multivibrator using IC 555 timer and derive the
expression for frequency of oscillation [14M]
SECTION-III
5. a)For a Digital to Analog converter (DAC) with 0-10 Volts range, calculate the values of
LSB, MSB and output voltage for a digital input of 1010. Estimate the DAC’s
Quantization error [7M]
b) Design a R-2R network for DAC [7M]

(OR)
6. a)Explain Successive approximation ADC with conversion process [7M]
b) Explain dual slope ADC with neat diagram [7M]
SECTION-IV
7. a)Draw the 4 bit Parallel Adder (74LS283) and logic diagram. Explain its functioning
with one example. [7M]
b)What are decoders? Draw the pin diagram of and logic diagram of 4X16 Decoder
 (74HC154). [7M]

(OR)
8.a) Design binary to Gray code converter. [10M]
b) Explain the operation of MUX [4M]

SECTION-V
9. Design a Modulo-10 counter using any flip flop. [14M]
(OR)
10. Design a conversion circuit to convert an S-R Flip Flop to J-K Flip Flop? [14M]
 R20
Code No: R20A0410

MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY

(Autonomous Institution – UGC, Govt. of India)
II [Link] I Semester Examinations
Linear and Digital Integrated Circuits
(EEE)
MODEL PAPER V
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 SECTIONS (One SECTION for each UNIT). Answer FIVE
Questions, Choosing ONE Question from each SECTION and each Question carries 14marks
******
SECTION – I
1. Draw and explain the operation of an basic integrator and practical integrator
[14M]
(OR)
2. Explain the operation of inverting and non-inverting AC amplifier [14M]
SECTION-II
3. Explain how a symmetrical wave form can be constructed using 555 timer [14M]
(OR)
4. Explain the operation of PLL . [14M]
SECTION-III

5. Explain the operation of parallel comparator type ADC with the help of a neat diagram.
[14M]
(OR)
6. Explain the DAC and ADC specifications. [14M]
SECTION-IV
7. Explain Binary to Gray and Gray to Binary code conversion with one example each [14M]
(OR)
8. Explain the IC interfacing between TTL and CMOS [14M]

SECTION-V
9. Explain the operation of D filp-flop and T flip-flop with truth table [14M]
(OR)
10. Explain about ROM and RAM [14M]