All of these are NCG positions
Nvidia Verification Engineer (Emulation team, Santa Clara):
Phone Interview
• What is transport and inertial delay?
• How to swap 2 numbers without a temporary register?
• What is setup and hold times?
• How to prevent setup and hold time violations
• How does cache from one processor access data from another processor cache
• How is clock gating performed?
• What is difference between flipflop and latch
• How do synthesis tools work?
• How is non unified cache better than unified cache?
• How to model inertial and transport delay?
• What is difference between == and ===?
• What is difference between wire and reg?
• What is reg default value and wire default value?
• Why do we use asynchronous resets?
Virtual On-site:
• Explain MESI protocol. From here he went to Owned state and Forward state.
• Write a function to copy a string given 2 character pointers as inputs.
• Insert a node into a linked list
• Write a constraint to make address+length fields inside a block of 4096 addresses.
• Implement a 2x1 Mux using NAND gates
• What gates are used in a full adder and half adder
• Explain about pipelining
• How to sort a group of files in Linux OS(Ans: Use Sort)
• How will you verify operations in a CPU?
• How to check if a number is odd
• What are the advantages and disadvantages of 5 stage and 10 stage pipeline
• Difference between blocking and non blocking assignment
• If a = b, c = d, and X= a+c, what kind of circuit does this represent
• What are the advantages of NUMA and UMA memories
• Explain in an equation how fifo full and fifo empty are generated.
• What is MMU?
• How do you verify Memory Controller?
Micron Design Verification Engineer(NAND Memory Team, San Jose)
Screening Round:
• Describe the basic components of a testbench.
• Can we use a sequence/sequencer to monitor data in the agent.
• Complete the task given below:
Qualcomm Front End Design Engineer (Snapdragon CPU subsystem design team, San Diego)
Screening Round:
• What is setup and hold time?
• How do you resolve setup and hold time violations?
• Equations for setup and hold time?
• How to check if a number is an exponent of two?
• Timing regions in systemverilog?
• Design FSM for 11011 detector?
• Write a 5x1 mux using 2x1 muxes?
• Twrite=5ns, Tread=50ns Burst Size is 100 Find FIFO Depth?
• What are the problems in CDC?
• How can we resolve these problems?
• Difference between task and function?
NXP Semiconductors SoC Verification Engineer(Automotive Team, Austin)
Virtual On-site:
• What is the difference between synchronous and asynchronous reset?
• If you have 16 inputs connected to 16 outputs, how will you find which is connected to which?
• Explain polymorphism in SystemVerilog
• Find out if a number is an exponent of 2 or not?
• Where do we use Dual Port RAM
• Explain about factory in UVM
• Explain about Phases in UVM
• Write a Python Code to convert a string into a list and a list into a dictionary
• Draw an FSM to detect whether a number is divisible by 5 in a bit stream
• How does a compiler in SystemVerilog execute blocks in parallel
Google ASIC DV Engineer(Gchips team, Mountain View)
Introductory Video Chat:
• If I used a fork inside a function, which should I use? a) join b) join_none c) join_all d) join_any e)
join_fork
• Declare a queue of type int with the name foo
• What are the main phases used in UVM
• When a sequence is started, which task is executed first?
• Which component is responsible for sending the sequence items to the driver
• How to deallocate memory from an object in systemverilog
• Differences between functions and tasks?
• How many address bits do we need for 4096 addresses
AMD Verification Engineer(Unified Memory Controller Verification Team, Austin or Boston)
Screening Round 1:
• Write the logic for a 1 bit adder
• Write the logic for sum when you can’t use xor gate
• Write a checker such that a given 2 bit command can’t be equal to 2 more than 4 times within 60
clock cycles
• Write an fsm to detect if a number is divisible by 3
• How will you verify an ALU with 4 bit inputs, 8 bit output, a valid bit, an overflow bit, and a 2 bit
opcode
• Write a sequence item class for this alu
• What is the use of uvm_object_utils
• Why are the derived class methods called instead of base class methods in uvm
• Write a constraint such that an array of inputs will never be equal and also never equal to the
other input when the index is same
Screening Round 2:
• Write UVM code for sequence item, sequence, and driver for a Single Port RAM module
• Draw an FSM to detect the sequence 10110(overlapping).
• Can we design the above sequence detector without using an FSM? If so, how?
• Write a C language code to reverse the digits of a given decimal number?
NVIDIA ASIC DV Interview (NCG Role):
• 1. There is an array having duplicate elements , Write a code in your preferred language to
remove the duplicates.
• 2. Verification Plan for an alarm clock.
• 3. Write a FSM in SV for the same alarm clock design.
