Let’s go through all core STA (Static Timing Analysis) concepts that are essential for

Physical Design (PD) — from basics to advanced, explained step-by-step.

🧠 1. What is STA (Static Timing Analysis)?

Static Timing Analysis (STA) is a method to verify the timing performance of a digital
design without applying test vectors.
It ensures that signals propagate through combinational logic and reach sequential
elements (like flip-flops) within the required time defined by the clock period.

STA is “static” because it checks all paths using timing equations instead of simulating
dynamic input patterns.

⚙️ 2. Key Components in STA

Term Meaning

Startpoint Beginning of a timing path (usually flip-flop Q, input port, or latch output).

Endpoint End of a timing path (usually flip-flop D, output port, or latch input).

Path The connection from startpoint → combinational logic → endpoint.

Clock Defines when data is launched and captured.

Slack Margin between required time and arrival time.

Setup & Hold Times Constraints of flip-flops/latches.

⏱ 3. Timing Paths in STA

There are four main path types STA checks:
1. Register to Register
2. Input to Register
3. Register to Output
4. Input to Output

Each must satisfy setup and hold requirements.

🧩 4. Timing Equations
Setup Analysis (Max Delay Path)
Ensures data arrives before the next clock edge.

Slack (Setup) = Required Time − Arrival Time

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 Required Time = Tclk + Tlatencycapture − Tsetup
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Arrival Time = Tclk−q + Tcomb + Tlatencylaunch

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If slack < 0 → setup violation.

Hold Analysis (Min Delay Path)

Ensures data doesn’t arrive too early before the capturing flip-flop’s hold window.

Slack (Hold) = Arrival Time − Required Time

Arrival Time = Tclk−q + Tcomb + Tlatencylaunch

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​
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Required Time = Tlatencycapture + Thold

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If slack < 0 → hold violation.

🔄 5. Types of Delays
Type Description

Cell Delay Delay within a logic cell (depends on input transition & output load).

Net Delay Delay through interconnects (depends on wire length, RC parasitics).

Clock Delay / Latency Time for clock to reach flip-flop from source.

Skew Difference in arrival time of clock between launch and capture FFs.

Transition Time (Slew) Time taken for signal to rise or fall (10% → 90%).

⏰ 6. Clock Concepts
Concept Meaning

Clock Latency Delay from clock source to FF pin (insertion delay).

Clock Skew Difference between launch & capture clock arrivals.

Clock Jitter Random variation of clock edge arrival over time.

Clock Uncertainty Combined effect of jitter + on-chip variation margins.

🧮 7. Key Timing Parameters

Parameter Description

Data Arrival Time Time taken for data to reach the endpoint.

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Parameter Description

Data Required Time Time by which data must arrive for correct operation.

Slack Required Time – Arrival Time (for setup); reverse for hold.

Tclk-q Delay from clock edge to valid Q output.

Tsetup / Thold Setup and hold requirements of flip-flop.

🧠 8. PVT Corners and Timing Libraries

STA is performed at different PVT corners:

Process Voltage Temperature Type

SS Min Min Worst for setup

FF Max Max Worst for hold

TT Typical Typical Typical analysis

👉 Setup violations usually occur at slow corner (SS)

👉 Hold violations usually occur at fast corner (FF)
🧰 9. STA in Physical Design Flow
PD Stage STA Purpose

Pre-CTS (Before Clock Tree) Ideal clocks used → check setup timing.

Post-CTS (After Clock Tree) Actual skew and latency known → check setup & hold.

Post-Route STA With real parasitics (RC extraction).

Signoff STA Final STA with SI, IR drop, OCV, etc. (PrimeTime/Tempus).

⚖️ 10. Timing Violations & Fixes

Violation Cause Fix

Setup Path too slow Increase drive strength, reduce load, pipeline, reduce logic depth,
use faster cells.

Hold Path too fast Insert delay buffers, lengthen wire, use smaller cells.

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Violation Cause Fix

Clock Skew Clock Adjust CTS or buffer insertion.

Issue imbalance

⚡ 11. Advanced STA Concepts

Concept Description

OCV (On-Chip Variation) Variation in process parameters across chip.

AOCV / POCV Advanced models considering path length and depth.

SI (Signal Integrity) Crosstalk-induced delay changes.

MCMM (Multi-Corner Multi-Mode) Checking multiple corners and modes (functional, scan, etc.)
simultaneously.

CRPR (Clock Reconvergence Pessimism Correction for shared clock path pessimism.
Removal)

Multi-Cycle Paths Data valid after multiple cycles → use

set_multicycle_path .

False Paths Paths that never activate → use set_false_path .

📈 12. STA Reports

Common reports from tools (like PrimeTime, Tempus):

report_timing
report_clocks

report_constraints

report_slack

report_path_group

Each report helps identify critical paths and timing bottlenecks.

🧩 13. STA Commands (Synopsys PrimeTime Basics)

Command Function

read_verilog Load netlist

read_liberty Load .lib timing files

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Command Function

read_sdc Load constraints

set_operating_conditions Set corner

update_timing Perform STA

report_timing Show timing path

report_clock Show clock properties

report_constraints Show setup/hold violations

✅ 14. Final Goal of STA in PD

At signoff, the design must have:
All setup slacks ≥ 0
All hold slacks ≥ 0
No max transition or cap violations
Clock skew & uncertainty within limits
All corners and modes clean

Only then, the chip is timing-closed and ready for tape-out.

Would you like me to make this into a visual diagram or PDF summary (like a “STA
Cheatsheet for Physical Design”) for easy revision?

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