ABSTRACT:
This study presents the Design, Meshing, And Electrical Characterization of a
Gate-All-Around Silicon Nanowire MOSFET (GAA-NW-MOSFET) using
Synopsys Sentaurus TCAD. The device consists of a Cylindrical Silicon
Nanowire Channel with a 10 nm radius and 20 nm gate length, surrounded by a
2 nm SiO₂ gate dielectric and a metal gate electrode that provides complete
360° electrostatic control. Compared to conventional planar MOSFETs, the
GAA architecture offers superior gate controllability, effectively suppressing
Short-Channel Effects (SCEs) and enhancing Electrostatic Integrity.
A symmetric N⁺–P–N⁺ doping configuration was implemented, with heavily
doped source/drain regions (1×10²⁰ cm⁻³) and a lightly doped channel (1×10¹⁶
cm⁻³). The device structure was carefully meshed to capture the detailed
geometry and doping gradients, ensuring high simulation accuracy. Advanced
physical models, including doping-dependent mobility, Shockley–Read–Hall
recombination, and bandgap narrowing, were employed to achieve realistic
electrical behavior. These models account for real material and carrier behaviors
under varying bias conditions, enabling more realistic simulation results. The
use of these models also enhances the reliability of the device’s predicted
electrical characteristics and performance trends.
The transfer characteristics (Id–Vgs) were simulated to analyze the transistor’s
switching response. The results confirm successful device operation and
demonstrate clear current modulation with varying gate voltage, indicating
effective gate control in the GAA nanowire MOSFET. Future work will include
detailed extraction of Ioff, Ion/Ioff ratio, and DIBL parameters to provide a
comprehensive evaluation of device performance and scalability.
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INTRODUCTION:
Understanding the Need for New Transistors:
Every modern electronic device — from smartphones to laptops — depends on
transistors, which act as microscopic switches that control the flow of electric
current.
The most common type of transistor used today is the MOSFET (Metal–Oxide–
Semiconductor Field-Effect Transistor). In a MOSFET, applying a voltage to
the gate terminal controls the movement of electrons from the source to the
drain through an energy barrier in the channel region.
As semiconductor technology continues to scale down into the nanometre
range, conventional MOSFETs begin to face serious performance issues. When
the channel length becomes very short, several problems arise:
The transistor starts leaking current even when it is turned off.
The gate loses control over the channel charge.
The subthreshold slope is limited by the 60 mV/decade limit, which
restricts how efficiently the device can switch from OFF to ON.
Short-channel effects (SCEs) such as Drain-Induced Barrier Lowering
(DIBL) and threshold voltage roll-off degrade performance.
These issues result in increased power consumption, reduced switching
speed, and poor reliability.
To overcome these limitations and achieve lower power operation with better
switching, researchers have developed new transistor architectures such as the
Tunnel Field-Effect Transistor (TFET) and Double Gate (DG) MOSFETs.
What is a Tunnel Field-Effect Transistor (TFET)?
The Tunnel Field-Effect Transistor (TFET) operates on the principle of quantum
tunneling, a phenomenon where electrons can pass through an energy barrier
instead of going over it — provided the barrier is sufficiently [Link] understand
this, imagine a MOSFET as a person trying to jump over a wall, while a TFET
allows the person to walk through the wall using a “quantum door.”
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Because TFETs use tunneling instead of thermal energy to move carriers, they
can achieve a subthreshold swing smaller than 60 mV/decade, which is
impossible in a conventional MOSFET.
This makes TFETs capable of operating at much lower voltages, drastically
reducing power consumption.
In TFETs, the gate voltage controls how thin the tunneling barrier becomes.
When the gate is OFF, the barrier is thick, and electrons cannot tunnel —
current is nearly zero.
When the gate is ON, the barrier becomes thin enough for electrons to
tunnel through, creating current flow from source to drain.
Structure Of The N⁺–P–N⁺ TFET:
A TFET consists of three main regions:
1. Source – where charge carriers originate,
2. Channel (Body) – controlled by the gate, and
3. Drain – where carriers exit.
In our structure:
The Source is n⁺-type, heavily doped with donor atoms (1×10²⁰ cm⁻³) to
provide abundant free electrons.
The Channel (Body) is p-type, lightly doped (1×10¹⁶ cm⁻³) to contain
more holes.
The Drain is n⁺-type, similar to the source.
This doping configuration forms an n⁺–p–n⁺ structure. You can imagine it as a
sandwich — with heavily doped n⁺ layers as the “bread” and the lightly doped
p-type layer as the “filling,” where tunneling occurs.
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Working Principle Of The N⁺–P–N⁺ TFET:
In the OFF state (when gate voltage VGS= 0), the energy barrier between the n⁺
source and p-type channel is wide and tall. Electrons cannot tunnel through it,
so the current is extremely small — the transistor is OFF.
As the gate voltage increases, it lowers the energy bands in the p-type channel,
making the barrier thinner and narrower.
At a certain gate voltage, electrons from the n⁺ source can tunnel through the
barrier directly into the channel. Once they tunnel, they are swept quickly to the
drain by the electric field, producing current flow.
When the gate voltage becomes high enough, the barrier almost disappears,
allowing a large number of electrons to tunnel — resulting in a sharp rise in
current (ON state).
In short:
Gate OFF → Barrier wide → No tunneling → Current ≈ 0
Gate ON → Barrier thin → Electrons tunnel → Current flows
This tunneling effect allows TFETs to switch sharply at low voltages, achieving
high efficiency with minimal power loss — ideal for low-power IoT and
portable electronics.
Why Use N⁺–P–N⁺ Instead Of P⁺–N–N+:
Earlier TFET designs used a p⁺–n–n+ doping profile, where holes were the main
tunneling carriers. However, holes have a higher effective mass and lower
mobility than electrons, meaning they move slower and tunnel less efficiently.
By reversing the polarity to n⁺–p–n⁺, electrons become the tunneling carriers.
Electrons are lighter, faster, and have higher mobility, resulting in:
Higher ON current (ION),
Steeper subthreshold slope (SS),
Faster switching, and
Better overall energy efficiency.
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Thus, the n⁺–p–n⁺ structure provides much improved performance compared to
p⁺–n–n+configurations.
Gate-All-Around (GAA) Nanowire Design:
The Gate-All-Around (GAA) structure is an advanced 3D transistor design
where the gate completely surrounds the channel — like a hollow cylinder
wrapped around a silicon nanowire.
This geometry offers superior electrostatic control over the channel, since the
gate influences it from all sides rather than just the top.
Key advantages of the GAA nanowire structure include:
Excellent control of the channel potential,
Strong suppression of short-channel effects (SCEs),
Uniform current flow through the channel, and
Very low leakage current in the OFF state.
Because of these advantages, the GAA structure is considered one of the best
geometries for nanoscale transistors and is widely adopted in advanced 3D
MOSFETs and TFETs. The GAA nanowire geometry ensures complete gate
control, minimizing leakage and short-channel effects.
Together, these features make the TFET a highly promising device for next-
generation low-power, high-performance electronic systems.
Tunneling and Short-Channel Effects in Modern Devices:
As devices scale down, short-channel effects become more dominant — the
drain’s electric field starts affecting the source–channel junction, reducing the
threshold voltage and increasing leakage. This leads to poor device control and
degraded subthreshold performance.
By combining tunneling conduction (in TFETs) with a 3D Gate-All-Around
structure, we can achieve both:
Steep switching through quantum tunneling, and
Strong electrostatic gate control to suppress short-channel effects.
This combination ensures that the device remains energy-efficient, fast, and
scalable even at nanometer dimensions.
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LITERATURE REVIEW AND LEARNING OUTCOME:
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Analytical Modeling of Junctionless Cylindrical Surrounding Gate
Nanowire MOSFETs (Pandian et al., 2014)
What they did?
Pandian et al. proposed an analytical model for a junctionless nanowire
MOSFET with a cylindrical Gate-All-Around (GAA) structure. They solved the
Poisson equation to obtain the potential distribution in the channel and derived
the drain current expressions for different operating regions. The analytical
results were compared with TCAD simulations, and both showed excellent
agreement. The study proved that reducing the silicon radius and oxide
thickness enhances gate control and reduces short-channel effects.
What we learned?
From this paper, we understood how device geometry directly affects the
electrostatic behavior of nanoscale transistors. The concept of a Gate-All-
Around cylindrical structure taught us that surrounding the channel with the
gate gives much stronger control compared to a single top gate. This helps in
reducing leakage current, improving subthreshold slope, and minimizing
threshold voltage [Link] idea guided our own 3D DG-MOSFET design —
showing that careful selection of channel thickness, oxide layer, and doping
concentration can significantly enhance device performance by suppressing
short-channel effects and improving current control.
Analytical and Simulation Investigation of Nanowire Tunnel FET (Kumar
et al., 2021)
What they did?
Kumar et al. performed both analytical modeling and TCAD simulation of a
nanowire Tunnel Field-Effect Transistor (TFET) using a Gate-All-Around
structure. They evaluated the potential profile and drain current under various
bias conditions and showed that the GAA geometry provides excellent
electrostatic control. Their study also highlighted how parameters like oxide
thickness, channel radius, and doping concentration influence the tunneling
current and overall device performance. The results confirmed that GAA
nanowire TFETs offer a low subthreshold swing and high ON/OFF current ratio,
making them ideal for low-power applications.
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What we learned?
From this study, we learned how quantum tunneling and strong gate coupling
can be combined to improve transistor performance at the nanoscale. The paper
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emphasized the role of Gate-All-Around control in achieving efficient
switching and reducing leakage [Link] understanding helped us in
visualizing the benefits of using a 3D DG-MOSFET structure in our project.
Even though our work focuses on MOSFETs rather than TFETs, the principle
remains the same — surrounding the channel with multiple gates or a 3D
structure ensures better electrostatic control, reduced short-channel effects, and
enhanced current flow. These concepts provided the theoretical foundation for
our design and meshing work in TCAD.
Channel-Length Scaling Pattern for Cylindrical Surrounding Double-Gate
(CSDG) MOSFETs (Maduagwu & Srivastava, 2020):
Maduagwu and Srivastava analyzed scaling behavior and natural length (λ) for
cylindrical double-gate devices to quantify short-channel control. Using the
parabolic potential approximation, they derived λ as a function of silicon-body
radius and oxide thickness. Their study found that the CSDG structure exhibits
the smallest natural length among comparable devices, allowing aggressive sub-
10 nm scaling. They recommended maintaining channel length approximately
five to six times the natural length to minimize short-channel effects. This
model provides valuable scaling design guidelines for nanowire MOSFETs.
Integration with Present Work:
The present project ‘Cylindrical Gate-All-Around Silicon Nanowire MOSFET:
TCAD Simulation and Electrical Characterization’—builds directly upon these
studies. Pandian et al. (2014) provided the analytical base for cylindrical
MOSFET behavior, Kumar et al. (2025) extended analytical frameworks into
tunneling and quantum transport regimes, and Maduagwu & Srivastava (2020)
supplied the scaling guidelines validating our design parameters (10 nm radius,
20 nm gate length). The combination of these foundational works ensures that
our TCAD simulations reflect both theoretical and practical aspects of nanowire
electrostatics.
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Conclusion:
Together, the reviewed works form a coherent pathway from analytical theory to
physical simulation. Our project validates the predicted advantages of the
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cylindrical Gate-All-Around (GAA) architecture—namely enhanced
electrostatic control, scalability, and fabrication simplicity—through practical
3D TCAD simulation. This literature foundation strengthens the case for GAA
nanowire MOSFETs as prime candidates for sub-10 nm VLSI technologies.
PROPOSED WORK:
Objective:
The main objective of this project is to design and simulate a Three-
Dimensional Gate-All-Around (GAA) Tunnel Field-Effect Transistor (TFET)
using Synopsys Sentaurus TCAD tools. The purpose of this work is to study
how a 3D gate-all-around geometry enhances gate control, reduces short-
channel effects, and improves tunneling current characteristics compared to
traditional planar MOSFETs. The n⁺–p–n⁺ doping configuration was selected
because electrons have higher mobility and lower effective mass than holes,
resulting in stronger tunneling efficiency and better ON-state performance.
Device Structure and Configuration:
The proposed TFET structure consists of a cylindrical silicon nanowire channel
that is completely surrounded by a thin SiO₂ gate oxide layer and a metal gate,
forming a true gate-all-around configuration. The source and drain are heavily
doped n⁺-type regions, while the channel is lightly doped p-type, creating an
n⁺–p–n⁺ junction. The total device length is 90 nm, consisting of a 20 nm
source, 50 nm channel, and 20 nm drain. The gate oxide thickness is 2 nm, and
the metal gate has a work function of 4.3 eV. The 3D doping profile was
constructed using Sentaurus Structure Editor (SDE), and a fine non-uniform
mesh was applied near the source–channel and drain–channel interfaces to
capture tunneling regions accurately. The color-coded doping visualization in
Sentaurus Visual (Figure 3.1) shows the heavily doped n⁺ source/drain in red
and the lightly doped p-type channel in blue.
PROPOSED STRUCTURE:
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CROSS SECTIONAL VIEW:
P N+
PARAMETERS:
Working Principle:
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The operation of the n⁺–p–n⁺ TFET is based on band-to-band tunneling
(BTBT) at the source–channel junction. In the OFF state, when the gate voltage
is zero, the energy barrier between the n⁺ source and p-type channel is wide,
preventing electron flow. As the gate voltage (VGS) increases, the gate field
lowers the channel energy bands, reducing the tunneling barrier width. This
enables electrons to tunnel directly from the source conduction band into the
channel valence band, resulting in a rapid rise in current. Once the tunneling
barrier becomes sufficiently thin, the device switches ON and conducts strongly
from source to drain. The double-sided gate control ensures a uniform electric
field around the channel, leading to improved electrostatic control, low leakage,
and steep switching characteristics.
TCAD Simulation Methodology:
The device simulation was carried out using Synopsys Sentaurus TCAD, which
provides a physics-based modeling environment for semiconductor devices. The
structure was defined in Sentaurus Structure Editor (SDE), and meshing was
carefully refined near tunneling junctions to achieve accurate field resolution.
The following physical models were activated: Fermi–Dirac statistics for
degenerate doping, doping-dependent mobility, bandgap narrowing (BGN) in
highly doped regions, Shockley–Read–Hall (SRH) recombination for carrier
lifetime effects, and the non-local Band-to-Band Tunneling (BTBT) model
using the Kane approach to model quantum tunneling. The simulation bias
conditions included sweeping the drain voltage (VDS) from 0 V to 1.2 V for
different gate voltages (VGS) ranging from 0 V to 1.2 V to observe the transfer
and output characteristics.
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CODE FOR CREATING GAA TFET STRUCTURE IN SDE:
(sdegeo:create-cylinder (position 0 0 0) (position 0 0 0.05)
0.017 "Metal" "gate")
(sdegeo:create-cylinder (position 0 0 0) (position 0 0 0.05)
0.012 "SiO2" "oxide")
(sdegeo:create-cylinder (position 0 0 0) (position 0 0 0.05) 0.01
"Silicon" "channel")
(sdegeo:create-cylinder (position 0 0 0) (position 0 0 -0.025)
0.01 "Silicon" "source")
(sdegeo:create-cylinder (position 0 0 0.05) (position 0 0 0.075)
0.01 "Silicon" "drain")
(sdegeo:define-contact-set "[Link]" 4 (color:rgb 1 0 0 ) "##")
(sdegeo:define-contact-set "[Link]" 4 (color:rgb 1 0 1 ) "##")
(sdegeo:define-contact-set "[Link]" 4 (color:rgb 1 1 0 ) "##")
(sdegeo:set-current-contact-set "[Link]")
(sdegeo:set-contact (list (car (find-face-id (position 0.0 0.0
0.075)))) "[Link]")
(render:rebuild)
(sdegeo:set-current-contact-set "none")
"[Link]"
(sdegeo:set-current-contact-set "[Link]")
(sdegeo:set-contact (list (car (find-face-id (position 0.0 0.0 -
0.025)))) "[Link]")
(render:rebuild)
(sdegeo:set-current-contact-set "[Link]")
"[Link]"
(sdegeo:set-contact (list (car (find-face-id (position 0.017 0.0
0.025)))) "[Link]")
(render:rebuild)
(sdedr:define-constant-profile "[Link]"
"BoronActiveConcentration" 1e+16)
(sdedr:define-constant-profile-material "[Link]"
"[Link]" "Silicon")
(sdedr:define-constant-profile "[Link]"
"ArsenicActiveConcentration" 1e+20)
(sdedr:define-constant-profile-region "[Link]"
"[Link]" "source")
(sdedr:define-constant-profile "[Link]"
"ArsenicActiveConcentration" 1e+20)
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SCHEMATIC STRUCTURE IN SDE:
DOPING PROFILE:
Only Source ,Drain And Channel
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(sdedr:define-constant-profile-region "[Link]"
"[Link]" "
(sdedr:define-refeval-window "RefEvalWin_1" "Cuboid" (position
-0.02 -0.02 -0.03) (position 0.02 -0.02 0.08))
(sdedr:define-refinement-size "RefinementDefinition_1" 0.0125
0.0125 0.0125 0.01 0.01 0.01 )
(sdedr:define-refinement-size "RefinementDefinition_1" 0.01
0.01 0.01 0.001 0.001 0.001 )
(sdedr:define-refinement-placement "RefinementPlacement"
"RefinementDefinition_1" (list "window" "RefEvalWin_1" ) )
(sdedr:define-refinement-function "RefinementDefinition_1"
"DopingConcentration" "MaxTransDiff" 1)
(sdedr:define-refinement-function "RefinementDefinition_1"
"MaxLenInt" "SiO2" "Silicon" 0.5 0.54)
(sdedr:define-refinement-function "RefinementDefinition_1"
"DopingConcentration" "MaxTransDiff" 0.001)
(sdedr:define-refinement-function "RefinementDefinition_1"
"DopingConcentration" "MaxTransDiff" 1)
(sdedr:define-refinement-function "RefinementDefinition_1"
"MaxLenInt" "source" "channel" 0.001 1.1 "DoubleSide"
"UseRegionNames")
(sdedr:define-refinement-function "RefinementDefinition_1"
"MaxLenInt" "drain" "channel" 0.001 1.1 "DoubleSide"
"UseRegionNames")
(sdedr:define-refinement-function "RefinementDefinition_1"
"MaxLenInt" "Silicon" "SiO2" 0.001 1.1)
(sde:set-meshing-command "snmesh")
(sde:build-mesh "" "/home/pguser/pro")
"Meshing successful"
(system:command "svisual /home/pguser/pro_msh.tdr &")
Doping Of The Full Structure:
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MESHING:
DEVICE CODE FOR ID vs VGS GRAPH:
File{
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Grid = "pro_msh.tdr"
Plot = "pro_des.tdr"
* Parameter = "@parameter@"
Current = "pro_des.plt"
Output = "pro_des.log"
}
Electrode{
{ Name="[Link]" Voltage=0.0 }
{ Name="[Link]" Voltage=0.0 }
{ Name="[Link]" Voltage=0.0 }
}
Thermode{
{ Name="[Link]" Temperature=300 SurfaceResistance=1e-
3}
{ Name="[Link]" Temperature=300 SurfaceResistance=1e-
3}
}
Physics {
Areafactor=0.05
Mobility( Phumob HighFieldSaturation Enormal )
EffectiveIntrinsicDensity ( Slotboom NoFermi )
}
Physics(RegionInterface="oxide/channel") {
Traps((FixedCharge Conc=1e12))
}
Physics(RegionInterface="IL_top/channel") {
Traps((FixedCharge Conc=1e12))
}
Plot{
*--Density and Currents, etc
eDensity hDensity
TotalCurrent/Vector eCurrent/Vector hCurrent/Vector
eMobility hMobility
eVelocity hVelocity
eQuasiFermi hQuasiFermi
*--Temperature
eTemperature Temperature * hTemperature
ID vs VGS CHARACTERISTICS USING SVISUAL (LINEAR SCALE):
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Id -Vgs
Characteristics
Id (A)
Vgs (V)
*--Fields and charges
ElectricField/Vector Potential SpaceCharge
*--Doping Profiles
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Doping DonorConcentration AcceptorConcentration
*--Generation/Recombination
SRH Band2Band * Auger
ImpactIonization eImpactIonization hImpactIonization
*--Driving forces
eGradQuasiFermi/Vector hGradQuasiFermi/Vector
eEparallel hEparallel eENormal hENormal
*--Band structure/Composition
BandGap
BandGapNarrowing
Affinity
ConductionBand ValenceBand
eQuantumPotential
}
Math {
Extrapolate
Iterations= 20
Notdamped= 100
Method= Blocked
SubMethod= Pardiso
}
Solve {
*- Build-up of initial solution:
NewCurrentPrefix="init_"
Coupled(Iterations=100){ Poisson Electron Hole }
Coupled{ Poisson Electron}
*- Bias drain to target bias
Quasistationary(
InitialStep=0.01 MinStep=1e-5 MaxStep=0.05
Goal{ Name="[Link]" Voltage= 0.1 }
) { Coupled { Poisson Electron Hole } }
ID vs VGS CHARACTERISTICS USING SVISUAL (LOG SCALE):
Id -Vgs
Characteristics
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Id (A)
Vgs (V)
*- gate voltage sweep
NewCurrentPrefix="IdVgs_"
Quasistationary(
InitialStep=1e-3 MinStep=1e-5 MaxStep=0.01
Goal{ Name="[Link]" Voltage= 2 }
) { Coupled { Poisson Electron Hole }
CurrentPlot(Time=(Range=(0 1) Intervals=100))
}
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System("rm init_n1_des.plt")
}
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