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TS3A5018
SCDS189H – JANUARY 2005 – REVISED MAY 2018

TS3A5018 10-Ω Quad SPDT Analog Switch

1 Features 3 Description
•
1 Low ON-State Resistance (10 Ω) The TS3A5018 device is a quad single-pole double-
throw (SPDT) analog switch that is designed to
• Low Charge Injection operate from 1.8 V to 3.6 V. This device can handle
• Excellent ON-State Resistance Matching digital and analog signals, and signals up to V+ can
• Low Total Harmonic Distortion (THD) be transmitted in either direction.
• 1.8-V to 3.6-V Single-Supply Operation
Device Information(1)
• Latch-Up Performance Exceeds 100 mA Per
PART NUMBER PACKAGE BODY SIZE (NOM)
JESD 78, Class II
SOIC (16) 9.90 mm × 6.00 mm
• ESD Performance Tested Per JESD 22
SSOP (16) 6.00 mm × 4.90 mm
– 2000-V Human-Body Mode (A114-B, Class II) TSSOP (16) 5.00 mm × 4.40 mm
– 1000-V Charged-Device Model (C101) TS3A5018
TVSOP (16) 4.40 mm × 3.60 mm
UQFN (16) 2.50 mm × 1.80 mm
2 Applications VQFN (16) 4.00 mm × 3.50 mm
• Sample-and-Hold Circuits (1) For all available packages, see the orderable addendum at
• Battery-Powered Equipment the end of the data sheet.
• Audio and Video Signal Routing
• Communication Circuits
Block Diagram
EN

IN

COM NC

NO

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3A5018
SCDS189H – JANUARY 2005 – REVISED MAY 2018 [Link]

Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................. 17
2 Applications ........................................................... 1 8.2 Functional Block Diagram (Each Switch)................ 17
3 Description ............................................................. 1 8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 17
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3 9 Application and Implementation ........................ 18
9.1 Application Information............................................ 18
6 Specifications......................................................... 4
9.2 Typical Application ................................................. 18
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings ............................................................ 4 10 Power Supply Recommendations ..................... 19
6.3 Recommended Operating Conditions....................... 4 11 Layout................................................................... 19
6.4 Thermal Information .................................................. 4 11.1 Layout Guidelines ................................................. 19
6.5 Electrical Characteristics for 3.3-V Supply................ 5 11.2 Layout Example .................................................... 19
6.6 Electrical Characteristics for 2.5-V Supply ............... 6 12 Device and Documentation Support ................. 20
6.7 Electrical Characteristics for 2.1-V Supply................ 7 12.1 Device Support .................................................... 20
6.8 Electrical Characteristics for 1.8-V Supply................ 7 12.2 Documentation Support ....................................... 21
6.9 Switching Characteristics for 3.3-V Supply ............... 8 12.3 Receiving Notification of Documentation Updates 21
6.10 Switching Characteristics for 2.5-V Supply ............. 8 12.4 Community Resources.......................................... 21
6.11 Switching Characteristics for 1.8-V Supply ............. 9 12.5 Trademarks ........................................................... 21
6.12 Typical Characteristics .......................................... 10 12.6 Electrostatic Discharge Caution ............................ 21
7 Parameter Measurement Information ................ 13 12.7 Glossary ................................................................ 21
8 Detailed Description ............................................ 17 13 Mechanical, Packaging, and Orderable
Information ........................................................... 21

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (March 2015) to Revision H Page

• Changed the pinout images.................................................................................................................................................... 3

• Changed the ron MAX value at 25°C From: 8 Ω To: 17 Ω in the Electrical Characteristics for 1.8-V Supply table................ 7
• Changed the ron MAX value at Full From: 14.55 Ω To: 32 Ω in the Electrical Characteristics for 1.8-V Supply table........... 7

Changes from Revision F (June 2013) to Revision G Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Deleted Ordering Information table. ....................................................................................................................................... 1

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5 Pin Configuration and Functions

D, DBQ, DGV and PW Package

16-Pin SOIC, SSOP, TVSOP and TSSOP Logic Circuit
(Top View) 1 Logic 16
Control
2 15
IN 1 16 V+
3 14
NC1 2 15 EN
4 13
NO1 3 14 NC4
5 12
COM1 4 13 NO4
6 11
NC2 5 12 COM4

NO2 6 11 NC3 7 10

COM2 7 10 NO3 8 9

GND 8 9 COM3

Not to scale

RGY Package
16-Pin VQFN RSV Package
(Top View) 16-Pin UQFN
(Top View)
V+
IN

NC1

EN
V+
IN
1

16

16

15

14

13
NC1 2 15 EN
NO1 1 12 NC4
NO1 3 14 NC4

Thermal COM1 2 11 NO4

COM1 4 13 NO4
Pad
NC2 3 10 COM4
NC2 5 12 COM4
NO2 4 9 NC3
NO2 6 11 NC3

8
COM2 7 10 NO3
8

COM2

GND

COM3

NO3
Not to scale
Not to scale
GND

COM3

Pin Functions
PIN
SOIC, SSOP, TYPE DESCRIPTION
NAME TVSOP, VQFN UQFN NO.
NO.
COM1 4 2 I/O Common path for switch
COM2 7 5 I/O Common path for switch
COM3 9 7 I/O Common path for switch
COM4 12 10 I/O Common path for switch
EN 15 13 I Active-low switch enable input
GND 8 6 — Ground
IN 1 15 I Switch path selector input
NC1 2 16 I/O Normally closed path for switch
NC2 5 3 I/O Normally closed path for switch
NC3 11 9 I/O Normally closed path for switch
NC4 14 12 I/O Normally closed path for switch
NO1 3 1 I/O Normally open path for switch
NO2 6 4 I/O Normally open path for switch
NO3 10 8 I/O Normally open path for switch
NO4 13 11 I/O Normally open path for switch
V+ 16 14 — Supply voltage

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
V+ Supply voltage (3) –0.5 4.6 V
VNC
VNO Analog voltage (3) (4) –0.5 4.6 V
VCOM
IK Analog port diode current VNC, VNO, VCOM < 0 –50 mA
INC
INO ON-state switch current VNC, VNO, VCOM = 0 to 7 V –64 64 mA
ICOM
VI Digital input voltage (3) (4) –0.5 4.6 V
IIK Digital input clamp current VI < 0 –50 mA
I+ Continuous current through V+ –100 100 mA
IGND Continuous current through GND –100 100 mA
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(3) All voltages are with respect to ground, unless otherwise specified.
(4) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VI/O Switch input and output voltage 0 V+ V
V+ Supply voltage 1.65 3.6 V
VI Control input voltage 0 3.6 V
TA Operating temperature -40 85 °C

6.4 Thermal Information

TS3A5018
(1) D DBQ DGV PW RGY RSV
THERMAL METRIC UNIT
(SOIC) (SSOP) (TVSOP) (TSSOP) (VQFN) (UQFN)
16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 73 90 120 108 51 184 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics for 3.3-V Supply

V+ = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS TA V+ MIN TYP MAX UNIT
Analog
Switch
VCOM, VNO,
Analog signal range 0 V+ V
VNC

ON-state 0 ≤ (VNC or VNO) ≤ V+, Switch ON, 25°C 7 10

ron 3V Ω
resistance ICOM = –32 mA, see Figure 17 Full 12
ON-state 25°C 0.3 0.8
VNC or VNO = 2.1 V, Switch ON,
Δron resistance match between 3V Ω
ICOM = –32 mA, see Figure 17 Full 1
channels
ON-state 25°C 5 7
0 ≤ (VNC or VNO) ≤ V+, Switch ON,
ron(flat) resistance 3V Ω
ICOM = –32 mA, see Figure 17 Full 8
flatness
VNC or VNO = 1 V, 25°C –0.1 0.05 0.1
VCOM = 3 V,
Switch OFF,
or 3.6 V
see Figure 18 Full –0.2 0.2
VNC or VNO = 3 V,
VCOM = 1 V,
INC(OFF), NC, NO VNC or VNO = 0 to 3.6 25°C –2 0.05 2 µA
INO(OFF) OFF leakage current V,
VCOM = 3.6 V to 0,
Switch OFF,
or 0V
see Figure 18 Full –10 10
VNC or VNO = 3.6 V to
0,
VCOM = 0 to 3.6 V,
VCOM = 1 V, 25°C –0.1 0.05 0.1
VNC or VNO = 3 V,
Switch OFF,
or 3.6 V
see Figure 18 Full –0.2 0.2
VCOM = 3 V,
VNC or VNO = 3 V,
COM VCOM = 0 to 3.6 V, 25°C –2 0.05 2
ICOM(OFF) µA
OFF leakage current VNC or VNO = 3.6 V to
0,
Switch OFF,
or 0V
see Figure 18 Full –10 10
VCOM = 3.6 V to 0,
VNC or VNO = 0 to 3.6
V,
VNC or VNO = 1 V, 25°C –0.1 0.05 0.1
NC, NO VCOM = Open,
INC(ON), Switch ON,
ON leakage or 3.6 V µA
INO(ON) see Figure 19 Full –0.2 0.2
current VNC or VNO = 3 V,
VCOM = Open,
VCOM = 1 V, 25°C –0.1 0.05 0.1
COM VNC or VNO = Open,
Switch ON,
ICOM(ON) ON leakage or 3.6 V µA
see Figure 19 Full –0.2 0.2
current VCOM = 3 V,
VNC or VNO = Open,
VIH Input logic high Full 2 V+ V
VIL Input logic low Full 0 0.8 V
25°C –1 0.05 1
IIH, IIL Input leakage current VI = V+ or 0 3.6 V µA
Full –1 1
Charge VGEN = 0, CL = 0.1 nF,
QC 25°C 3.3 V 2 pC
injection RGEN = 0, see Figure 26
NC, NO
CNC(OFF), VNC or VNO = V+ or Switch OFF,
OFF 25°C 3.3 V 4.5 pF
CNO(OFF) GND, see Figure 20
capacitance
COM
Switch OFF,
CCOM(OFF) OFF VCOM = V+ or GND, 25°C 3.3 V 9 pF
see Figure 20
capacitance
NC, NO
CNC(ON), VNC or VNO = V+ or Switch ON,
ON 25°C 3.3 V 16 pF
CNO(ON) GND, see Figure 20
capacitance
COM
Switch ON,
CCOM(ON) ON VCOM = V+ or GND, 25°C 3.3 V 16 pF
see Figure 20
capacitance

(1) The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
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Electrical Characteristics for 3.3-V Supply (continued)

V+ = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS TA V+ MIN TYP MAX UNIT
Digital input
CI VI = V+ or GND, See Figure 20 25°C 3.3 V 3 pF
capacitance
Switch ON,
BW Bandwidth RL = 50 Ω, 25°C 3.3 V 300 MHz
see Figure 22
RL = 50 Ω, Switch OFF,
OISO OFF isolation 25°C 3.3 V –48 dB
f = 10 MHz, see Figure 23
RL = 50 Ω, Switch ON,
XTALK Crosstalk 25°C 3.3 V –48 dB
f = 10 MHz, see Figure 24
RL = 50 Ω, Switch ON,
XTALK(ADJ) Crosstalk adjacent 25°C 3.3 V –81 dB
f = 10 MHz, see Figure 25
f = 20 Hz to 20
RL = 600 Ω,
THD Total harmonic distortion kHz, 25°C 3.3 V 0.21%
CL = 50 pF,
see Figure 27
25°C 2.5 7
I+ Positive supply current VI = V+ or GND, Switch ON or OFF 3.6 V µA
Full 10

6.6 Electrical Characteristics for 2.5-V Supply

V+ = 2.3 V to 2.7 V, TA = –40°C to 85°C (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS TA V+ MIN TYP MAX UNIT
VCOM, VNC,
Analog signal range 0 V+ V
VNO

ON-state 0 ≤ (VNC or VNO) ≤ V+, Switch ON, 25°C 12 20

ron 2.3 V Ω
resistance ICOM = –24 mA, see Figure 17 Full 22
ON-state 25°C 0.3 1
VNC or VNO = 1.6 V, Switch ON,
Δron resistance match 2.3 V Ω
ICOM = –24 mA, see Figure 17 Full 2
between channels
ON-state 25°C 14 18
0 ≤ (VNC or VNO) ≤ V+, Switch ON,
ron(flat) resistance 2.3 V Ω
ICOM = –24 mA, see Figure 17 Full 20
flatness
VNC or VNO = 0.5 V, 25°C –0.1 0.05 0.1
VCOM = 2.2 V,
Switch OFF,
or 2.7 V
see Figure 18 Full –0.2 0.2
VNC or VNO = 2.2 V,
INC(OFF), NC, NO VCOM = 0.5 V,
µA
INO(OFF) OFF leakage current VNC or VNO = 0 to 3.6 V, 25°C –2 0.05 2
VCOM = 3.6 V to 0,
Switch OFF,
or 0V
see Figure 18 Full –10 10
VNC or VNO = 3.6 V to 0,
VCOM = 0 to 3.6 V,
VCOM = 0.5 V, 25°C –0.1 0.05 0.1
VNC or VNO = 2.2 V,
Switch OFF,
or 2.7 V
see Figure 18 Full –0.2 0.2
VCOM = 2.2 V,
COM VNC or VNO = 0.5 V,
ICOM(OFF) µA
OFF leakage current VCOM = 0 to 3.6 V, 25°C –2 0.05 2
VNC or VNO = 3.6 V to 0,
Switch OFF,
or 0V
see Figure 18 Full –10 10
VCOM = 3.6 V to 0,
VNC or VNO = 0 to 3.6 V,
VNC or VNO = 0.5 V, 25°C –0.1 0.05 0.1
NC, NO VCOM = Open,
INC(ON), Switch ON,
ON leakage or 2.7 V µA
INO(ON) see Figure 19 Full –0.2 0.2
current VNC or VNO = 2.2 V,
VCOM = Open,
VCOM = 0.5 V, 25°C –0.1 0.05 0.1
COM VNC or VNO = Open,
Switch ON,
ICOM(ON) ON leakage or 2.7 V µA
see Figure 19 Full –0.2 0.2
current VCOM = 2.2 V,
VNC or VNO = Open,
VIH Input logic high Full 1.7 V+ V
VIL Input logic low Full 0 0.7 V

(1) The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
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Electrical Characteristics for 2.5-V Supply (continued)

V+ = 2.3 V to 2.7 V, TA = –40°C to 85°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS TA V+ MIN TYP MAX UNIT
25°C –0.1 0.05 0.1
IIH, IIL Input leakage current VI = V+ or 0 2.7 V µA
Full –1 1
Charge VGEN = 0, CL = 0.1 nF,
QC 25°C 2.5 V 1 pC
injection RGEN = 0, see Figure 26
NC, NO
CNC(OFF), Switch OFF,
OFF VNC or VNO = V+ or GND, 25°C 2.5 V 3 pF
CNO(OFF) see Figure 20
capacitance
COM
Switch OFF,
CCOM(OFF) OFF VCOM = V+ or GND, 25°C 2.5 V 9 pF
see Figure 20
capacitance
NC, NO
CNC(ON), Switch ON,
ON VNC or VNO = V+ or GND, 25°C 2.5 V 16 pF
CNO(ON) see Figure 20
capacitance
COM
Switch ON,
CCOM(ON) ON VCOM = V+ or GND, 25°C 2.5 V 16 pF
see Figure 20
capacitance
Digital input
CI VI = V+ or GND, See Figure 20 25°C 2.5 V 3 pF
capacitance
Switch ON,
BW Bandwidth RL = 50 Ω, 25°C 2.5 V 300 MHz
see Figure 22
RL = 50 Ω, Switch OFF,
OISO OFF isolation 25°C 2.5 V –48 dB
f = 10 MHz, see Figure 23
RL = 50 Ω, Switch ON,
XTALK Crosstalk 25°C 2.5 V –48 dB
f = 10 MHz, see Figure 24
RL = 50 Ω, Switch ON,
XTALK(ADJ) Crosstalk adjacent 25°C 3.3 V –81 dB
f = 10 MHz, see Figure 25
Total harmonic RL = 600 Ω, f = 20 Hz to 20 kHz,
THD 25°C 2.5 V 0.33%
distortion CL = 50 pF, see Figure 27
25°C 2.5 7
I+ Positive supply current VI = V+ or GND, Switch ON or OFF 2.7 V µA
Full 10

6.7 Electrical Characteristics for 2.1-V Supply

V+ = 2.00 V to 2.20 V, TA = –40°C to 85°C (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS TA V+ MIN TYP MAX UNIT
VIH Input logic high Full 1.2 4.3 V
VIL Input logic low Full 0 0.5 V

(1) The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.

6.8 Electrical Characteristics for 1.8-V Supply

V+ = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS TA V+ MIN TYP MAX UNIT
Analog signal
VCOM, VNC, VNO 0 V+ V
range

ON-state 0 ≤ (VNC or VNO) ≤ V+, Switch ON, 25°C 5.5 17

ron 1.65 V Ω
resistance ICOM = –32 mA, see Figure 17 Full 32
ON-state 25°C 0.3 1
resistance match VNC or VNO = 1.5 V, Switch ON,
Δron 1.65 V Ω
between ICOM = –32 mA, see Figure 17 Full 1.2
channels
ON-state 25°C 2.7 5.5
0 ≤ (VNC or VNO) ≤ V+, Switch ON,
ron(flat) resistance 1.65 V Ω
ICOM = –32 mA, see Figure 17 Full 7.3
flatness

(1) The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
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Electrical Characteristics for 1.8-V Supply (continued)

V+ = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS TA V+ MIN TYP MAX UNIT
VNC or VNO = 0.3 V, 25°C –0.25 0.03 0.25
VCOM = 1.65V,
Switch OFF,
or 1.95 V
see Figure 18 Full –4.5 4.5
VNC or VNO = 1.65V,
NC, NO VCOM = 0.3 V,
INC(OFF),
OFF leakage µA
INO(OFF) VNC or VNO = 1.95 V to 0 V, 25°C –0.4 0.01 0.4
current
VCOM = 0 V to 1.95 V,
Switch OFF,
or 0V
see Figure 18 Full –6.5 6.5
VNC or VNO = 0 V to 1.95 V,
VCOM = 1.95 V to 0 V,
VCOM = 1.65 V, 25°C –0.4 0.02 0.4
VNC or VNO = 0.3V,
Switch OFF,
or 1.95 V
see Figure 18 Full –0.9 0.9
VCOM = 0.3 V,
COM VNC or VNO = 1.65V,
ICOM(OFF) OFF leakage µA
current VCOM = 0 V to 1.95 V, 25°C –0.4 0.02 0.4
VNC or VNO = 1.95 V to 0 V,
Switch OFF,
or 0V
see Figure 18 Full –4.5 4.5
VCOM = 1.95 V to 0,
VNC or VNO = 0 to 1.95 V,
VNC or VNO = 0.3 V, 25°C –2. 0.02 2
NC, NO VCOM = Open,
INC(ON), Switch ON,
ON leakage or 1.95 V µA
INO(ON) see Figure 19 Full –2 0.02 2
current VNC or VNO = 1.65 V,
VCOM = Open,
VCOM = 0.3 V, 25°C –4.5 4.5
COM VNC or VNO = Open,
Switch ON,
ICOM(ON) ON leakage or 1.95 V µA
see Figure 19 Full
current VCOM = 1.65 V,
VNC or VNO = Open,
VIH Input logic high VI = V+ or GND Full 1.95 V 1 3.6 V
VIL Input logic low Full 1.95 V 0 0.4 V

Input leakage 25°C –0.1 0.01 0.1

IIH, IIL VI = V+ or 0 1.95 V µA
current Full –2.1 2.1

6.9 Switching Characteristics for 3.3-V Supply

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS TA V+ MIN TYP MAX UNIT
25°C 3.3 V 2.5 3.5 8
VCOM = 2 V, CL = 35 pF,
tON Turnon time 3 V to ns
RL = 300 Ω, see Figure 21 Full 2.5 9
3.6 V
25°C 3.3 V 0.5 2 6.5
VCOM =2 V, CL = 35 pF,
tOFF Turnoff time 3 V to ns
RL = 300 Ω, see Figure 21 Full 0.5 7
3.6 V

6.10 Switching Characteristics for 2.5-V Supply

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS TA V+ MIN TYP MAX UNIT
25°C 2.5 V 2.5 5 9.5
VCOM = 1.5 V, CL = 35 pF,
tON Turnon time 2.3 V to ns
RL = 300 Ω, see Figure 21 Full 2.5 10.5
2.7 V
25°C 2.5 V 0.5 3 7.5
VCOM =1.5 V, CL = 35 pF,
tOFF Turnoff time 2.3 V to ns
RL = 300 Ω, see Figure 21 Full 0.5 9
2.7 V

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6.11 Switching Characteristics for 1.8-V Supply

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS TA V+ MIN TYP MAX UNIT
25°C 1.8 V 14.1 49.3
VCOM = V+, CL = 35 pF, 1.65 V
tON Turnon time ns
RL = 50 Ω, see Figure 21 Full to 49.3 56.7
1.95 V
25°C 1.8 V 16.1 26.5
VCOM = V+, CL = 35 pF, 1.65 V
tOFF Turnoff time ns
RL = 50 Ω, see Figure 21 Full to 31.2
1.95 V
25°C 1.8 V 5.3 18.4 58
Break-before- VNC = VNO = V+/2, CL = 35 pF, 1.65 V
tBBM ns
make time RL = 50 Ω, see Figure 21 Full to 58
1.95 V

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6.12 Typical Characteristics

18 10
16 TA = 25°C
14 V+ = 2.5 V 8
855C
12
255C
6
ron (Ω)

10

ron (W)
8
6 4

4 V+ = 3.3 V –405C
2 2

0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0
VCOM (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCOM (V)

Figure 1. ron vs VCOM (V+ = 3.3 V) Figure 2. ron vs VCOM (V+ = 2.5 V)
40 40
INC_ON
35 INO_ON
INC(ON) ICOM_ON
30
Leakage Current (nA)

Leakage Current (nA) 30 INC_OFF

ICOM(ON)
INO_OFF
25 ICOM_OFF
20 20
INC(OFF)
ICOM(OFF) 15
INO(ON)
10
10
INO(OFF) 5
0
−60 −40 −20 0 20 40 60 80 100 0
−60 −40 −20 0 20 40 60 80 100
TA (°C) Temperature (°C) G005

Figure 3. Leakage Current vs Temperature (V+ = 3.6 V) Figure 4. Leakage Current vs Temperature (V+ = 1.8 V)
5 0.6
0.5

0.4
4
0.3
Charge Injection (pC)

Charge Injection - pC

V+ = 3.3 V 0.2
3
0.1
0.0
2 -0.1

-0.2
V+ = 2.5 V
1 -0.3
-0.4

0 -0.5
0 1 2 3 4 -0.6
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VCOM (V) VCOM - V

Figure 5. Charge Injection (QC) vs VCOM Figure 6. Charge Injection (QC) vs VCOM (V+ = 1.8 V)

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Typical Characteristics (continued)

7 8
tON
6 7 tON

6
5
5 tOFF
tOFF

tON/tOFF (ns)
4
tON/tOFF (ns)

4
3
3
2 2

1 1

0
0
2.0 2.5 3.0 3.5 4.0 −40 25 85

V+ (V) TA (5C)

Figure 7. tON and tOFF vs Supply Voltage Figure 8. tON and tOFF vs Temperature (V+ = 3.3 V)
1.8 0
TA = 25°C
1.6
−1
Logic Level Threshold (V)

1.4
−2
1.2
−3
Gain (dB)

1
0.8 −4
0.6
−5
0.4
VIH −6
0.2
VIL
0 −7
1.65 1.85 2.05 2.25 2.45 2.65 2.85 3.05 3.25 3.45 3.6 1 10 100 1K
V+ (V) G001 Frequency (MHz)

Figure 9. Logic-Level Threshold vs V+ Figure 10. Gain vs Frequency Bandwidth (V+ = 3.3 V)
0 0

-10 -10

-20
-20
-30
-30
-40
Gain - dB

Gain - dB

-40 -50

-50 -60

-70
-60
-80
-70
-90
-80 -100
-90 -110
1 10 100 1000 1 10 100 1000
f - Frequency - MHz f - Frequency - MHz

Figure 11. OFF Isolation vs Frequency (V+ = 1.8 V) Figure 12. Crosstalk Adjacent vs Frequency (V+ = 1.8 V)

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Typical Characteristics (continued)

0 0
-10 −10

-20
−20
−30
-30
−40
Gain - dB

Gain (dB)
-40
−50
-50
−60
-60 −70
-70 −80

-80 −90
1 10 100 1k
-90 Frequency (MHz)
1 10 100 1000
f - Frequency - MHz

Figure 13. Crosstalk vs Frequency (V+ = 1.8 V) Figure 14. OFF Isolation vs Frequency
(V+ = 3.3 V)
0.45 4.0
0.40 3.5
0.35 3.0
0.30 2.5
0.25 2.0
THD (%)

I+ (µA)

0.20 1.5
0.15
1.0
0.10
0.5
0.05
0.0
0.00 −40 25 85
10 100 1000 10 K 100 K
Frequency (MHz) TA (5C)

Figure 15. Total Harmonic Distortion vs Frequency Figure 16. Power-Supply Current vs Temperature
(V+ = 3.3 V)

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7 Parameter Measurement Information

V+

VNC NC
COM VCOM
+
VNO NO Channel ON
VCOM – VNO or VNC
r on = Ω
IN or EN I COM
VI ICOM
VI = VIH or VIL
+

GND

Figure 17. ON-State Resistance (ron)

V+

VNC NC
OFF-State Leakage Current
COM VCOM
+ Channel OFF
VNO NO +
VI = VIH or VIL
VNC or VNO = 0 to V+
IN or EN and
VI VCOM =V+ to 0
+

GND

Figure 18. OFF-State Leakage Current (ICOM(OFF), INC(OFF), INO(OFF))

V+

VNC NC
COM
+ VCOM
VNO NO ON-State Leakage Current
Channel ON
IN or EN VI = VIH or VIL
VI
+

GND

Figure 19. ON-State Leakage Current (ICOM(ON), INC(ON))

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Parameter Measurement Information (continued)

V+

VNC NC
Capacitance
Meter VBIAS = V+ or GND
VNO NO
VI = VIH or VIL
VCOM COM
VBIAS Capacitance is measured at NC,
VI NO, COM, and IN inputs during
ON and OFF conditions.
IN or EN
GND

Figure 20. Capacitance (CI, CCOM(OFF), CCOM(ON), CNC(OFF), CNC(ON))

V+

TEST RL CL
NC or NO VNC or VNO
tON 300 Ω 35 pF
VCOM (3) COM
NC or NO CL(2) RL
CL(2) tOFF 300 Ω 35 pF

RL

VI Logic V+
Input 50% 50%
Logic IN or EN
GND (VI) 0
Input(1)
tON tOFF
Switch
Output 90% 90%
(VNC)
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns,
tf < 5 ns.
(2) CL includes probe and jig capacitance.
(3) See Electrical Characteristics for VCOM.

Figure 21. Turnon (tON) and Turnoff Time (tOFF)

V+
Network Analyzer

50 Ω VNC NC Channel ON: NC to COM

COM VCOM VI = V+ or GND
Source
Signal VNO NO

Network Analyzer Setup

IN or EN
50 Ω VI Source Power = 0 dBm
+ (632-mV P-P at 50- Ω load)
GND
DC Bias = 350 mV

Figure 22. Bandwidth (BW)

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Parameter Measurement Information (continued)

V+
Network Analyzer

Channel OFF: NC to COM

50 Ω VNC NC
VI = V+ or GND
COM VCOM
Source
50 VNO NO
Signal Network Analyzer Setup
IN or EN
VI Source Power = 0 dBm
50 Ω (632-mV P-P at 50- Ω load)
+ GND
DC Bias = 350 mV

Figure 23. OFF Isolation (OISO)

V+
Network Analyzer
Channel ON: NC to COM
50 Ω VNC NC Channel OFF: NO to COM
VCOM VI = V+ or GND
Source
VNO NO
Signal
IN or EN 50 Ω Network Analyzer Setup
VI
50 Ω + Source Power = 0 dBm
GND (632-mV P-P at 50- Ω load)
DC Bias = 350 mV

Figure 24. Crosstalk (XTALK)

V+
Network Analyzer

50 Ω VNC1
NC1 Channel ON: NC to COM
COM1
Source
VNC2 NC2
Signal Network Analyzer Setup
50 Ω
COM2
IN or EN
Source Power = 0 dBm
50 Ω VI
(632 mV P-P at 50 Ω load)
+
GND DC Bias = 350 mV

Figure 25. Crosstalk Adjacent

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Parameter Measurement Information (continued)

V+ Logic VIH
Input
OFF ON OFF V
(VI ) IL
RGEN
NC or NO
COM VCOM
+ VCOM ΔVCOM
VGEN NC or NO
CL(1)
IN or EN
VI VGEN = 0 to V+
RGEN = 0
CL = 0.1 nF
Logic
Input(2) GND QC = CL × ΔVCOM
VI = VIH or VIL

(1) CL includes probe and jig capacitance.

(2) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns,
tf < 5 ns.

Figure 26. Charge Injection (QC)

Channel ON: COM to NC VI = VIH or VIL

VSOURCE = V+ P-P fSOURCE = 20 Hz to 20 kHz
V+/2
V+
Audio Analyzer
RL
10 µ F
NC
10 µ F
Source
COM
Signal
600 Ω CL(1)
600 Ω IN or EN NO
VI
+
GND
600 Ω

(1) CL includes probe and jig capacitance.

Figure 27. Total Harmonic Distortion (THD)

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8 Detailed Description

8.1 Overview
The TS3A5018 is a quad single-pole-double-throw (SPDT) solid-state analog switch. The TS3A5018, like all
analog switches, is bidirectional. When powered on, each COM pin is connected to its respective NC pin. For this
device, NC stands for normally closed and NO stands for normally open. The switch is enabled when EN is low.
If IN is also low, COM is connected to NC. If IN is high, COM is connected to NO.
The TS3A5018 is a break-before-make switch. This means that during switching, a connection is broken before a
new connection is established. The NC and NO pins are never connected to each other.

8.2 Functional Block Diagram (Each Switch)

EN

IN

COM NC

NO

8.3 Feature Description

The low ON-state resistance, ON-state resistance matching, and charge injection in the TS3A5018 make this
switch an excellent choice for analog signals that require minimal distortion. In addition, the low THD allows
audio signals to be preserved more clearly as they pass through the device.
The 1.8-V to 3.6-V operation allows compatibility with more logic levels, and the bidirectional I/Os can pass
analog signals from 0 V to V+ with low distortion.

8.4 Device Functional Modes

Table 1. Function Table

NO TO COM, NC TO COM,
EN IN
COM TO NO COM TO NC
L L OFF ON
L H ON OFF
H X OFF OFF

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TS3A5018 can be used in a variety of customer systems. The TS3A5018 can be used anywhere multiple
analog or digital signals must be selected to pass across a single line.

9.2 Typical Application

1.8 V

V+
NO1
EN To/From
System
NC1
IN

C or System
Logic COM1
NO4
To/From
System
COM4 NC4
GND

Figure 28. System Schematic for TS3A5018

9.2.1 Design Requirements

In this particular application, V+ was 1.8 V, although V+ is allowed to be any voltage specified in Recommended
Operating Conditions. A decoupling capacitor is recommended on the V+ pin. See Power Supply
Recommendations for more details.

9.2.2 Detailed Design Procedure

In this application, EN and IN are, by default, pulled low to GND. Choose these resistor sizes based on the
current driving strength of the GPIO, the desired power consumption, and the switching frequency (if applicable).
If the GPIO is open-drain, use pullup resistors instead.

9.2.3 Application Curve

0

-1

-2

-3

-4
Gain - dB

-5

-6

-7

-8

-9

-10
1 10 100 1000
f - Frequency - MHz

Figure 29. Gain vs Frequency Bandwidth (V+ = 1.8 V)

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.

11 Layout

11.1 Layout Guidelines

Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and so they will have to
turn corners. Figure 30 shows progressively better techniques of rounding corners. Only the last example
maintains constant trace width and minimizes reflections.
Unused switch I/Os, such as NO, NC, and COM, can be left floating or tied to GND. However, the IN and EN
pins must be driven high or low. Due to partial transistor turnon when control inputs are at threshold levels,
floating control inputs can cause increased ICC or unknown switch selection states.

11.2 Layout Example

WORST BETTER BEST
2W

1W min.

W
Figure 30. Trace Example

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Device Nomenclature

Table 2. Parameter Description

SYMBOL DESCRIPTION
VCOM Voltage at COM
VNC Voltage at NC
VNO Voltage at NO
ron Resistance between COM and NC or NO ports when the channel is ON
Δron Difference of ron between channels in a specific device
ron(flat) Difference between the maximum and minimum value of ron in a channel over the specified range of conditions
INC(OFF) Leakage current measured at the NC port, with the corresponding channel (NC to COM) in the OFF state
Leakage current measured at the NC port, with the corresponding channel (NC to COM) in the ON state and the output
INC(ON)
(COM) open
INO(OFF) Leakage current measured at the NO port, with the corresponding channel (NO to COM) in the OFF state
Leakage current measured at the NO port, with the corresponding channel (NO to COM) in the ON state and the output
INO(ON)
(COM) open
ICOM(OFF) Leakage current measured at the COM port, with the corresponding channel (COM to NC or NO) in the OFF state
Leakage current measured at the COM port, with the corresponding channel (COM to NC or NO) in the ON state and the
ICOM(ON)
output (NC or NO) open
VIH Minimum input voltage for logic high for the control input (IN, EN)
VIL Maximum input voltage for logic low for the control input (IN, EN)
VI Voltage at the control input (IN, EN)
IIH, IIL Leakage current measured at the control input (IN, EN)
Turnon time for the switch. This parameter is measured under the specified range of conditions and by the propagation
tON
delay between the digital control (IN) signal and analog output NC or NO) signal when the switch is turning ON.
Turnoff time for the switch. This parameter is measured under the specified range of conditions and by the propagation
tOFF
delay between the digital control (IN) signal and analog output (NC or NO) signal when the switch is turning OFF.
Charge injection is a measurement of unwanted signal coupling from the control (IN) input to the analog (NC or NO)
QC output. This is measured in coulomb (C) and measured by the total charge induced due to switching of the control input.
Charge injection, QC = CL × ΔVCOM, CL is the load capacitance and ΔVCOM is the change in analog output voltage.
CNC(OFF) Capacitance at the NC port when the corresponding channel (NC to COM) is OFF
CNC(ON) Capacitance at the NC port when the corresponding channel (NC to COM) is ON
CNO(OFF) Capacitance at the NC port when the corresponding channel (NO to COM) is OFF
CNO(ON) Capacitance at the NC port when the corresponding channel (NO to COM) is ON
CCOM(OFF) Capacitance at the COM port when the corresponding channel (COM to NC) is OFF
CCOM(ON) Capacitance at the COM port when the corresponding channel (COM to NC) is ON
CI Capacitance of control input (IN, EN)
OFF isolation of the switch is a measurement of OFF-state switch impedance. This is measured in dB in a specific
OISO
frequency, with the corresponding channel (NC to COM) in the OFF state.
Crosstalk is a measurement of unwanted signal coupling from an ON channel to an OFF channel (NC1 to NO1). Adjacent
XTALK crosstalk is a measure of unwanted signal coupling from an ON channel to an adjacent ON channel (NC1 to NC2) .This is
measured in a specific frequency and in dB.
BW Bandwidth of the switch. This is the frequency in which the gain of an ON channel is –3 dB below the DC gain.
Total harmonic distortion describes the signal distortion caused by the analog switch. This is defined as the ratio of root
THD mean square (RMS) value of the second, third, and higher harmonic to the absolute magnitude of the fundamental
harmonic.
I+ Static power-supply current with the control (IN) pin at V+ or GND

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12.2 Documentation Support

12.2.1 Related Documentation
For related documentation, see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on [Link]. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At [Link], you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TS3A5018D Obsolete Production SOIC (D) | 16 - - Call TI Call TI -40 to 85 TS3A5018

TS3A5018DBQR Active Production SSOP (DBQ) | 16 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 YA018
TS3A5018DBQR.B Active Production SSOP (DBQ) | 16 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 YA018
TS3A5018DGVR Active Production TVSOP (DGV) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 YA018
TS3A5018DGVR.B Active Production TVSOP (DGV) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 YA018
TS3A5018DGVRG4 Active Production TVSOP (DGV) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 YA018
TS3A5018DGVRG4.B Active Production TVSOP (DGV) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 YA018
TS3A5018DR Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TS3A5018
TS3A5018DR.B Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TS3A5018
TS3A5018DRG4 Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TS3A5018
TS3A5018DRG4.B Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TS3A5018
TS3A5018PW Obsolete Production TSSOP (PW) | 16 - - Call TI Call TI -40 to 85 YA018
TS3A5018PWR Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 YA018
TS3A5018PWR.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 YA018
TS3A5018RGYR Active Production VQFN (RGY) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 YA018
TS3A5018RGYR.B Active Production VQFN (RGY) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 YA018
TS3A5018RGYRG4 Active Production VQFN (RGY) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 YA018
TS3A5018RGYRG4.B Active Production VQFN (RGY) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 YA018
TS3A5018RSVR Active Production UQFN (RSV) | 16 3000 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 ZUN
TS3A5018RSVR.B Active Production UQFN (RSV) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 ZUN

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 23-Jul-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS3A5018DBQR SSOP DBQ 16 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1
TS3A5018DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
TS3A5018DGVRG4 TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
TS3A5018DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TS3A5018DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TS3A5018PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TS3A5018RGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1
TS3A5018RGYRG4 VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1
TS3A5018RSVR UQFN RSV 16 3000 180.0 13.2 2.1 2.9 0.75 4.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 23-Jul-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TS3A5018DBQR SSOP DBQ 16 2500 353.0 353.0 32.0
TS3A5018DGVR TVSOP DGV 16 2000 353.0 353.0 32.0
TS3A5018DGVRG4 TVSOP DGV 16 2000 353.0 353.0 32.0
TS3A5018DR SOIC D 16 2500 353.0 353.0 32.0
TS3A5018DRG4 SOIC D 16 2500 353.0 353.0 32.0
TS3A5018PWR TSSOP PW 16 2000 353.0 353.0 32.0
TS3A5018RGYR VQFN RGY 16 3000 353.0 353.0 32.0
TS3A5018RGYRG4 VQFN RGY 16 3000 353.0 353.0 32.0
TS3A5018RSVR UQFN RSV 16 3000 184.0 184.0 19.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RSV 16 UQFN - 0.55 mm max height
1.8 x 2.6, 0.4 mm pitch ULTRA THIN QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4231225/A

[Link]
 PACKAGE OUTLINE
RSV0016A SCALE 5.000
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD

1.85
B A
1.75

PIN 1 INDEX AREA

2.65
2.55

0.55 C
0.45
SEATING PLANE

0.05 0.05 C
0.00

2X 1.2

SYMM (0.13) TYP

5 ℄ 8
0.45
15X
0.35

4
9

SYMM
2X 1.2 ℄

12X 0.4

1 0.25
12 16X
0.15
0.07 C A B
0.05
16 13
0.55
0.45 PIN 1 ID
(45° X 0.1)

4220314/C 02/2020
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

[Link]
 EXAMPLE BOARD LAYOUT
RSV0016A UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD

SYMM
(0.7) ℄

16 13 SEE SOLDER MASK

DETAIL

16X (0.2) 1 12

SYMM
12X (0.4) ℄ (2.4)

(R0.05) TYP 4 9

15X (0.6)

5 8
(1.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 25X

0.05 MIN
0.05 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK

EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK

OPENING METAL OPENING

NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4220314/C 02/2020
NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 ([Link]/lit/slua271).

[Link]
 EXAMPLE STENCIL DESIGN
RSV0016A UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD

(0.7)
16 13

16X (0.2) 1 12

SYMM
12X (0.4) ℄ (2.4)

(R0.05) TYP
4 9

15X (0.6)

5 8
SYMM
℄

(1.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE: 25X

4220314/C 02/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

[Link]
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

4X (0 -12 )

8
9
0.30
4.5 16X 1.2 MAX
B 0.17
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

[Link]
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/B 12/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/B 12/2023
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
DBQ0016A SCALE 2.800
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

SEATING PLANE

.228-.244 TYP
[5.80-6.19] .004 [0.1] C
A PIN 1 ID AREA
14X .0250
[0.635]
16
1

2X
.189-.197
[4.81-5.00] .175
NOTE 3 [4.45]

8
9
16X .008-.012
B .150-.157 [0.21-0.30] .069 MAX
[3.81-3.98] [1.75]
NOTE 4 .007 [0.17] C A B

.005-.010 TYP
[0.13-0.25]

SEE DETAIL A

.010
[0.25]
GAGE PLANE

.004-.010
0 -8 [0.11-0.25]
.016-.035
[0.41-0.88] DETAIL A
(.041 ) TYPICAL
[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.

[Link]
 EXAMPLE BOARD LAYOUT
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6] SEE
SYMM
DETAILS
1
16

16X (.016 )
[0.41]

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL
OPENING OPENING

.002 MAX .002 MIN

[0.05] [0.05]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6]
SYMM
1
16

16X (.016 )
[0.41]
SYMM

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X

4214846/A 03/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
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Last updated 10/2025