PERI INSTITUTE OF TECHNOLOGY

Mannivakkam,Chennai-600048

(Affiliated to ANNA

UNIVERSITY,Chennai)

EC3352-DIGITAL SYSTEM DESIGN

LAB MASTER MANUAL
NAME:…………………………………………………………………

REGISTER NO:

………………………………………………………… YEAR/SEM:

……………………………………………………………

DEPARTMENT:……………………………………………………….

SUBJECT:………………………………………………………………
 Mannivakkam, Chennai-600 048.

BONAFIDE CERTIFICATE
This is a bonafide certificate of the practical work done by

Mr./Ms. …………………………………… Register No……………..…………

of .............................................................................................. department

..……. Year / …..… Semester during the academic year …….…………….

in the .................................................................................. laboratory.

Staff In-Charge Head of the Department

Submitted for Practical Examination held on ……………………......………………….

Internal Examiner External Examiner

 INDEX

EXP. DATE NAME OF THE EXPERIMENT PAGE MARKS SIGNATURE

NO NO

3
 EC3352 – DIGITAL SYSTEMS DESIGN LABORATORY
LIST OF EXPERIMENTS
(Regulation 2021)
LIST OF EXPERIMENTS:
1. Verification of Boolean Theorems using basic gates.
2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implement Half/Full Adder and Subtractor.
4 .Design and implement combinational circuits using MSI devices:
 4 – bit binary adder / subtractor
 Magnitude Comparator
 Application using multiplexers
5. Design and implement shift-registers.
6. Design and implement synchronous counters.
7. Design and implement asynchronous counters.

4
Ex. No.:
Date: STUDY OF LOGIC GATES

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:
SL No. COMPONENT SPECIFICATION QTY
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1

THEORY:

Circuit that takes the logical decision and the process are called logic gates.
Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low
level when any one of the inputs is low.

5
OR GATE:

The OR gate performs a logical addition commonly known as OR

function. The output is high when any one of the inputs is high. The output is low
level when both the inputs are low.

NOT GATE:

The NOT gate is called an inverter. The output is high when the input is
low. The output is low when the input is high.

NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when

both inputs are low and any one of the input is low .The output is low level when
both inputs are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both
inputs are low. The output is low when one or both inputs are high.

X-OR GATE:

The output is high when any one of the inputs is high. The output is
low when both the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.

6
(ii) Logical inputs are given as per circuit
diagram. (iii) Observe the output and verify the
truth table.

7
AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:

7
NOT GATE:

SYMBOL: PIN DIAGRAM:

X-OR GATE :

SYMBOL : PIN DIAGRAM :

8
2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

9
NOR GATE:

Program Output& Viva Total

(3) Result (4) (10)
(3)

RESULT:

10
11
12
13
14
15
16
17
18
Procedure:
1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and
ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.

Program Output& Viva Total

(3) Result (4) (10)
(3)

RESULT:

19
Ex. No.:
Date: DESIGN OF ADDER AND SUBTRACTOR
AIM:
To design and construct half adder, full adder, half subtractor and full
subtractor circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:

[Link]. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. IC TRAINER KIT - 1

THEORY:

HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one
from the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position.
Above circuit is called as a carry signal from the addition of the less significant
bits sum from the X-OR Gate the carry out from the AND gate.
FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input;
it consists of three inputs and two outputs. A full adder is useful to add three bits at
a time but a half adder cannot do so. In full adder sum output will be taken from X-
OR Gate, carry output will be taken from OR Gate.

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HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half
subtractor has two input and two outputs. The outputs are difference and borrow.
The difference can be applied using X-OR Gate, borrow output can be implemented
using an AND Gate and an inverter.

FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a

full subtractor the logic circuit should have three inputs and two outputs. The two
half subtractor put together gives a full subtractor .The first half subtractor will be
C and A B. The output will be difference output of full subtractor. The expression
AB assembles the borrow output of the half subtractor and the second term is
the inverted difference output of first X-OR.

HALF ADDER

TRUTH TABLE:

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

21
K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:

FULL ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

22
K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY:

CARRY = AB + BC + AC

LOGIC DIAGRAM:
FULL ADDER USING TWO HALF ADDER

23
HALF SUBTRACTOR

TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

K-Map for BORROW:

BORROW = A’B

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LOGIC DIAGRAM:

FULL SUBTRACTOR

TRUTH TABLE:
A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference:

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 Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow:

Borrow = A’B + BC + A’C

LOGIC DIAGRAM:
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

PROCEDURE:
1. Test the individual ICs with its specified verificat ion table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and
ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.

26
 5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.

Program Output& Viva Total

(3) Result (4) (10)
(3)

RESULT:

27
Ex. No.:
Date: DESIGN AND IMPLEMENTATION OF CODE CONVERTER

AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
[Link]. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1

THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion
circuit must be inserted between the two systems if each uses different codes for
same information. Thus, code converter is a circuit that makes the two systems
compatible even though each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code
uses four bits to represent a decimal digit. There are four inputs and four outputs.
Gray code is a non-weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables
are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output
variable.

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 A code converter is a circuit that makes the two systems compatible even
though each uses a different binary code. Each one of the four maps represents one
of the four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean
expressions derived by the maps. These are various other possibilities for a logic
diagram that implements this circuit. Now the OR gate whose output is C+D has
been used to implement partially each of three outputs.
BINARY TO GRAY CODE CONVERTOR

TRUTH TABLE:
| Binary input | Gray code output |
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

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K-Map for G3:

G3 = B 3
K-Map for G2:

K-Map for G1:

30
K-Map for G0:

LOGIC DIAGRAM:

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GRAY CODE TO BINARY CONVERTOR
TRUTH TABLE:

| Gray Code | Binary Code |

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

K-Map for B3:

B3 = G3

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K-Map for B2:

K-Map for B1:

33
K-Map for B0:

LOGIC DIAGRAM:

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BCD TO EXCESS-3 CONVERTOR
TRUTH TABLE:
| BCD input | Excess – 3 output |
B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

K-Map for E3:

E3 = B3 + B2 (B0 + B1)

35
K-Map for E2:

K-Map for E1:

36
K-Map for E0:

LOGIC DIAGRAM:

37
PROCEDURE:

1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and
ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.

Program Output& Viva Total

(3) Result (4) (10)
(3)

RESULT:

38
Ex. No.:
Date: DESIGN OF 4-BIT ADDER AND SUBTRACTOR

AIM:
To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:
[Link]. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two
binary numbers. It can be constructed with full adders connected in cascade, with
the output carry from each full adder connected to the input carry of next full adder
in chain. The augends bits of ‘A’ and the addend bits of ‘B’ are designated by
subscript numbers from right to left, with subscript 0 denoting the least significant
bits. The carries are connected in chain through the full adder. The input carry to
the adder is C0 and it ripples through the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The input
carry C0 must be equal to 1 when performing subtraction.

39
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with
one common binary adder. The mode input M controls the operation. When M=0,
the circuit is adder circuit. When M=1, it becomes subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with
an input carry from a previous stage. Since each input digit does not exceed 9, the
output sum cannot be greater than 19, the 1 in the sum being an input carry. The
output of two decimal digits must be represented in BCD and should appear in the
form listed in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2
decimal digits, together with the input carry, are first added in the top 4 bit adder to
produce the binary sum.

PIN DIAGRAM FOR IC 7483:

40
LOGIC DIAGRAM:
4-BIT BINARY ADDER

Addition CE=0

LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR

Subtraction CE=1
41
LOGIC DIAGRAM:
4-BIT BINARY ADDER/SUBTRACTOR

TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0

1 0 1 0 1 0 1 1 1 0 1 0 1 1 0 0 0 1

0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1

1 1 1 1 0 1 1 1 1 0 1 1 0 0 1 0 0 0

0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 0 0

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LOGIC DIAGRAM:
BCD ADDER

43
TRUTH TABLE:
BCD SUM CARRY
S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

PROCEDURE:

1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and
ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.

Program Output& Viva Total

(3) Result (4) (10)
(3)

RESULT:

44
Ex. No.: DESIGN AND IMPLEMENTATION OF MAGNITUDE
COMPARATOR
Date:

AIM:
To design and implement
(i) 2 – bit magnitude comparator using basic gates.
(ii) 8 – bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:

[Link]. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1

THEORY:

The comparison of two numbers is an operator that determine one number is

greater than, less than (or) equal to the other number. A magnitude comparator is a
combinational circuit that compares two numbers A and B and determine their
relative magnitude. The outcome of the comparator is specified by three binary
variables that indicate whether A>B, A=B (or) A<B.

45
 A = A3 A2 A1 A0
B = B3 B2 B1 B0

The equality of the two numbers and B is displayed in a combinational

circuit designated by the symbol (A=B).

This indicates A greater than B, then inspect the relative magnitude of pairs
of significant digits starting from most significant position. A is 0 and that of B is 0.

We have A<B, the sequential comparison can be expanded as

A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01

A<B = A31B3 + X3A21 B2 + X3X2A11 B1 + X3X2X1A01 B0

The same circuit can be used to compare the relative magnitude of two BCD
digits.
Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)

   
x3 x2 x1 x0

46
TRUTH TABLE

A1 A0 B1 B0 A>B A=B A<B

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

2 BIT MAGNITUDE COMPARATOR

K MAP

47
48
LOGIC DIAGRAM:

49
PIN DIAGRAM FOR IC 7485:

50
LOGIC DIAGRAM:
8 BIT MAGNITUDE COMPARATOR

TRUTH TABLE:

A B A>B A=B A<B

0000 0000 0000 0000 0 1 0
0001 0001 0000 0000 1 0 0
0000 0000 0001 0001 0 0 1

PROCEDURE:

1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and
ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.

Program Output& Viva Total

(3) Result (4) (10)
(3)

RESULT:

51
Ex. No.: DESIGN AND IMPLEMENTATION OF MULTIPLEXER
Date: AND DEMULTIPLEXER

AIM:
To design and implement multiplexer and demultiplexer using logic gates
and study of IC 74150 and IC 74154.

APPARATUS REQUIRED:
[Link]. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational
circuit that selects binary information from one of many input lines and directs
it to a single output line. The selection of a particular input line is controlled by a
set of selection lines. Normally there are 2n input line and n selection lines whose
bit combination determine which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For
this reason, the demultiplexer is also known as a data distributor. Decoder can also
be used as demultiplexer.

52
 In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND
gates. The data select lines enable only one gate at a time and the data on the data
input line will pass through the selected gate to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

53
CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

54
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

55
LOGIC DIAGRAM FOR DEMULTIPLEXER:

56
TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74150:

57
PIN DIAGRAM FOR IC 74154:

PROCEDURE:

1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and
ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.

Program Output& Viva Total

(3) Result (4) (10)
(3)

RESULT:

58
Ex. No.: DESIGN AND IMPLEMENTATION OF SHIFT REGISTER
Date:
AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:
[Link]. COMPONENT SPECIFICATION QTY.
1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:

A register is capable of shifting its binary information in one or both

directions is known as shift register. The logical configuration of shift register
consist of a D-Flip flop cascaded with output of one flip flop connected to input of
next flip flop. All flip flops receive common clock pulses which causes the shift in
the output of the flip flop. The simplest possible shift register is one that
uses only flip flop. The output of a given flip flop is connected to the input of next
flip flop of the register. Each clock pulse shifts the content of register one bit
position to right.

59
PIN DIAGRAM:

LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK Serial in Serial out

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

60
LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:

TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

61
TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

TRUTH TABLE:
DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
PROCEDURE:
1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and
ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.

62
 Program Output& Viva Total
(3) Result (4) (10)
(3)

RESULT:

63
Ex. No.: CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE
Date: COUNTER AND MOD 10/MOD 12 RIPPLE COUNTER

AIM:
To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter.

APPARATUS REQUIRED:

[Link]. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 30

THEORY:

A counter is a register capable of counting number of clock pulse arriving at

its clock input. Counter represents the number of clock pulses arrived. A specified
sequence of states appears as counter output. This is the main difference between a
register and a counter. There are two types of counter, synchronous and
asynchronous. In synchronous common clock is given to all flip flop and in
asynchronous first flip flop is clocked by external pulse and then each successive
flip flop is clocked by Q or Q output of previous stage. A soon the clock of second
stage is triggered by output of first stage. Because of inherent propagation delay
time all flip flops are not activated at same time which results in asynchronous
operation.

64
PIN DIAGRAM FOR IC 7476:

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0

65
 6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1

LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0

66
 4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0

LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0

67
 8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0

PROCEDURE:

1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and
ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.

Program Output& Viva Total

(3) Result (4) (10)
(3)

RESULT:

68
Ex. No.: DESIGN AND IMPLEMENTATION OF 3 BIT
Date: SYNCHRONOUS UP/DOWN COUNTER

AIM:
To design and implement 3 bit synchronous up/down counter.
APPARATUS REQUIRED:
[Link]. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:

A counter is a register capable of counting number of clock pulse arriving at

its clock input. Counter represents the number of clock pulses arrived. An up/down
counter is one that is capable of progressing in increasing order or decreasing order
through a certain sequence. An up/down counter is also called bidirectional
counter. Usually up/down operation of the counter is controlled by up/down signal.
When this signal is high counter goes through up sequence and when up/down
signal is low counter follows reverse sequence.

69
 STATE TABLE:
Input Present State Next State A B C
Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1

K MAP

70
STATE DIAGRAM:

CHARACTERISTICS TABLE:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

71
LOGIC DIAGRAM:

PROCEDURE:

1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and
ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.

Program Output& Viva Total

(3) Result (4) (10)
(3)

RESULT:

72