Interconnect Parameters – Capacitance, Resistance, and w = W - H/2

Inductance: RESISTANCE INTERCONNECT

Interconnect are physical connections between two transistors and/or PARAMETER:
the external surroundings. The resistance of a wire is proportional to its length
 multiple layers of aluminium or copper, layer of polysilicon, L and inversely proportional to its cross- section A.
heavily doped n+ and p+ diffusion layers The resistance of a rectangular conductor
ρL ρL
 They all cause an increase in propagation delay, or a drop in R= ohm= ohm
performance A HW
Where ρ is specific resistivity, L is length, A is area of cross-section = H.W
 They all have an impact on the energy dissipation and the power Sheet resistance, can be described as the ratio of the DC voltage drop per
distribution unit length to the surface current per width. Sheet resistance is a measure of
 They all cause the introduction of extra noise sources, which affect the electrical resistance of a thin layer of material, such as a thin film of a
the reliability of the circuit conducting or semiconducting material
1, Capacitance 2, Resistance 3, Inductance Material Sheet Resistance (Ω/□)
n or p well diffusion 1000-1500
CAPACITANCE INTERCONNECT PARAMETER: +¿ ¿ +¿¿
n , p diffusion 50-150
+¿ ¿ +¿¿
n , p diffusion with silicide 3-5
The capacitance of such a wire is a function of its shape, its +¿ ¿ +¿¿
n , p polysilocon 150-200
distance to the substrate, and the distance to surrounding wires. +¿ ¿ +¿¿
Two types (i) Parallel plate Capacitance and (ii)Fringe Capacitance n , p polysilicon with silicide 4-5
(i) Parallel plate Capacitance: Aluminium 0.05-1
Consider a rectangular wire placed above the semiconductor
substrate. If the width of the wire is substantially larger than the At very high frequencies an additional phenomenon — called the skin effect
— comes into play such that the resistance becomes frequency-dependent.
thickness of the insulating material, it may be assumed that the
electrical-field lines are orthogonal to the capacitor plates, and that INDUCTANCE INTERCONNECT PARAMETER:
its capacitance can be modeled by the parallel-plate capacitance
model. The inductance of a section of a circuit states that a changing
where W and L are respectively the width current passing through an inductor generates a voltage drop ΔV.
and length of the wire,
and tdi and εdi represent the
thickness of the dielectric layer and
its permittivity. On-chip inductance include ringing and overshoot effects,
reflections of signals due to impedance mismatch, inductive
(ii) Fringing Capacitance:
coupling between lines, and switching noise due to Ldi/dt voltage
The capacitance between the side-
walls of the wires and the substrate,
called the fringing capacitance, as shown below.
drops.
Lumped Model: represented by a distributed rc-model.

The circuit parasitics of a wire are distributed along its length and
are not lumped into a single position. Yet, when only a single Assume now that each of the N nodes of the network is initially
parasitic component is dominant, when the interaction between the discharged to GND, and that a step input is applied at node s at time
components is small, it is often useful to lump the different t = 0. The Elmore delay at node i is then given by the following
fractions into a single circuit element. The advantage of this expression:
approach is that the effects of the parasitic then can be described by Therefore, the Elmore delay is equivalent to the first-order time
an ordinary differential equation. constant of the network (or the first moment of the impulse

response).
RC Chain/ The Elmore RC Chain Delay:

Distributed RC line Model/ Distributed rc line Model:

The operation of this simple RC network is described by the A distributed rc line model is a more appropriate model which has,
following ordinary differential equation r and c stand for the resistance and capacitance per unit length.
Lumped RC Model/ The Elmore Delay:
The Transmission Line Model:
Similar to the resistance and capacitance of an interconnect line, the
inductance is distributed over the wire. A distributed rlc model of a
wire, known as the transmission line model
The transmission line has the prime property that a signal
propagates over the interconnection medium as a wave. This is in
contrast to the distributed rc model, where the signal diffuses from
the source to the destination governed by the diffusion equation

Comparators, Shifters, Multi-input Adders, Multipliers

This simple model, called the lumped RC model, is pessimistic and
0’s detector: A = 00…000
inaccurate for long interconnect wires, which are more adequately
 1’s detector: A = 11…111 Funnel Shifter
Equality comparator: A=B A funnel shifter can do all six types of shifts
Magnitude comparator: A < B Selects N-bit field Y from 2N–1-bit input
1’s detector: N-input AND gate Shift by k bits (0  k < N)
0’s detector: NOTs + 1’s detector (N-input NOR) Logically involves N N:1 multiplexers
Equality Comparator N N-input multiplexers
Check if each bit is equal (XNOR, aka equality gate) Use 1-of-N hot select signals for shift amount
1’s detect on bitwise equality nMOS pass transistor design (Vt drops!)

Magnitude Comparator
Compute B – A and look at sign
B – A = B + ~A + 1
For unsigned numbers, carry out is sign bit

Barrel Shifter
Barrel shifters perform right rotations using wrap-around wires.
Left rotations are right rotations by N – k = k + 1 bits.
Shifters Shifts are rotations with the end bits masked off.
Logical Shift: Shifts number left or right and fills with 0’s
1011 LSR 1 = 0101 1011 LSL1 = 0110
Arithmetic Shift: Shifts number left or right. Rt shift sign extends
1011 ASR1 = 1101 1011 ASL1 = 0110
Rotate: Shifts number left or right and fills with lost bits
1011 ROR1 = 1101 1011 ROL1 =0111

• Working of 4-bit Ripple Carry Adder
• Let’s take an example of two input sequences 0101 and 1010.
These are representing the A4 A3 A2 A1 and B4 B3 B2 B1.
• As per this adder concept, input carry is 0.
• When Ao & Bo are applied at 1st full adder along with input
carry 0.
• Here A1 =1 ; B1=0 ; Cin=0
• Sum (S1) and carry (C1) will be generated as per the Sum and
Carry equations of this adder. As per its theory, the output
equation for the Sum = A1⊕B1⊕Cin and Carry =
A1B1⊕B1Cin⊕CinA1
• As per this equation, for 1st full adder S1 =1 and Carry output
i.e., C1=0.
• Same like for next input bits A2 and B2, output S2 = 1 and
C2 = 0. Here the important point is the second stage full adder
gets input carry i.e., C1 which is the output carry of initial
stage full adder.
• Like this will get the final output sequence (S4 S3 S2 S1) = (1 • High-speed Carry Look-ahead Adders are used as
1 1 1) and Output carry C4 = 0 implemented as IC’s. Hence, it is easy to embed the adder in
• This is the addition process for 4-bit input sequences when circuits. By combining two or more adders calculations of
it’s applied to this carry adder. higher bit boolean functions can be done easily. Here the
increase in the number of gates is also moderate when used
for higher bits.
•
• 4-Bit Carry Look-ahead Adder •
• In parallel adders, carry output of each full adder is given as a
carry input to the next higher-order state. Hence, these adders
it is not possible to produce carry and sum outputs of any
state unless a carry input is available for that state.
• So, for computation to occur, the circuit has to wait until the
carry bit propagated to all states. This induces carry
propagation delay in the circuit.

• Using the Gi and Pi terms the Sum Si and Carry Ci+1 are
given as below –
• Si = Pi ⊕ Gi.
• Ci+1 = [Link] +Gi.
• Therefore, the carry bits C1, C2, C3, and C4 can be calculated
• C1 = C0.P0+G0.
• C2 = C1.P1+G1 = ( C0.P0+G0).P1+G1.
• C3 = C2.P2+G2 = (C1.P1+G1).P2+G2.
• C4 = C3.P3+G3 = C0.P0.P1.P2.P3 + P3.P2.P1.G0 +
P3.P2.G1 + G2.P3 + G3.
• It can be observed from the equations that carry Ci+1 only

depends on the carry C0, not on the intermediate carry bits.

Applications