SystemVerilog Interview Questions – Section-wise

Prepared By: Shashi Kant Sharma

(Senior Knowledge Associate), FutureWiz

1. Data Types in SystemVerilog

Basic (1–10):

1. What is the difference between reg, wire, and logic?

2. How is bit different from logic?

3. What are 2-state and 4-state variables? Give examples.

4. What is a typedef and how is it used in SystemVerilog?

5. What is the use of enum in SystemVerilog?

6. What is the difference between int, integer, and longint?

7. Explain packed vs unpacked arrays.

8. What is the difference between static and dynamic arrays?

9. How is a queue different from a dynamic array?

10. What are associative arrays and where are they useful?

Advanced (11–20):

11. How do you initialize a dynamic array? How can you resize the dynamic array (while keeping
previous values , without keeping previous values)

12. What happens when you access an out-of-bounds index in a queue? Can we initialize queue
using foreach loop?

13. How to declare Associative array? How it is different from dynamic array. If different type of
addresses are there, can we iterate this array using foreach loop?

14. Can we mix 2-state and 4-state types? What are the implications?

15. What is a union in SystemVerilog? Give an example.

16. How is a string handled differently from an array of bytes?

17. What are the advancements incorporated in System Verilog Functions? Explain function call
by value and function call by reference?

18. How does bit[7:0] a; differ from byte a;?

19. What is a null handle in the context of classes? Write a code snippet to check whether the
handle of any class is created or not.

20. List all the SV data types, What are default initial values for various SV data types?
 2. Classes and OOP Concepts

Basics (21–30):

21. What is a class in SystemVerilog?

22. How do you define a constructor in a class?

23. What is the difference between class and struct?

24. What is the use of the this keyword?

25. How do you instantiate a class?

26. What is encapsulation in OOP?

27. What are the advantages of using classes in verification?

28. How is memory allocated for classes vs structs?

Advanced OOP (31–45):

29. Explain inheritance with an example.

30. What is the super keyword used for?

31. What are virtual methods? Why are they important?

32. How does dynamic polymorphism work in SV?

33. What is the purpose of the virtual class? Explain the Virtual methods and pure virtual
methods.

34. What is interface class and when should it be used?

35. How do you implement deep copy in a class? Differentiate between shallow copy and deep
copy with an Example.

36. What is the difference between static and automatic class members? Can we access class
properties and methods without handle? Illustrate with Example.

37. Explain the extern keyword with example. Write an extern method .

38. Can classes contain processes like @ or forever? If yes, how?

39. How do you pass a class object as an argument to a task or function?

40. What is the use of parameterized classes?

41. How do classes support inheritance and constraint reuse?

42. Write a code snippet which counts the total number of objects created for class.

43. Can classes be compared using ==? What does it compare?

44. How is new[] used to create arrays of objects?

 45. Explain the rules to implement polymorphism. Write a code to demonstrate polymorphism
in multilevel inheritance.

3. Randomization & Constraints

Basics (46–55):

46. What is the difference between rand and randc? Mimic the functionality of randc using rand.

47. How do you define constraints in SystemVerilog?

48. How is randomization triggered in a class?

49. What is the use of constraint_mode() method?

50. How do you use inline constraints?

51. What is the use of the inside keyword?

52. Explain with example: weighted randomization using dist.

53. What happens if randomization fails?

54. How do you randomize a class object within another class?

55. Can you use randc inside a constraint?

Advanced (56–70):

56. What are soft constraints?

57. How do you override constraints in derived classes?

58. What is constraint inheritance?

59. What are implications of conflicting constraints?

60. How do you debug randomization failures?

61. What is the difference between solve before and unique constraints?

62. How can you disable specific constraints?

63. What is the scope of constraints?

64. Can you constrain the size of dynamic arrays or queues?

65. How do you apply constraints conditionally?

66. Explain pre_randomize() and post_randomize().

67. How to randomize an enum value?

68. What is random stability?

69. Explain the concept of "constraint duplication".

70. How can you restrict values to be prime numbers or odd only?
 4. Inter-process Communication and Concurrency

Fork-Join (71–75):

71. What are the types of fork-join? Explain fork-join_any and fork-join_none.

72. How do you create parallel processes?

73. How do you implement a timeout using fork-join_any? Mimic fork-join functionality using (a)
fork join_any (b) fork- join_none.

74. What are race conditions and how do you prevent them?

75. Can you use wait fork inside a class?

Semaphore (76–80):

76. What is a semaphore in SystemVerilog?

77. How do you initialize a semaphore?

78. Difference between get(), try_get() and peek() in semaphore?

79. How are semaphores used to implement resource locking?

80. What happens if two processes try to acquire the same semaphore token?

Mailbox (81–85):

81. What is a mailbox and its use case?

82. Difference between put() and try_put()?

83. How do you check if a mailbox is empty?

84. Can you pass a class object through a mailbox?

85. What is the use of blocking and non-blocking get()?

Interface (86–90):

86. What is the purpose of an interface in SV?

87. How does an interface simplify DUT connectivity?

88. What is a modport? Explain the clocking block.

89. How are modports used for access control?

90. Can an interface contain tasks and functions?

5. Functional Coverage

Basics (91–95):

91. What is functional coverage? Why is it needed?

 92. How do you declare a covergroup?

93. What is a coverpoint?

94. How do you sample a covergroup?

95. How do you exclude bins from coverage?

Advanced (96–105):

96. What is cross coverage? How do you control bin combinations?

97. How do you associate a covergroup with a class?

98. What are illegal bins and ignore bins?

99. How do you write conditional coverpoints?

100. What is coverage merging?

101. What is the effect of coverage_control() method?

102. What is the purpose of bins = default?

103. How do you extract functional coverage data from a simulator?

104. How to disable/enable coverage selectively?

105. What’s the difference between code coverage and functional coverage?

6. Assertions (SVA)

Basics (106–110):

106. What are assertions in SystemVerilog?

107. Difference between immediate and concurrent assertions?

108. What is a sequence in SVA?

109. What is the difference between |-> and |=>?

110. What is the use of disable iff()?

Advanced (111–120):

111. How do you assert that signal A stays high for 3 clock cycles?

112. How do you check if one signal follows another within N cycles?

113. How do you handle assertion failures gracefully?

114. What is vacuous success?

115. How to create overlapping and non-overlapping sequences?

116. What is the difference between @ (posedge clk) and @(negedge clk) in assertions?
Differentiate @(posedge clk) with $rose(clk)
117. How to write temporal assertions with multiple conditions?

118. How are properties reused across assertions?

119. Can you write assertions inside modules and interfaces?

120. What are concurrent cover properties?

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