8086 Microprocessor

By
Dr. Pradyut Kumar Biswal
 Microprocessor Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology  Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are8086 Microprocessor
11/12/2025 32
multiplexed Intel 8085 (8 bit processor)
 Overview
➢ First 16- bit processor released by ➢ Addressable memory space is
INTEL in the year 1978 organized in to two banks of 512 kb
each; Even (or lower) bank and Odd
(or higher) bank. Address line A0 is
➢ Originally HMOS, now manufactured used to select even bank and control
using HMOS III technique signal 𝐁𝐇𝐄 is used to access odd
bank

➢ Approximately 29, 000 transistors, ➢ Uses a separate 16 bit address for

40 pin DIP, 5V supply I/O mapped devices  can generate
216 = 64 k addresses.

➢ Does not have internal clock; ➢ Operates in two modes: minimum

external asymmetric clock source mode and maximum mode, decided
with 33% duty cycle by the signal at MN and 𝐌𝐗 pins.

➢ It can prefetches up to 6 instruction

➢ 20-bit address to access memory  bytes from memory and queues
can address up to 220 = 1 megabytes them in order to speed up
of memory space. instruction execution.

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Architecture
11/12/2025 8086 Microprocessor 5
 Architecture
Both units operate
asynchronously to
give the 8086 an
overlapping
instruction fetch and
execution
mechanism which is
called as Pipelining.
This results in
efficient use of the
system bus and
system performance.

Bus Interface Unit (BIU)

BIU fetches instructions, reads data
Execution Unit (EU)
from memory and I/O ports, writes
data to memory and I/ O ports,
EU executes instructions that have
calculating the address of the
already been fetched by the BIU.
memory operands and transferring
the instruction bytes to queue.
BIU and EU functions separately.
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Architecture: BIU
Dedicated Adder to generate
20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

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 Architecture: BIU
Segment
Registers

8086’s 1-megabyte memory The 8086 can directly address four Programs obtain access to code
is divided into segments of segments (256 K bytes within the 1 and data in the segments by
up to 64K bytes each. M byte of memory) at a particular changing the segment register
time. content to point to the desired
segments.

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Architecture: BIU
Segment Code Segment Register
Registers
➢ 16-bit

➢ CS contains the base or start of the current code segment; IP contains

the distance or offset from this address to the next instruction byte to
be fetched.

➢ BIU computes the 20-bit physical address by logically shifting the

contents of CS 4-bits to the left and then adding the 16-bit contents of
IP.

➢ That is, all instructions of a program are relative to the contents of the
CS register multiplied by 16 and then offset is added provided by the
IP.

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Architecture: BIU
Segment Data Segment Register
Registers
➢ 16-bit

➢ Points to the current data segment; operands for most instructions

are fetched from this segment.

➢ The 16-bit contents of the Source Index (SI) or Destination Index (DI)
or a 16-bit displacement are used as offset for computing the 20-bit
physical address.

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Architecture: BIU
Segment Stack Segment Register
Registers
➢ 16-bit

➢ Points to the current stack.

➢ The 20-bit physical stack address is calculated from the Stack Segment
(SS) and the Stack Pointer (SP) for stack instructions such as PUSH and
POP.

➢ In based addressing mode, the 20-bit physical stack address is

calculated from the Stack segment (SS) and the Base Pointer (BP).

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Architecture: BIU
Segment Extra Segment Register
Registers
➢ 16-bit

➢ Points to the extra segment in which data (in excess of 64K pointed to
by the DS) is stored.

➢ String instructions use the ES and DI to determine the 20-bit physical

address for the destination.

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Architecture: BIU
Segment Instruction Pointer
Registers
➢ 16-bit

➢ Always points to the next instruction to be executed within the

currently executing code segment.

➢ So, this register contains the 16-bit offset address pointing to the next
instruction code within the 64Kb of the code segment area.

➢ Its content is automatically incremented as the execution of the next

instruction takes place.

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Memory Address Generation
Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

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 Memory Address Generation
➢ The following examples shows the CS:IP scheme of address
formation:
CS 34BA IP 8AB4 Code segment
34BA0
Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR 8AB4 (offset)
four binary digits left
3D654

34BA0(CS)+
8AB4(IP)
3 D 6 5 4 (next address)
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8086 Microprocessor 15
• Example For Address Calculation (segment: offset)

• If the data segment starts at location 1000h and a data

reference contains the address 29h where is the actual
data?

Offset 0000 0000 0010 1001

Segment Address
0001 0000 0000 0000 0000

Required Address 0001 0000 0000 0010 1001

16
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Architecture: BIU
Instruction queue

➢ A group of First-In-First-
Out (FIFO) in which up to 6
bytes of instruction code are
pre fetched from the
memory ahead of time.
➢ This is done in order to
speed up the execution by
overlapping instruction fetch
with execution.
➢ This mechanism is known
as pipelining.
➢ Whenever the queue of the
BIU is not full, it has room
for at least two more bytes
and at the same time the EU
is not requesting it to read or
write operands from
memory, the BIU is free to
look ahead in the program
by pre-fetching the next
sequential instruction.
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Architecture: BIU
Instruction queue

➢ If BIU is interrupted by EU
for memory access during
fetching of an instruction,
then it first completes the
fetching and then services
the EU.
➢ If any branch instruction is
encountered, BIU will reset
the queue and begin
refilling from new location
after passing the
instruction to EU. This is
called pipeline flushing.

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 Architecture: EU
▪ EU decodes and
executes instructions.
▪ A decoder in the EU
control system
translates instructions.
▪ Generates data address
if necessary and passes
it to BIU.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL
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DX can be used as DH and DL 19
Architecture: EU
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 6 types OF DF IF TF SF ZF AF PF CF

[Link]. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

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Architecture: EU
EU Accumulator Register (AX)
Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or

AL.

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Architecture: EU
EU Base Register (BX)
Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

All memory references utilizing this register content for

addressing use DS as the default segment register.

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Architecture: EU
EU Counter Register (CX)
Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

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Architecture: EU
EU Data Register (DX)
Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.

When combined, DL register contains the low order byte of

the word, and DH contains the high-order byte.

Used to hold the high 16-bit result (data) in 16 X 16

multiplication or the high 16-bit dividend (data) before a
32 ÷ 16 division and the 16-bit reminder after division.

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Architecture: EU
EU Stack Pointer (SP) and Base Pointer (BP)
Registers
SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during

execution of instructions that involve the stack segment in
the external memory.

SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.

BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.

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Architecture: EU
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

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 Architecture: EU
Auxiliary Carry Flag Carry Flag
Flag Register This is set, if there is a carry or borrow This flag is set, when there is
from the lowest nibble, i.e, bit three a carry out of MSB in case of
during addition or during subtraction addition or a borrow in case
respectively. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Trap Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
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8086 Microprocessor
decrementing mode. 27
Registers and Special Functions: Summary
Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to access memory
data

CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS register to
access data from stack memory

SI Source Index Used to hold index value of source operand (data) for string
instructions

DI Data Index Used to hold the index value of destination operand (data) for string
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8086 Microprocessor 28
 Segment and Offset register
Combination
• CS:IP

• SS:SP SS:BP

• DS:BX DS:SI

• DS:DI (for other than string operations)

• ES:DI (for string operations)

29
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Pins and signals
Pins and Signals: Common Signals
AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals

S4 S3 Segment Register
S5 = IF,
0 0 ES
S6 = 0
0 1 SS always
1 0 CS or no access
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1 1 DS
 Pins and Signals: Common Signals
BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
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 Pins and Signals: Common Signals

Operation 𝑩𝑯𝑬 A0 Data Lines Used

1 Read/ Write byte at an even address 1 0 D7 – D0

2 Read/ Write byte at an odd address 0 1 D15 – D8

3 Read/ Write word at an even address 0 0 D15 – D0

4 Read/ Write word at an odd address 0 1 D15 – D8 in first operation byte from
odd bank is transferred
1 0 D7 – D0 in first operation byte from
even bank is transferred

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 Pins and Signals: Common Signals
TEST
𝐓𝐄𝐒𝐓 input is used in conjunction with the
‘WAIT’ instruction.

8086 will enter a wait /idle state after

execution of the WAIT instruction and
will resume execution only when the
𝐓𝐄𝐒𝐓 is made low by an active hardware.

This is used to synchronize an external

activity to the processor internal
operation.

READY
This is the acknowledgement from the
slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.
The signal is active high.

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 Pins and Signals: Common Signals
RESET (Input)
Causes the processor to immediately
terminate its present activity.
The signal must be active HIGH for at
least four clock cycles.

When the system is rest, Flag register is

cleared. This disables the external
interrupts. IP and three segment
CLK
registers DS, SS, and ES are cleared.. The
The clock input provides the basic timing
CS register is set to FFFFH. This reset
for processor operation and bus control
operation takes about 10 clock periods.
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled
during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.
This signal is active high and internally
synchronized.

NMI Non Maskable Interrupt

It is positive edge triggered non
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maskable interrupt request.
Pins and Signals: Mode Pin
The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

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Pins and Signals: Minimum Mode
Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)

8086 itself generates all the bus control signals

DT/𝐑
ഥ (Data Transmit/ Receive) Output signal from the
processor to control the direction of data flow
through the data transceivers. When high, data is
being transmitted by 8086.
𝐃𝐄𝐍 (Data Enable) Output signal from the processor
used as out put enable for the transceivers

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

M/𝐈𝐎 Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

𝐖𝐑 Write control signal; asserted low Whenever

processor writes data to memory or I/O port

𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
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Pins and Signals: Minimum Mode
Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)

8086 itself generates all the bus control signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

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Latching of 20-bit address

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Buffering Data Bus

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Deriving Control Signals

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Pins and Signals: Maximum Mode
During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)

Pins 24 -31 are reassigned

𝑺𝟎 , 𝑺𝟏 , 𝑺𝟐 Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.

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Pins and Signals: Maximum Mode
During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)

Pins 24 -31 are reassigned

𝑸𝑺𝟎 , 𝑸𝑺𝟏 (Queue Status) The processor provides the status

of queue in these lines.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.

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Pins and Signals: Maximum Mode
During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)

Pins 24 -31 are reassigned

𝐑𝐐/𝐆𝐓𝟎 , (Bus Request/ Bus Grant) These requests are used

𝐑𝐐/𝐆𝐓𝟏 by other local bus masters to force the processor
to release the local bus at the end of the
processor’s current bus cycle.

These pins are bidirectional.

The request on𝐆𝐓𝟎 will have higher priority than𝐆𝐓𝟏

𝐋𝐎𝐂𝐊 An output signal activated by the LOCK prefix

instruction.

Remains active until the completion of the

instruction prefixed by LOCK.

The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while

executing an instruction prefixed by LOCK to
prevent other bus masters from gaining control of
the system bus.

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 Memory
Processor Memory
▪ Registers inside a microcomputer
▪ Store data and results temporarily
▪ No speed disparity
▪ Cost 

Primary or Main Memory

▪ Storage area which can be directly accessed by
Memory microprocessor
▪ Store programs and data prior to execution
Store Programs
▪ Should not have speed disparity with processor 
and Data
Semi Conductor memories using CMOS technology
▪ ROM, EPROM, Static RAM, DRAM

Secondary Memory
▪ Storage media comprising of slow devices such as
magnetic tapes and disks
▪ Hold large data files and programs: Operating
system, compilers, databases, permanent programs
etc.
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Memory organization in 8086
Memory IC’s : Byte oriented

8086 : 16-bit

Word : Stored by two consecutive memory

locations; for LSB and MSB

Address of word : Address of LSB

Bank 0 : A0 = 0  Even addressed

memory bank

Bank 1 : 𝑩𝑯𝑬 = 0  Odd

addressed memory bank

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Memory organization in 8086

Operation 𝑩𝑯𝑬 A0 Data Lines Used

1 Read/ Write byte at an even address 1 0 D7 – D0

2 Read/ Write byte at an odd address 0 1 D15 – D8

3 Read/ Write word at an even address 0 0 D15 – D0

4 Read/ Write word at an odd address 0 1 D15 – D8 in first operation byte from
odd bank is transferred
1 0 D7 – D0 in first operation byte from
even bank is transferred
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 8284 Clock Generator
• The 8086 CPUs require a specific waveform for
the system clock
– Fast rise and fall times ( <10ns )
– Logic 0: -0.5 to 0.6 V
– Logic 1: 3.9 to 5.0 V
– Duty cycle of 33%

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 8284 Clock Generator
➢ The 8284 provides the proper
clock signal
– Uses a crystal oscillator (3
oscillations per clock)

➢ Provides the correct waveforms

for other signals to 8086.
– RESET
– the READY signal for the
insertion of WAIT states into the
processor bus cycle.

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 8284 Clock Generator
➢ F/C̅ (Frequency/Crystal) The voltage on this pin
determines the clocking source for the 8284A. If this
input pin is high, an external clock at EFI is selected.
While it is low, the internal crystal oscillator
provides the clock frequency signal.
➢ X1 and X2 Crystal Inputs These pins are connected
to an external crystal which is used as a clock
frequency source of the clock generator. The
external crystal clock frequency will be about three
times the required frequency.
➢ EFI (External Frequency Input) This is an alternate
clock input when F/C̅ pin is pulled high.
➢ CLK CLK is an output pin that provides the clock
(CLK) signal which is used as input signal to the 8086
processor. The CLK pin has an output signal with
33% duty cycle.
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 8284 Clock Generator
➢ PCLK (Peripheral Clock) This is a clock output
signal that is one sixth of the crystal. PLCK is
half of the clock frequency and has a 50% duty
cycle.
➢ OSC (Oscillator Output) This is an oscillator-
output signal which is running at crystal or EFI
frequency and can be used to provide clock
signal at EFI to the other 8284 clock generators
in multiple processor system.
➢ CSYNC (Clock Synchronization) This pin is used
for synchronization of clock signals in a
multiprocessor system where all processors
receive the clock at EFI. If the internal crystal
oscillator is used, this pin must be grounded.

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 8284 Clock Generator and Driver
• R̅E̅S̅ (Reset Input) To reset the 8086 processor,
8284A clock generator should send the RESET
signal. Generally, this pin is connected to an RC
network for generating RESET signal at power
on.
• RESET (Reset Output) This signal is connected
to the 8086 RESETs input pin. The RESET signal
must be synchronized with the clock.
• RDY1 , RDY2 The slow memory or I/O devices
can request for extension of bus cycles using
RDY1 or RDY2 pins. These two wait-state ready
inputs are provided to support a 8086- based
system.
• READY The READY output pin connects to the
8086 READY input which enables the bus cycle
period insertion between T3 and T4. The 8086
READY signal must be synchronized with the
RDY1 and RDY2 inputs.
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 8284 Clock Generator and Driver
➢ A̅S̅YN
̅ C ̅ ̅ (Ready Synchronization Select) This
input pin is used to select either one or two
stages of synchronization for the RDY1 and
RDY2 inputs. If it is low, one level is
selected. When it is high, two levels of
synchronization are selected.
➢ A̅E̅N1̅ , A̅E̅N2̅ These signals are provided to
arbitrate bus priorities whenever RDY1 and
RDY2 are active. The 8284A responds to
RDY1 when A̅E̅N̅1 is low. In the same way,
clock generator responds to RDY2 if A̅E̅N2̅ is
low.
➢ VCC (Power Supply Input) This pin is
connected to + 5 V ± 10%.
➢ GND (Ground) This pin must be grounded.

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Minimum mode 8086 System

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 Minimum mode Read Cycle Timing
Diagram

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Minimum mode Write Cycle Timing
Diagram

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The 8288 Bus Controller
➢ Provides the signals eliminated from the 8086/8088 by
the maximum mode operation.

The 8288 bus controller; (a) block diagram and (b) pin diagram.
IC 8288 Internal Block Diagram
INTA
IORD
Status Command IOWR
S2
Decoder Signal AIORD
S1
Generator MRD
S0
MWR
AMWR

CLK DT/R
Control
AEN Control DEN
Signal
CEN Logic ALE
Generator
IOB MCE/PDEN
 8288 Bus Controller Pin Functions
➢ Status inputs are connected to the status output
pins on 8086.

Status Signals
Command Signal Generated
S2 S1 S0

0 0 0 INTA

0 0 1 IORD

0 1 0 IOWR/AIOWR

0 1 1 HALT State

1 0 0 OPCODE fetch operation

1 0 1 MRD

1 1 0 MWR/AMWR

1 1 1 Passive
 8288 Bus Controller Pin Functions
• CLK: The clock input provides internal timing. The CLK
output pin of the 8284 signal generator is connected to
CLK pin of IC 8288.
• ALE: The address latch enable output is used to
demultiplex the address/data bus and address/status
bus.
• DEN: The data bus enable pin is used to enable the
transreceiver IC which controls the bidirectional data
bus in the system.
• DT/R: Data transmit/receive signal output to control
direction of the bidirectional data bus buffers.
 8288 Bus Controller Pin Functions
• AEN: If logic 0 is applied to this pin (address enable)
then all the control signals gets enabled.
• CEN: If logic 1 is applied on this pin (control enable)
then all the command signals gets enabled along with
control signals with AEN = 0 .
• IOB: The I/O bus mode input selects either I/O
bus mode or system bus mode operation.
If IOB = 1, I/O bus mode is selected and PDEN = 0
If IOB = 0, system bus mode is selected and MCE = 1
 8288 Bus Controller Pin Functions
• AEN: If logic 0 is applied to this pin (address enable)
then all the control signals gets enabled.
• CEN: If logic 1 is applied on this pin (control enable)
then all the command signals gets enabled along with
control signals with AEN = 0 .
• IOB: The I/O bus mode input selects either I/O
bus mode or system bus mode operation.
If IOB = 1, I/O bus mode is selected and PDEN = 0
If IOB = 0, system bus mode is selected and MCE = 1
 8288 Bus Controller Pin Functions
• AIOWR: Advanced I/O write is a command output to
an advanced I/O write control signal.
• IORD: The I/O read command output provides
I/O with its read control signal.
• IOWR: The I/O write command output provides I/O
with its write control signal.
• AMWR: Advanced memory write control pin provides
memory with an early/advanced write signal.
• MWR: The memory write control pin provides
memory with its normal write control signal.
• MRD: The memory read control pin provides memory
with a read control signal.
 8288 Bus Controller Pin Functions
• INTA: The interrupt acknowledge output
acknowledges an interrupt request input applied to
the INTR pin.

• MCE/PDEN: The master cascade enable /peripheral

data enable output selects cascade operation for IC
8259PIC if IOB is connected to logic 0 and enables the
I/O bus transceivers if IOB is connected to logic 1.
 Summary of 8288
• Minimum mode operation is similar to that of the Intel
8085A microprocessor, whereas maximum mode
operation is new and specifically designed for the
operation of the 8087 arithmetic coprocessor.

• The 8288 bus controller must be used in the maximum

mode to provide the control bus signals to the
memory and I/O.
Maximum mode 8086 System

11/12/2025 8086 Microprocessor 66

 Maximum mode Read Cycle
Timing Diagram

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 Maximum mode Write Cycle
Timing Diagram

11/12/2025 8086 Microprocessor 68

 ADDRESSING MODES
of 8086

11/12/2025 8086 Microprocessor 69

 Addressing Modes
Every instruction of a program has to operate on a data.
The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing
memory data
7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for
10. Indirect I/O port Addressing I/O ports

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing

11/12/2025 Group
8086 Microprocessor V : Implied Addressing m
704o
0de
 Addressing Modes
1. Register Addressing The instruction will specify the name of the
register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL

7. Based Index Addressing (CL)  (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

11/12/2025 8086 Microprocessor 71

 Addressing Modes
1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL)  08H

8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX)  0A9FH
12. Implied Addressing

11/12/2025 8086 Microprocessor 72

 Addressing Modes : Memory Access
20 Address lines  8086 can address up to
220 = 1M bytes of memory

However, the largest register is only 16 bits

Physical Address will have to be calculated

Physical Address : Actual address of a byte in
memory. i.e. the value which goes out onto the
address bus.

Memory Address represented in the form –

Seg : Offset (Eg - 89AB:F012)

Each time the processor wants to access

memory, it takes the contents of a segment
register, shifts it one hexadecimal place to the
16 bytes of
left (same as multiplying by 1610), then add the contiguous memory
required offset to form the 20- bit address

89AB : F012 → 89AB → 89AB0 (Paragraph to byte → 89AB x 10 = 89AB0)

F012 → 0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
11/12/2025 8086 Microprocessor 44
73
 Addressing Modes
1. Register Addressing

2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.

5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
7. Based Index Addressing
MOV BX, [1354H]
8. String Addressing MOV BL, [0400H]
9. Direct I/O port Addressing
The square brackets around the 1354H denotes
10. Indirect I/O port Addressing
the contents of the memory location. When
executed, this instruction will copy the contents of
11. Relative Addressing the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.

11/12/2025 8086 Microprocessor 74

 Addressing Modes
1. Register Addressing In Register indirect addressing, name of the
register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.

3. Direct Addressing Registers used to hold EA are any of the following

registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
6. Indexed Addressing
address calculation.
7. Based Index Addressing
Example:
Note : Register/ memory
8. String Addressing
enclosed in brackets refer
MOV CX, [BX]
to content of register/
9. Direct I/O port Addressing memory
Operations:
10. Indirect I/O port Addressing
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
12. Implied Addressing
(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA +1)
11/12/2025 8086 Microprocessor 75
 Addressing Modes
1. Register Addressing In Based Addressing, BX or BP is used to hold the
base value for effective address and a signed 8-bit
2. Immediate Addressing or unsigned 16-bit displacement will be specified
in the instruction.
3. Direct Addressing
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.

5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
6. Indexed Addressing

7. Based Index Addressing

When BP holds the base value of EA, BP and SS is
used.
8. String Addressing
Example:
9. Direct I/O port Addressing
MOV AX, [BX + 08H]
10. Indirect I/O port Addressing
Operations:
11. Relative Addressing
0008H  08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA

(AX)  (MA) or,

(AL)  (MA)
11/12/2025 8086 Microprocessor
(AH)  (MA + 1) 48
76
 Addressing Modes
1. Register Addressing SI or DI register is used to hold an index value for
memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
3. Direct Addressing
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.

5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
6. Indexed Addressing

7. Based Index Addressing

Example:
8. String Addressing
MOV CX, [SI + 0A2H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing
FFA2H  A2H (Sign extended)
11. Relative Addressing
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
11/12/2025 8086 Microprocessor 77
 Addressing Modes
1. Register Addressing In Based Index Addressing, the effective address
is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
6. Indexed Addressing
000AH  0AH (Sign extended)
7. Based Index Addressing

8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA

10. Indirect I/O port Addressing (DX)  (MA) or,

11. Relative Addressing (DL)  (MA)

(DH)  (MA + 1)
12. Implied Addressing

11/12/2025 8086 Microprocessor 78

 Addressing Modes
1. Register Addressing Employed in string operations to operate on string
data.
2. Immediate Addressing
The effective address (EA) of source data is stored
3. Direct Addressing in SI register and the EA of destination is stored in
DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES
6. Indexed Addressing

7. Based Index Addressing

Example: MOVS BYTE
8. String Addressing
Operations:
9. Direct I/O port Addressing
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA

11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
12. Implied Addressing

Note : Effective address of (MAE)  (MA)

the Extra segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
11/12/2025 If8086
DFMicroprocessor
= 0, then (SI)  (SI) +1 and (DI) = (DI)51+1
79
 Addressing Modes
1. Register Addressing These addressing modes are used to access data
from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.

4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing Operations: PORTaddr = 09H

(AL)  (PORT)
6. Indexed Addressing
Content of port with address 09H is
7. Based Index Addressing
moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.

11. Relative Addressing Example: OUT [DX], AX

12. Implied Addressing Operations: PORTaddr = (DX)
(PORT)  (AX)

Content of AX is moved to port

whose address is specified by DX
11/12/2025
register.
8086 Microprocessor 80
 Addressing Modes
1. Register Addressing

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
6. Indexed Addressing
Operations:
7. Based Index Addressing

8. String Addressing 000AH  0AH (sign extend)

9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
11. Relative Addressing MA = BA + EA

12. Implied Addressing If ZF = 1, then the program control jumps to

new address calculated above.

If ZF = 0, then next instruction of the

program is executed.
11/12/2025 8086 Microprocessor 81
 Addressing Modes
1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

11/12/2025 8086 Microprocessor 82

 Instruction Set

8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

11/12/2025 8086 Microprocessor 83

 Instruction Set
Data Transfer Instructions

➢ Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.

➢ Generally involve two operands: Source operand and

Destination operand of the same size.

➢ Source: Register or a memory location or an immediate

data Destination : Register or a memory location.

➢ The size should be a either a byte or a word.

➢ A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/
memory.

11/12/2025 8086 Microprocessor 84

 Instruction Set
Data Transfer Instructions
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …
MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, mem (reg2)  (mem)

MOV reg/ mem, data

MOV reg, data (reg)  data

MOV mem, data (mem)  data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)

11/12/2025 8086 Microprocessor 85

 Instruction Set
Data Transfer Instructions
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …
PUSH reg16/ mem

PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)

PUSH mem (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 1610 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2

POP mem MA S = (SS) x 1610 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2
11/12/2025 8086 Microprocessor 59
86
 Instruction Set
Data Transfer Instructions
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …
PUSHF :
Push flags onto stack. (SP)  (SP) – 2
MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (flag)
No flags are affected.

POPF

POP flags from stack MA S = (SS) x 1610 + SP

(flag)  (MA S ; MA S + 1)
All status and control flags are (SP)  (SP) + 2
modified.

11/12/2025 8086 Microprocessor 59

87
 Instruction Set
Data Transfer Instructions
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)

IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX)

(AX)  (PORT) (PORT)  (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL)  (addr8) OUT addr8, AL (addr8)  (AL)

IN AX, addr8 OUT addr8, AX
(AX)  (addr8) (addr8)  (AX)

11/12/2025 8086 Microprocessor 88

 Instruction Set
Data Transfer Instructions
Mnemonics: LAHF, SAHF…

LAHF

Load AH register from flags lower byte AH = Flag_LByte

SAHF

Store the content of AH in lower byte of Flag_Lbyte = AH

Flag register.

11/12/2025 8086 Microprocessor 89

 Instruction Set
Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADD reg2, reg1 (reg2)  (reg1) + (reg2)

ADD reg2, mem (reg2)  (reg2) + (mem)
ADD mem, reg1 (mem)  (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data

ADD A, data

ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16

11/12/2025 8086 Microprocessor 90

 Instruction Set
Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF

ADC A, data

ADC AL, data8 (AL)  (AL) + data8+CF

ADC AX, data16 (AX)  (AX) +data16+CF

11/12/2025 8086 Microprocessor 91

 Instruction Set
Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2)  (reg2) - (reg1)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data

SUB A, data

SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16

11/12/2025 8086 Microprocessor 92

 Instruction Set
Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2)  (reg2) - (reg1) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF

SBB A, data

SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF

11/12/2025 8086 Microprocessor 93

 Instruction Set
Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8)  (reg8) + 1

INC reg16 (reg16)  (reg16) + 1

INC mem (mem)  (mem) + 1

DEC reg/ mem

DEC reg8 (reg8)  (reg8) - 1

DEC reg16 (reg16)  (reg16) - 1

DEC mem (mem)  (mem) - 1

11/12/2025 8086 Microprocessor 94

 Instruction Set
Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
MUL reg/ mem
MUL reg For byte : (AX)  (AL) x (reg8)
For word : (DX)(AX)  (AX) x (reg16)

MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

IMUL reg/ mem

IMUL reg For byte : (AX)  (AL) x (reg8)
For word : (DX)(AX)  (AX) x (reg16)

IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

CBW: Convert Signed Byte to Word. The byte to be

converted is in AL and Result will be stored
in AX.

CWD: Convert Signed Word to Double word. Copies

the sign bit of AX to all the bits of DX. This
operation is required before signed division.

11/12/2025 8086 Microprocessor 95

 Instruction Set
Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL)  (AX) / (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) / (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

DIV mem For 16-bit :- 8-bit :

(AL)  (AX) / (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) / (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

11/12/2025 8086 Microprocessor 96

 Instruction Set
Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

IDIV reg/ mem

IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

IDIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

11/12/2025 8086 Microprocessor 97

 Instruction Set
Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags  (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags  (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags  (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

11/12/2025 8086 Microprocessor 98

 Instruction Set
Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags  (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags  (mem) – (data)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

11/12/2025 8086 Microprocessor 99

 Instruction Set
Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags  (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags  (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

11/12/2025 8086 Microprocessor 10

0
 Instruction Set
Logical Instructions
Mnemonics: AND, OR, XOR, TEST, NOT, SHR, SHL, RCR, RCL …

AND A, data

AND AL, data8 (AL)  (AL) & data8

AND AX, data16 (AX)  (AX) & data16

AND Reg / Mem, data

AND reg, data (Reg)  (Reg) & data

AND mem, data (mem)  (mem) & data

AND Reg / Mem, Reg/ Mem

AND reg2, reg1 (Reg2)  (Reg1) & (Reg2)

AND reg, mem (reg)  (mem) & (reg)
AND mem, reg (mem)  (mem) & (reg)

11/12/2025 8086 Microprocessor 10

1
 Instruction Set
Logical Instructions
Mnemonics: AND, OR, XOR, TEST, NOT, SHR, SHL, RCR, RCL …

OR A, data

OR AL, data8 (AL)  (AL) | data8

OR AX, data16 (AX)  (AX) | data16

OR Reg / Mem, data

OR reg, data (Reg)  (Reg) | data

OR mem, data (mem)  (mem) | data

OR Reg / Mem, Reg/ Mem

OR reg2, reg1 (Reg2)  (Reg1) | (Reg2)

OR reg, mem (reg)  (mem) | (reg)
OR mem, reg (mem)  (mem) | (reg)

11/12/2025 8086 Microprocessor 10

2
 Instruction Set
Logical Instructions
Mnemonics: AND, OR, XOR, TEST, NOT, SHR, SHL, RCR, RCL …

XOR A, data

XOR AL, data8 (AL)  (AL) ^ data8

XOR AX, data16 (AX)  (AX) ^ data16

XOR Reg / Mem, data

XOR reg, data (Reg)  (Reg) ^ data

XOR mem, data (mem)  (mem) ^ data

XOR Reg / Mem, Reg/ Mem

XOR reg2, reg1 (Reg2)  (Reg1) ^ (Reg2)

XOR reg, mem (reg)  (mem) ^ (reg)
XOR mem, reg (mem)  (mem) ^ (reg)

11/12/2025 8086 Microprocessor 10

3
 Instruction Set
Logical Instructions
Mnemonics: AND, OR, XOR, TEST, NOT, SHR, SHL, RCR, RCL …

TEST A, data

TEST AL, data8 Modify flags  (AL) & data8

TEST AX, data16 Modify flags  (AX) & data16

TEST Reg / Mem, data

TEST reg, data Modify flags  (Reg) & data

TEST mem, data Modify flags  (mem) & data

TEST Reg / Mem, Reg/ Mem

TEST reg2, reg1 Modify flags  (Reg1) & (Reg2)

TEST reg, mem Modify flags  (mem) & (reg)
TEST mem, reg Modify flags  (mem) & (reg)

11/12/2025 8086 Microprocessor 10

4
 Instruction Set
Logical Instructions
Mnemonics: AND, OR, XOR, TEST, NOT, SHR, SHL, RCR, RCL …

NOT Reg / Mem

NOT reg reg  Complement of reg

NOT mem (mem)  complement of (mem)

11/12/2025 8086 Microprocessor 10

5
 Instruction Set
Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

11/12/2025 8086 Microprocessor 10

6
 Instruction Set
Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

11/12/2025 8086 Microprocessor 10

7
 Instruction Set
Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

11/12/2025 8086 Microprocessor 10

8
 Instruction Set
Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, ROL …

11/12/2025 8086 Microprocessor 10

9
 Instruction Set
Processor Control Instructions
Mnemonics Explanation
STC Set CF  1

CLC Clear CF  0

CMC Complement carry CF  CF/

STD Set direction flag DF  1

CLD Clear direction flag DF  0

STI Set interrupt enable flag IF  1

CLI Clear interrupt enable flag IF  0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a coprocessor

which shares the address and data bus
with the 8086

LOCK
11/12/2025 Lock
8086 bus during next instruction
Microprocessor 11
0
 Instruction Set
Control Transfer Instructions
❑ 8086 conditional branch instructions affecting individual flags

Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, Z = 1

JNZ disp8 Jump if result is not zero, i.e, Z = 1

11/12/2025 8086 Microprocessor 91

111
 Instruction Set
Control Transfer Instructions
Name Alternate name Name Alternate name
JE disp8 JZ disp8 JA disp8 JNBE disp8
Jump if equal Jump if result is 0 Jump if above Jump if not below
or equal
JNE disp8 JNZ disp8
JAE disp8 JNB disp8
Jump if not equal Jump if not zero
Jump if above or Jump if not below
JG disp8 JNLE disp8 equal
Jump if greater Jump if not less or
JB disp8 JNAE disp8
equal
Jump if below Jump if not above
JGE disp8 JNL disp8 or equal
Jump if greater Jump if not less
than or equal
JBE disp8 JNA disp8
JL disp8 JNGE disp8 Jump if below or Jump if not above
Jump if less than Jump if not equal
greater than or
equal
JLE disp8 JNG disp8
Jump if less than Jump if not
or equal greater

11/12/2025 8086 Microprocessor 90

112
 Instruction Set
String Manipulation Instructions

❑ String : Sequence of bytes or words

❑ 8086 instruction set includes instruction for string movement, comparison,

scan, load and store.

❑ REP instruction prefix : used to repeat execution of string instructions

❑ String instructions end with S or SB or SW.

S represents string, SB string byte and SW string word.

❑ Offset or effective address of the source operand is stored in SI register and

that of the destination operand is stored in DI register.

❑ Depending on the status of DF, SI and DI registers are automatically

updated.

❑ DF = 0  SI and DI are incremented by 1 for byte and 2 for word.

❑ DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

11/12/2025 8086 Microprocessor 11

3
 Instruction Set
String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE)  (MA)

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1

If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

MOVSW MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1)  (MA; MA + 1)

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2

If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2

11/12/2025 8086 Microprocessor 11

4
 Instruction Set
String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
Compare two string byte or string word

CMPS

CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

Modify flags  (MA) - (MAE)

If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
CMPSW If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

For word operation

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2
If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2

11/12/2025 8086 Microprocessor 11

5
 Instruction Set
String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
Scan (compare) a string byte or word with accumulator

SCAS

SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)

If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0

If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

SCASW MAE = (ES) x 1610 + (DI)

Modify flags  (AX) - (MAE)

If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 2

11/12/2025 8086 Microprocessor 84
116
If DF = 1, then (DI)  (DI) – 2
 Instruction Set
String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to AX

LODS

LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)

If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1

LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)

If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2

11/12/2025 8086 Microprocessor 11

7
 Instruction Set
String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to string

STOS

STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

STOSW MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1 )  (AX)

If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2

11/12/2025 8086 Microprocessor 11

8
 Instruction Set
String Manipulation Instructions
Mnemonics: MOVS, CMPS, SCAS, LODS, STOS, REP

REP

REPZ/ REPE While CX  0 and ZF = 1, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) – 1
ZF = 0)

REPNZ/ REPNE While CX  0 and ZF = 0, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) - 1
ZF = 1)

11/12/2025 8086 Microprocessor 11

9
 Instruction Set
Control Transfer Instructions
Transfer the control to a specific destination or target instruction
Do not affect flags

❑ 8086 Unconditional transfers

Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

11/12/2025 8086 Microprocessor 12

0
 Instruction Set
Control Transfer Instructions
❑ 8086 signed conditional ❑ 8086 unsigned conditional
branch instructions branch instructions

Checks flags

If conditions are true, the program control is

transferred to the new memory location in the same
segment by modifying the content of IP

11/12/2025 8086 Microprocessor 12

1
 Largest Number
MOV SI, 5000 MOV AL, [SI]
Find the largest no. from the
MOV CL, [SI] data array. Size of the data array
SVEC: INC SI
is stored at F000H:5000H. The
MOV CH, 00 LOOP SVEW
starting address of the data
array is F000H:5001H.
INC SI MOV [6000], AL Store the largest number at
F000H:6000H.
MOV AL, [SI] HLT

DEC CL

INC SI

SVEW : CMP AL,[SI]

JNC SVEC

11/12/2025 8086 Microprocessor 122

 Smallest Number
MOV SI, 5000 MOV AL, [SI]
Find the smallest no. from a
MOV CL, [SI] data array. Size of the data array
SVEC: INC SI
is stored at F000H:5000H. The
MOV CH, 00 LOOP SVEW
starting address of the data
array is F000H:5001H.
INC SI MOV [6000], AL Store the largest number at
F000H:6000H.
MOV AL, [SI] HLT

DEC CL

INC SI

SVEW : CMP AL,[SI]

JC SVEC

11/12/2025 8086 Microprocessor 123

 Factorial
Find the factorial of a 16-bit no.
MOV CX, [5000] stored at F000H:5000H. Store
the 32-bit result at F000H:6000H
MOV AX, 0001 and F000H:6002H.

MOV DX, 0000

SVEW: MUL CX

LOOP SVEW

MOV [6000], AX

MOV [6002], DX

HLT
11/12/2025 8086 Microprocessor 124
 Assembler Directives

Instructions to the Assembler regarding the program being

executed.

Control the generation of machine codes and organization of

the program; but no machine codes are generated for
assembler directives.

Also called ‘pseudo instructions’

Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..

11/12/2025 8086 Microprocessor 93

125
 Assembler Directives
DB Define Byte

DW Define a byte type (8-bit) variable

SEGMENT Reserves specific amount of memory

ENDS locations to each variable

ASSUME Range : 00H – FFH for unsigned value;

00H – 7FH for positive value and
ORG 80H – FFH for negative value
END
EVEN General form : variable DB value/ values
EQU

PROC
FAR Example:
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for
SHORT the variable LIST and each data specified in the
instruction are stored as initial value in the reserved
MACRO memory location
ENDM
11/12/2025 8086 Microprocessor 12
6
 Assembler Directives
DB Define Word

DW Define a word type (16-bit) variable

SEGMENT Reserves two consecutive memory locations

ENDS to each variable

ASSUME Range : 0000H – FFFFH for unsigned value;

0000H – 7FFFH for positive value and
ORG 8000H – FFFFH for negative value
END
EVEN General form : variable DW value/ values
EQU

PROC
FAR Example:
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for
SHORT the variable ALIST and each 16-bit data specified in
the instruction is stored in two consecutive memory
MACRO location.
ENDM
11/12/2025 8086 Microprocessor 12
7
 Assembler Directives
DB SEGMENT : Used to indicate the beginning of
a code/ data/ stack segment
DW
ENDS : Used to indicate the end of a code/
SEGMENT data/ stack segment
ENDS
General form:
ASSUME

ORG
END Segnam SEGMENT
EVEN
…
EQU … Program code
… or
PROC … Data Defining Statements
…
FAR …
NEAR
ENDP Segnam ENDS

SHORT

MACRO User defined name of

the segment
ENDM
11/12/2025 8086 Microprocessor 96
128
 Assembler Directives
DB Informs the assembler the name of the
program/ data segment that should be used
DW for a specific segment.

SEGMENT General form:

ENDS
ASSUME segreg : segnam, .. , segreg : segnam
ASSUME

ORG
User defined name of
END Segment Register
the segment
EVEN
EQU

PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the
ENDP instructions of the program are
stored in the segment ACODE and
data are stored in the segment
SHORT ADATA

MACRO
ENDM
11/12/2025 8086 Microprocessor 97
129
 Assembler Directives
ORG (Origin) is used to assign the starting address
DB
(Effective address) for a program/ data segment

DW END is used to terminate a program; statements

after END will be ignored
SEGMENT
ENDS EVEN : Informs the assembler to store program/
data segment starting from an even address
ASSUME
EQU (Equate) is used to attach a value to a variable

ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements
EQU following ORG 1000H should be stored in
memory starting with effective address
1000H
PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of
SHORT ORG 1200H memory location assigned to A will be 1200H
A DB 4CH and that of B will be 1202H and 1203H.
EVEN
MACRO B DW 1052H
ENDM
11/12/2025 _SDATA ENDS 8086 Microprocessor 98
130
 Assembler Directives
PROC Indicates the beginning of a procedure
DB
ENDP End of procedure
DW
FAR Intersegment call
SEGMENT
ENDS NEAR Intrasegment call

General form
ASSUME

ORG
procname PROC[NEAR/ FAR]
END
EVEN …
… Program statements of the
EQU procedure
…

PROC RET Last statement of the

procedure
ENDP
FAR procname ENDP
NEAR

SHORT User defined name of

the procedure
MACRO
ENDM
11/12/2025 8086 Microprocessor 99
131
 Assembler Directives
DB
Examples:
DW

SEGMENT ADD64 PROC NEAR The subroutine/ procedure named ADD64 is

ENDS declared as NEAR and so the assembler will
… code the CALL and RET instructions involved
… in this procedure as near call and return
ASSUME …

ORG RET
ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT
is declared as FAR and so the assembler will
… code the CALL and RET instructions involved
PROC … in this procedure as far call and return
ENDP …
FAR
NEAR RET
CONVERT ENDP

SHORT

MACRO
ENDM
11/12/2025 8086 Microprocessor 100
132
 Assembler Directives
DB Reserves one memory location for 8-bit
signed displacement in jump instructions
DW
Example:
SEGMENT
ENDS

ASSUME JMP SHORT The directive will reserve one

AHEAD memory location for 8-bit
ORG displacement named AHEAD
END
EVEN
EQU

PROC
ENDP
FAR
NEAR

SHORT

MACRO
ENDM
11/12/2025 8086 Microprocessor 101
133
 Assembler Directives
DB MACRO Indicate the beginning of a macro

DW ENDM End of a macro

SEGMENT General form:

ENDS

ASSUME macroname MACRO[Arg1, Arg2 ...]

Program
… statements in
ORG
… the macro
END …
EVEN
EQU macroname ENDM

PROC
ENDP
FAR User defined name of
NEAR the macro

SHORT

MACRO
ENDM
11/12/2025 8086 Microprocessor 102
134
 ASCENDING ORDER

MOV SI, 5000H

XCHG AL, [SI]

DEC SI
MOV CL, [SI]

DEC CL XCHG AL, [SI]

EEE: MOV SI, 5000H INC SI

MOV CH, [SI] SVEW: DEC CH

DEC CH
JNZ VEMU
INC SI
DEC CL
VEMU: MOV AL, [SI]
JNZ EEE
INC SI
HLT
CMP AL, [SI]

JC SVEW

11/12/2025 8086 Microprocessor 135

 DESCENDING ORDER
MOV SI, 5000H
XCHG AL, [SI]

DEC SI
MOV CL, [SI]

DEC CL XCHG AL, [SI]

EEE: MOV SI, 5000H INC SI

MOV CH, [SI] SVEW: DEC CH

DEC CH
JNZ SVEC
INC SI
DEC CL
SVEC: MOV AL, [SI]
JNZ EEE
INC SI
HLT
CMP AL, [SI]

JNC SVEW

11/12/2025 8086 Microprocessor 136

 Fibonacci sequence

MOV AL, 00H

MOV SI, 5000H

ADD SI, 01H

MOV [SI], AL
MOV [SI], AL
ADD SI, 01H
LOOP L1
ADD AL, 01H
HLT
MOV [SI], AL

SUB CX, 0002H

L1: MOV AL, [SI-1]

ADD AL, [SI]

11/12/2025 8086 Microprocessor 137

 Fibonacci sequence

MOV AL, 00H

MOV SI, 5000H

ADD SI, 01H

MOV [SI], AL
MOV [SI], AL
ADD SI, 01H
LOOP L1
ADD AL, 01H
HLT
MOV [SI], AL

SUB CX, 0002H

L1: MOV AL, [SI-1]

ADD AL, [SI]

11/12/2025 8086 Microprocessor 138

 STRING MANIPULATION – MOVE

MOV CL,05H
MOV SI,1100H
MOV DI,1200H
CLD
L1 MOVSB
LOOP L1
HLT

11/12/2025 8086 Microprocessor 139

 Interrupts of 8086

• An interrupt is an external or internal signal that breaks

the normal sequence of execution of instructions,
diverts its execution to some other program called
“Interrupt Service Routine (ISR).

• At the end of each instruction cycle the 8086 checks to

see if any interrupts have been requested .

• After executing ISR, the control is transferred back

again to the main program which was being executed at
the time of interruption.

11/12/2025 8086 Microprocessor 140

 Interrupts of 8086
• There are two types of interrupts

➢ Hardware interrupts: These interrupts are

generated by external devices i.e outside the
processor (using NMI, INTR pins). Eg: Keyboard
interrupt.

➢ Software interrupts: It is generated internally by

the process circuit or by the execution of an
interrupt instruction. Eg: INT instruction,
overflow interrupt, divide by zero.

11/12/2025 8086 Microprocessor 141

 Hardware Interrupts of 8086
➢ NMI : Non Maskable Interrupt input pin which
means that any interrupt request at NMI input
cannot be masked or disabled by any means. it is
of type 2 interrupt
➢ When this interrupt is activated, these following
actions take place
• Completes the current instruction that is in progress.
• Pushes the Flag register values on to the stack.
• Pushes the CS (code segment) value and IP
(instruction pointer) value of the return address on
to the stack.
• IP is loaded from the contents of the word location
00008H.
• CS is loaded from the contents of the next word
location 0000AH.
• Interrupt flag and trap flag are reset to 0.
11/12/2025 8086 Microprocessor 142
 Hardware Interrupts of 8086
➢ INTR: The INTR is a maskable interrupt because the
microprocessor will be interrupted only if interrupts are
enabled using set interrupt flag instruction.

➢ The INTR interrupt is activated by an I/O port. If the

interrupt is enabled and NMI is disabled, then the
microprocessor first completes the current execution and
sends ‘0’ on INTA pin twice. The first ‘0’ means INTA
informs the external device to get ready and during the
second ‘0’ the microprocessor receives the 8 bit.
➢ These actions are taken by the microprocessor
• First completes the current instruction.
• Activates INTA output and receives the interrupt type, say X.
• Flag register value, CS value of the return address and IP value
of the return address are pushed on to the stack.
• IP value is loaded from the contents of word location X × 4
CS is loaded from the contents of the next word location.
• Interrupt flag and trap flag is reset to 0

11/12/2025 8086 Microprocessor 143

 Interrupt Vector table of 8086

➢ The first 1Kbyte of memory of 8086 (00000 to

003FF) is set aside as a table for storing the starting
addresses of Interrupt Service Procedures (ISP).

➢ Since 4-bytes are required for storing starting

addresses of ISPs, the table can hold 256 Interrupt
procedures.

➢ The starting address of an ISP is often called the

Interrupt Vector or Interrupt Pointer. Therefore,
the table is referred as Interrupt Vector Table.

➢ In this table, IP value is put in as low word of the

vector & CS is put in high vector.
11/12/2025 8086 Microprocessor 144
 Interrupt Vector table of 8086

11/12/2025 8086 Microprocessor 145

 Software Interrupts
➢ INT N- Interrupt instruction with type number
It is 2-byte instruction. First byte provides the op-code
and the second byte provides the interrupt type number.

➢ There are 256 interrupt types under this group.

Its execution includes the following steps −
▪ Flag register value is pushed on to the stack.
▪ CS value of the return address and IP value of the
return address are pushed on to the stack.
▪ IP is loaded from the contents of the word location
‘type number’ × 4
▪ CS is loaded from the contents of the next word
location.
▪ Interrupt Flag and Trap Flag are reset to 0

11/12/2025 8086 Microprocessor 146

 Software Interrupts
▪ TYPE 0 interrupt represents division by zero
situation.
▪ TYPE 1 interrupt represents single-step execution
during the debugging of a program.
▪ TYPE 2 interrupt represents non-maskable NMI
interrupt.
▪ TYPE 3 interrupt represents break-point interrupt.
▪ TYPE 4 interrupt represents overflow interrupt.
▪ The interrupts from Type 5 to Type 31 are
reserved for other advanced microprocessors
▪ Interrupts from 32 to Type 255 are available for
hardware and software interrupts.

11/12/2025 8086 Microprocessor 147

 Software Interrupts
➢ INT 3-Break Point Interrupt Instruction: 1-byte
instruction. These instructions are inserted into
the program so that when the processor reaches
there, then it stops the normal execution of
program and follows the break-point procedure.

➢ INTO - Interrupt on overflow instruction: 1-byte

conditional interrupt instruction, i.e. it is active
only when the overflow flag is set to 1 and
branches to the interrupt handler whose interrupt
type number is 4. If the overflow flag is reset
then, the execution continues to the next
instruction.

11/12/2025 8086 Microprocessor 148