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Outline
• Introduction
EE681A – Compact Modeling
Part 4: MOS-Capacitor • MOS Capacitor

Yogesh S. Chauhan
Department of Electrical Engineering
IIT Kanpur
Email: chauhan@[Link]
Book – Modern Semiconductor Devices for Integrated Circuits by Chenming C. Hu
Office: WL125, Phone: 7244

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What is MOSFET? Switch vs. MOSFET

IDS
• MOSFET is a transistor used for amplifying or
switching electronic signals. I
Gate
V VGS

Drain I I
OFF ON
OFF ON

Source VGS
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Invention of Transistor Invention of Point Contact Transistor

• Inventors
• First Transistor (1947-1948) at AT&T’s Bell Labs – Walter H. Brattain (1902–1987)
– Point Contact Transistor – John Bardeen (1908–1991)
– William B. Shockley (1910–1988)
– First transistor was bipolar contact transistor
– Material – Germanium

IEEE Spectrum, Dec. 2022

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C. Hu, Modern Semiconductor Device for Integrated Circuits

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Invention of Bipolar Junction Transistor

William Shockley
• Worked on theory of Diode, Transistor,
Thyristor etc.
• Invented First transistor at Bell Labs
• Received Nobel Prize in 1956
• Formed Shockley semiconductor in
Mountain View, California in 1956
– Employees of Shockley semiconductor
(Robert Noyce, Gordon Moore, ….)
– These employees opened 65 companies in
next 20 years including Intel, AMD, …

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Source: The Electrochemical Society Interface • Fall 2007

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Fairchild Semiconductor
• Shockley Semiconductor's
mismanagement involved an
authoritarian, paranoid style,
including psychological tests,
secretiveness, and focusing on his
pet project (the four-layer diode)
over commercial silicon
transistors, alienating his top
engineers.
• This led to the "Traitorous Eight"
leaving in 1957 to found Fairchild Source: The
Semiconductor, sparking the Electrochemical
growth of Silicon Valley. Society Interface •
Fall 2007
• Shockley's company struggled,
never turned a profit, and was
eventually sold, as.
Source: The Electrochemical Society Interface • Fall 2007
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Silicon Valley
• Started with Shockley Semiconductor in 1956

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Integrated Circuit (IC) Invention of Integrated Circuits

• Jack Kilby (at Texas Instruments) demonstrated first working IC in
• IC – Electronic circuit manufactured on the surface of a 1958.
thin substrate of semiconductor material. – Jack Kilby was awarded the Nobel Prize in Physics 2000.
– Kilby's work was named an IEEE Milestone in 2009.
• Additional materials are deposited and patterned to
form interconnections between semiconductor devices.
First IC First handheld Calculator

• Robert Noyce (at Fairchild Semiconductor) also invented IC separately

six months later than Kilby.
– It was made of silicon, whereas Kilby's chip was made of germanium.
• ICs are used in virtually all electronic equipment today – Fairchild Semiconductor was also home of the first silicon gate IC
technology with self-aligned gates, which stands as the basis of all modern
and have revolutionized the world of electronics. CMOS computer chips.
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Outline Why study MOS Capacitor?

• Introduction • MOS Capacitor works like heart of MOSFET.
• MOSFET is nothing but MOS capacitor with PN-
• MOS Capacitor junctions at two ends.

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Metal-Oxide-Silicon (MOS)
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capacitor
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Metal–Oxide–Semiconductor Field-
MOS Capacitor
Effect Transistor
• MOS Capacitor has three regions of operation:
• For better understanding of MOSFET, one must first be
familiar with structure and working of MOS capacitor. – Accumulation Region
– Depletion Region
– Inversion Region

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Energy Band Diagram of

Flat-band Condition & Flat-band Voltage
MOS Capacitor in Equilibrium
• The band is flat at flat band voltage.
• No net transfer of energy across any interface.
• No net charge transport across any interface.

E0 : Vacuum level
E0 – Ef : Work function V fb   g   s
E0 – Ec : Electron affinity
For more details – Check Tsividis book
Si/SiO2 energy barrier
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HW – Draw band diagram for different combinations.

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Surface Accumulation (Vg < Vfb ) Surface Accumulation is Surface potential

s

• Gate Voltage
• Negative Qg must be balanced
by a positive substrate charge. V g  V fb   s  V ox
• Voltage across Oxide negligible

• Holes accumulate at surface to V ox  V g  V fb   s

provide net positive charge.
 V g  V fb

• This condition is known as • Gauss’ Law

surface accumulation. E ox   Q acc /  ox
Vox  Eox * Tox  Qacc / Cox
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Accumulation charge
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Q acc   C ox (V g  V fb )
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Surface Depletion (Vg > Vfb) Surface Depletion

• Voltage across Oxide
• When Vg>Vfb, the positive Qdep qN aWdep qN a 2 s s
Vox    
potential at gate will simply C ox C ox C ox
drive holes away from the
surface.
• Applied Gate Voltage
• Surface get depleted by qNa 2s s
negative ionized ions. Vg Vfb s Vox Vfb s 
Cox
• This condition is called • Calculate s ?
surface depletion.
Depletion Region Charge Q
dep
 qN W
a dep
 2 qN  
a s s
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Threshold Condition and Threshold Voltage

Surface Inversion (Vg > >Vfb)
Threshold (of inversion):
ns = Na , or
• Electric field in depletion region (Ec–Ef)surface= (Ef – Ev)bulk , or
breaks covalent bonds.
 A=B, and C = D
• Electron goes towards surface and
hole goes towards substrate.

• Thus in MOS Capacitor, supply of

inversion charge is controlled by kT  N a 
substrate. st  2B  2 ln 
q  ni 
• This condition is called Surface
Inversion. Eg kT  N v  kT  N v  kT  N a 
q B   ( E f  Ev ) |bulk  ln  ln  ln 
2 q  ni  q  N a  q  ni 
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Threshold Voltage Threshold Voltage

Tox = 20nm

V t(V), N +gate/P-body

Vt (V), P+ gate/N-body
Vg  V fb φs Vox
At threshold,
kT  N a 
 st  2B  2 ln 
q  ni 

qN a 2 s 2B
Vox 
Cox
Body Doping Density (cm-3 )
qN a 2 s 2 B
Vt  Vg at threshold  V fb  2B  qN sub 2 s 2 B + for P-body,
Cox Vt  V fb  2 B  – for N-body
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Strong Inversion–Beyond Threshold

Inversion Layer Charge
Maximum Depletion Region Width
2 s 2B
• Applied Gate Voltage
Vg > Vt Wdep  Wdmax 
qN a Q dep Q inv
Vg > Vt Ec V g  V fb  2 B  
- C ox C ox
Ef
-- Ev qN a 2  s 2 B Q inv
gate ---
 V fb  2 B  
++++++++++ qVg C ox C ox
SiO2
- - - - - - - - Q inv
V - - - - - - - E c, Ef
 Vt 
C ox
Q dep Q inv
Ev
P - Si substrate

M O S
Inversion Layer Charge Qinv  Cox (Vg Vt )
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Choice of Vt and Gate Doping Type Surface Space-Charge Region

• The potential ψp(x) is defined as the potential Ei(x)/q
Vt is generally set at a small positive value with respect to the bulk of the semiconductor.
so that, at Vg = 0, the transistor does not
• At semiconductor surface, ψp(0)=ψs (surface potential).
have an inversion layer and current does
not flow between the two N+ regions
The inversion layer may be thought of
as a thin N-type layer.

• P-body is normally paired with N+-gate to

achieve a small positive threshold voltage.
• N-body is normally paired with P+-gate to
achieve a small negative threshold voltage.
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Surface Space-Charge Region Review: Basic MOS Capacitor Theory

• Mathematical • Surface potential
analysis gives
relation between – Negligible in accumulation
Qs and ψs. (HW – saturates at 2φB when Vg is larger than Vt
exercise)

• Different regions
– Accumulation
– Depletion
– Inversion

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Review: Basic MOS Capacitor Theory MOS CV Characteristics

Accumulation Charge • CV Measurement Setup

Depletion Charge dQg dQs

C 
dVg dVg
Total substrate charge Qsub (C/cm2),
is the sum of Qacc, Qdep, and Qinv.
Inversion
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MOS CV Characteristics Supply of Inversion Charge May be Limited

dQg dQs
C 
dVg dVg
Accumulation Depletion

Inversion in MOSFET Inversion in MOS Capacitor

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Quasi-Static CV of MOS Capacitor MOS CV – Frequency dependence

• The quasi-static CV is obtained by the application of a slow

linear-ramp voltage (< 0.1V/s) to the gate, while measuring Ig
with a very sensitive DC ammeter. C is calculated from Ig =
C·dVg/dt. This allows sufficient time for Qinv to respond to the
slow-changing Vg .
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MOS Capacitance in depletion Large Signal Deep Depletion

κox – relative permittivity of oxide

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x0 – oxide thickness

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Relaxation from Deep Depletion Low or High frequency?

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MOS CV – Insulator thickness dependence Silicon MOS Capacitor

• Vt decreases with decrease in oxide thickness.
• Metal-oxide-silicon (MOS) capacitor is by far the most
• Variation in capacitance increases. practical and important MIS system.
– The interface consists of single-crystal silicon followed by a
monolayer of SiO, that is, incompletely oxidized silicon, then a
thin strained region of SiO, and then SiO2.
– Interface traps and oxide charges affect the ideal MOS
characteristics.

(a) (b)
Si-SiO2 interface Current generation MOSFET
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Silicon MOS Capacitor Interface Traps

Classifications of traps and charges: also called interface states, fast states, or surface states
• Interface traps of density Dit, and trapped charges Qit • Qit exists within the forbidden gap due to the
– Located at the Si-SiO2 interface with energy states within the silicon forbidden
bandgap and can exchange charges with silicon in a short time. interruption of the periodic lattice structure at the
– Qit is also determined by the occupancy or the Fermi level so its amount is bias surface of a crystal.
dependent. Interface traps can possibly be produced by excess silicon (trivalent – Measurements on clean surfaces in an ultra-high-vacuum
silicon), broken Si-H bonds, excess oxygen and impurities.
system confirm that Qit can be very high-on the order of the
• Fixed oxide charges Qf density of surface atoms (=1015 atoms/cm2).
– Located at or near the interface and are
immobile under an applied electric • For the present MOS capacitors having thermally
field. grown SiO2 on Si, most of the interface-trapped charge
• Oxide trapped charges Qot can be neutralized by low-temperature (450C)
– Can be created, for example, by X-ray hydrogen annealing.
radiation or hot-electron injection;
these traps are distributed inside the – The total surface traps can be as low as 1010 cm-2, which
oxide layer. amounts to about one interface trap per 105 surface atoms.
• Mobile ionic charges Qm
– Such as sodium ions, which are mobile
within the oxide under bias-
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temperature stress conditions.
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Thermally oxidized silicon.

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Donor and Acceptor traps Total Interface Traps

Every interface has both kinds of traps.
• A convenient notation is to interpret the sum of these by an
• An interface trap is considered a donor if it is neutral and can equivalent Dit distribution, with an energy level called
become positively charged by donating (giving up) an electron. neutral level Eo above which the states are of acceptor type,
and below which are of donor type.
• An acceptor interface trap is neutral and becomes negatively • To calculate the trapped charge, it can also be assumed that
charged by accepting an electron. at room temperature, the occupancy takes on the value of 0
• The distribution functions (occupancy) for the interface traps are and 1 above and below EF. The Qit charges are
similar to those for the bulk impurity levels. the effective net
– Et, is the energy of the interface trap, and the ground-state degeneracy charges per unit area
is 2 for donor (gD) and 4 for acceptor (gA). (i.e., C/cm2).

For donor interface traps

For acceptor interface traps

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Ci – insulator capacitance
CD – depletion-layer capacitance

Interface-trap Density Distribution Low and High frequency limits

• Because interface-trap levels are distributed across the energy bandgap, they are
characterized by an interface-trap density distribution: • Low frequency: Rit is set to zero and CD is in parallel to Ci.
𝐷 = Number of traps/cm2-eV
• High frequency: Cit-Rit branch is ignored or open.
– When a voltage is applied, the Fermi level moves up or down with respect to the
interface-trap levels and a change of charge in the interface traps occurs. – The traps are not fast enough to respond to the fast signal.
– Interface-trap lifetime τit=CitRit which determines the frequency behavior of the
interface traps.
– Cit and Rit are the capacitance and resistance associated with the interface traps and, • The total terminal capacitance for these two cases are
thus, are also functions of energy.

These equations and equivalent circuits are useful in the measurement of interface traps.
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Measurement of Interface Traps Measurement of Interface Traps

• Both the input conductance and the input capacitance of the • Curves are stretched out in the
equivalent circuit contain similar information about the voltage direction.
interface traps. – This is due to the fact that extra
charge has to fill the traps, so it
– Either capacitance measurement or conductance measurement takes more total charge or applied
can be used to evaluate the interface-trap density. voltage to accomplish the same ψs
(or band bending).
– The ψs-V curve can be used to
• Conductance technique can give more accurate results, determine Dit.
especially for MOS capacitors with relatively low interface-
trap density (=1010 cm-2-eV-1).
• Gap in capacitance between the LF
and HF curves, before the point of
• The capacitance measurement, however, can give rapid Vmin near strong inversion is
evaluation of flat-band shift and the total interface-trapped proportional to Dit.
charge.
Homework – Read measurement
techniques ([Link])
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References
• Chenming Hu, “Modern Semiconductor
Devices for Integrated Circuits”, Prentice
Hall

• Yannis Tsividis and Colin McAndrew,

“Operation and Modeling of the MOS
Transistor”, Oxford Univeristy Press

• Simon M. Sze, “Physics of

Semiconductor Devices”, WILEY

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