VLSI TESTING
DESIGN FOR TESTABILITY
FAULT DETECTION TECHNIQUES
DEFINITION OF TESTING
a Testing in its broadest sense means to examine a product
and to ensure that it functions and exhibits the properties
and capabilities that it was designed to possess.
a Main purpose of testing is to detect malfunctions in the
product hardware and to locate their causes so that they
may be eliminated.
§
OtbT : object to be tested
DUT : device under test
CUT : circuit under test
Ls : Latches
CN : Combinational Networks
CONVENTIONAL TEST
METHODS
These rely primarily on mechanical means and not on use
of additional circuits in an otbT for the purpose of
facilitating its testing. Examples include use of extra I/O
for additional test points, improvement of test features.
Characteristics:
a They are used for testing system parts only outside the
system.
a They rely on feeding signals directly through the test
interface during listing.
a They rely on the use of tester-driven timing.
DIFFICULTIES IN TESTING
a Shortage of I/O points.
a Signal distortions in interface connections.
a Noise disturbances.
a Uncertainties in input feeding.
a Uncertainties in output sensing. (Rejection of good parts
reduces apparent yield.)
a Difficulty in synchronizing test objects timing with tester
timing.
a High costs for test equipment ,test generation and
execution.
a Large volume of data to be processed.
FAULTS
ë
FAULT DEFINITION
In any circuit composed of logic gates, there is
the possibility of the occurrence of a fault. A fault
is defined to have occurred when a circuit variable
assumes a value(1,0 or X) which differs from that
expected that is violates the original circuit
equation.
Fault Types:
a SAO : Stuck at µ0¶ (short with ground rail)
a SA1 : Stuck at µ1¶ (short with Vdd)
FAULT TYPES AND
MODELS
Examples of physical defects include
a Defects in silicon substrate.
a Photolithographic defects.
a Mask contamination and scratches.
a Process variation and abnormalities.
a Oxide defects.
Õ
Shorts, opens, transistor stuck-on or stuck-off, Resistive
shorts and opens, Excessive change in threshold voltage
and excessive change in steady state currents.
ÑINDS OF FAULTS
a Single faults
a Multiple faults.
CIRCUIT FOR AO1
Õ
ÑINDS OF FAULTS
a Single faults
a Multiple faults.
No of single fault locations : 7
No of single faults : 2 * 7 = 14
No of double fault combs. : 2 * 2 * 7C2 = 84
Fault combinations are not unique. A test for SA0
at x1 also covers SA0 at x5 and x7.
FAULT EQUIVALENCES
a One or more inputs to an OR gate at SA1 is
equivalent to an OR gate whose output is at SA1.
a One or more inputs to an AND gate at SA0 is
equivalent to an AND gate whose output is at
SA0.
a All inputs to an OR gate at SA0 is equivalent to an
OR gate whose output is at SA0.
a All inputs to an AND gate at SA1 is equivalent to
an AND gate whose output is at SA1.
Thus any gate output fault has an equivalent single
stuck fault or multiple stuck fault.
MASÑING OF FAULTS
Definition:
Let Tg be a test that detects a fault g. We
can say that a fault f functionally masks the
fault g iff the multiple faults (f,g) is not
detected by any test in Tg.
SINGLE STUCÑ FAULT
MODEL
Single stuck-fault model (SSF) is the classical
or standard fault model. Its usefulness results
from the following attributes:
a it presents many different physical faults;
a it is independent of technology;
a compared to other fault models, the number
of SSFs in a circuit is small;
a SSFs can be used to model other type of
faults.
AND-NAND BLOCÑ
X=AND(A,B,C,D) Y=NAND(A,B,C,D)
A B C D X Y
A sa0 1 1 1 1 1 0
A sa1 0 1 1 1 0 1
B sa0 1 1 1 1 1 0
B sa1 1 0 1 1 0 1
C sa0 1 1 1 1 1 0
C sa1 1 1 0 1 0 1
D sa0 1 1 1 1 1 0
D sa1 1 1 1 0 0 1
The test sequence can thus be obtained by finding
out the combinations.
Complementary circuits can be tested in the
similar fashion.
For a single stack model containing N nodes,
where in each node can be in one of the 3 states
(good,SA0,SA1) 3N combinations are possible.
For N=100 we get 5.1047 combinations which is a
very large data to process.
EXISTENCE FUNCTION
Developing a test sequence:
x6=x3.x4
x5=x1.x2
x7=x5+x6
Rules for labeling the nodes:
a Primary inputs are labeled with the lowest indexed
variables.
a Fan outs are labeled separately.
CIRCUIT FOR AO1
Õ
EQUATIONS
Fi(x0,x1«.xp)=Gi(xo,x1«.xp)
F=G
ÊF.G +ÊG.F = 0
where F is the set of inputs and G is the set of outputs.
F G
x1.x2 x5
x3.x4 x6
x5+x6 x7
ÊF.G : x5¶x1x2 x6¶x3x4 x7¶x5 x7¶x6
AG.F : x5x1¶ x6x3¶ x5x2¶ x6x4¶ x7x6¶x5¶
EXISTENCE FUNCTION
GENERATOR
Mark all the points which are covered by
at least one of the terms. Instead of 7
variable Ñ map use a Marquand chart.
After cancellation, take the remaining
points. These are the ones in the existence
function circuit. ( No of ones = 16).
Move from one point to a place where
there is a change in output.
Longest chain will produce the desired test
sequence. The complete test sequence is
5-7-6-14-10-11-9-13-5.
Each of the input variables is tested independently
for a change in value from 0 to 1 and again from 1
to 0. Each of the intermediate variable is also
tested in the process.
Each output variable is thereby tested for its
ability to change value from a 1 to 0 and from a 0
to 1.
ADVANTAGES OF TEST
SEQUENCES
a Test sequence can be produced by a hardware unit
instead of the usual software unit.
a Continuous resetting between tests is not
necessary.
a Since at least one of the outputs change on the
application of an input, detection of a failure is
logically straightforward.
a The test sequence covers all detectable single
faults.
a The test sequence is closed i.e it returns to the
initial state. This helps in reducing resetting.
DRAWBACÑS OF SINGLE
STACÑ FAULT MODEL
Does not take into account other kinds of
faults such as
a AC-faults.
a Bridging circuits.
a Faults in CMOS circuits.
a Multiple faults simultaneously presented in
the system.
DESIGN FOR
TESTABILITY
Testable means capable of being ascertained as
being fault free or not.
The aim of testability is to make the parts testable
not only on test fixtures separately from the
system but also within the system when the parts
are connected.
It should also include diagnosability i.e the
capability of locating faults at least down to the
smallest repair-replaceable unit
THREE ÑEY FUNCTIONS
a Control
Setting the conditions for the tests so that stimuli can
be supplied to the object to be tested.
a Observation
Obtaining the response to the stimuli so that the
behavior can be evaluated.
a Isolation
Making the control and observation possible and
more reliable.
TECHNIQUES
a Ad-hoc Testable Design Techniques
a Initialize sequential circuit
a Avoid redundancy logic
a Avoid asynchronous logic
a Avoid redundant circuits.
a Built in Self Testing. (BIST)
AD-HOC DESIGN
The three main features are
a Partition and Multiplexer techniques.
a Use of switches
Ex: For a 32 bit counter checking is very
difficult. But if we have sub-circuits ,testing
will be easier.
Switches will be placed throughout.
PARTITION TECHNIQUE
BUILT IN SELF
TECHNIQUES
In built-in-self-techniques (BIST) parts of the
circuits are used to test the circuit itself. On line
BIST is used to perform test under normal
operation where as off line BIST for testing
offline.
Components:
a Pseudo Random Pattern Generator (PRPG)
a Output Random Analyzer (ORA)
BUILT IN SELF TEST
OUTPUT RANDOM
ANALYZER
Cyclic Redundancy Check
G(x) = Q(x) P(x) + R(x)
where P(x) is the characteristic polynomial (output of the
CUT).
R(x) is the remainder and Q(x) is the quotient.
P(x) = x^5 + x^4 + x^2 + 1
G(x) with the sequence {1 1 1 1 0 1 0 1}
G(x) = x^7 + x^6 + x^5 + x^4 + x^2 + 1 and
R(x) = x^4 + x^2 which corresponds to the register(0 0 1 0
1)
The on chip storage of a fault dictionary
containing all the test inputs with the
corresponding outputs is prohibitively
expensive in terms of the chip area.
Alternative is to compare the outputs of 2
identical circuits for the same inputs
assuming that the probability that the two
devices will have the same kind of faults is
less.
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