8085 ARCHITECTURE

Niraj Khadka
8085 Registers
• Accumulator
• 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE
operations. It is connected to internal data bus & ALU.
• General Purpose Registers
• 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each
register can hold 8-bit data.
• These registers can work in pair to hold 16-bit data and their pairing
combination is like B-C, D-E & H-L.

Niraj Khadka
8085 Registers
• Program Counter
• 16-bit register used to store the memory address location of the next instruction
to be executed.
• Microprocessor increments the program counter whenever an instruction is
being executed, so that the program counter points to the memory address of
the next instruction that is going to be executed.
• Stack Pointer
• 16-bit register works like stack, which is always incremented/decremented by 2
during push & pop operations.
• Temporary Register
• 8-bit register, which holds the temporary data of arithmetic and logical
operations.
Niraj Khadka
Unit 2: Basic Computer Architecture
• 8085 Microprocessor Architecture and Operations
• Address, Data And Control Buses
• Internal Data Operation and Registers
• Externally Initiated Operations
• Addressing Modes
• Memory and Memory Operations
• Flag and Flag Register
• 8085 Pin Diagram and Functions
• Multiplexing and De-multiplexing of address/data bus
• Generation Of Control Signals

Niraj Khadka
Unit 2: Basic Computer Architecture
• 8086 Microprocessor
• Logical Block Diagram
• Segment Registers,
• Memory Segmentation
• Bus Interface Unit and Execution Unit
• Pipelining

Niraj Khadka
Flags
• CY => If the last operation generates a carry its status will 1 otherwise 0. It can
handle the carry or borrow from one word to another.
• P => If the result of the last operation has even number of 1’s (even parity), its
status will be 1 otherwise 0.
• AC => If the last operation generates a carry from the lower half word (lower
nibble), its status will be 1 otherwise 0. Used for performing BCD arithmetic.
• Z = > If the result of last operation is zero, its status will be 1 otherwise o. It is
often used in loop control and in searching for particular data value.

• S => If the most significant bit (MSB) of the result of the last operation is 1
(negative), then its status will be 1 otherwise 0.
Niraj Khadka
INTEL 8085 microprocessor
• 8-bit data bus
• 16-bit address bus, which can address upto 64KB
• A 16-bit program counter
• A 16-bit stack pointer
• Six 8-bit registers arranged in pairs: BC, DE, HL
• Requires +5V supply to operate at 3.2 MHZ single phase clock

Niraj Khadka
8085 Registers
• Flag Register
• 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending
upon the result stored in the accumulator.
• These are the set of 5 flip-flops −
• Sign (S)
• Zero (Z)
• Auxiliary Carry (AC)
• Parity (P)
• Carry (C)

Niraj Khadka
8085 Registers
• Instruction Register
• 8-bit register
• When an instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder then decodes the information
present in the Instruction register.

Niraj Khadka
• Interrupt Control
• Control interrupt during a process.
• 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP.
• Serial I/O control
• It controls the serial data communication by using these two instructions: SID
(Serial input data) and SOD (Serial output data).

Niraj Khadka
8085 Functional Units
• Address buffer and Address data-buffer
• content stored in the stack pointer and program counter is loaded into the
address buffer and address-data buffer to communicate with the CPU.
• memory and I/O chips are connected to these buses; the CPU can exchange
the desired data with the memory and I/O chips.
• Address Bus and Data Bus
• Data bus carries the data to be stored. It is bidirectional.
• Address bus carries the location to where it should be stored and it is
unidirectional.

Niraj Khadka
8085 Pin Diagram

Niraj Khadka
Details of the 8085 Pins
• A8 – A15
• it carries the most significant 8-bits of memory/IO address.
• AD0 – AD7
• It is a multiplexed bus consisting of least significant 8-bit of memory I/O
address as well as 8bit data bus.
• Control and Status Signals
• Used to identify the nature of operation.
• RD’, WR’, ALE control signal
• IO/M, S0, and S1

Niraj Khadka
Status Signals Meaning

Niraj Khadka
Details of the 8085 Pins
• Power Supply
• VCC indicates +5v power supply and VSS indicates ground signal.
• Clock Signal
• X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to
set frequency of the internal clock generator. This frequency is internally
divided by 2.
• CLK OUT − This signal is used as the system clock for devices connected with
the microprocessor.

Niraj Khadka
Externally initiated signal pins of 8085
• INTA − It is an interrupt acknowledgment signal.
• RESET IN − This signal is used to reset the microprocessor by setting the program
counter to zero.
• RESET OUT − This signal is used to reset all the connected devices when the
microprocessor is reset.
• READY − This signal indicates that the device is ready to send or receive data. If
READY is low, then the CPU has to wait for READY to go high.
• HOLD − This signal indicates that another master is requesting the use of the
address and data buses.
• HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD
request and it will relinquish the bus in the next clock cycle. HLDA is set to low after
the HOLD signal is removed.
Niraj Khadka
Details of the 8085 Pins
• Interrupt pins
• There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
• 2 serial signals, i.e. SID and SOD and these signals are used for serial
communication.
• SOD (Serial output data line) − The output SOD is set/reset as specified by the
SIM instruction.
• SID (Serial input data line) − The data on this line is loaded into accumulator
whenever a RIM instruction is executed.

Niraj Khadka
Externally Initiated Operations
• 8085 microprocessor support some Externally initiated operations,
which are also known as Peripheral operations.
• Different external input/output devices or signals can initiate these
types of operations. In 8085 microprocessor chip, their individual pins
are assigned for externally initiated operations.
• RESET
• Interrupt
• READY
• HOLD

Niraj Khadka
Externally Initiated Operations
• RESET
• This RESET key is used to clear the program counter and update it with 0000H
memory location.
• When this RESET pin is activated by any external key, then all the internal
operations are suspended for that time. After that the execution of the
program can begin at the zero memory address.
• There should be some code at the 0000H location which is generally
contained in a EEPROM wired physically at that location.

Niraj Khadka
Externally Initiated Operations
• Interrupt:
• 8085 microprocessor chip have some pins for interrupt like TRAP, RST 5.5, RST
6.5 and RST 7.5.
• TRAP is highest priority while RST 5.5, RST 6.5 and RST 7.5 are vectored
interrupt.
• TRAP is non-maskable while others are maskable.
• The microprocessor can be interrupted from the normal instructions and
asked to perform some other emergency operations, which are also known as
Service routine.
• The microprocessor resumes its operation after the completion Service
routine.

Niraj Khadka
Externally Initiated Operations
• READY
• The 8085 microprocessor has a pin called READY.
• If the signal at this READY pin is in low state then the microprocessor enters
into the Wait state.
• The Input/Output devices that are connected to microprocessor are of
different speed, which is need to be synchronized with the speed of
microprocessor.
• This signal is used mainly to synchronize slower external devices with the
microprocessor.

Niraj Khadka
Externally Initiated Operations
• HOLD
• When the HOLD pin is activated by an external signal, the microprocessor
releases the control of buses and allows the external peripheral to use them.
• For example, the HOLD signal is used Direct memory access (DMA) data
transfer.
• In this DMA, the external Input/Output devices directly communicate with
the memory without interfering the processor every time.

Niraj Khadka
• Before reading the addressing modes in 8085 we need to understand
the instruction cycle, machine cycle, t-states and common instructions
of 8085.

Niraj Khadka
8085 Instruction Cycle
• Time required to execute and fetch an entire instruction is
called instruction cycle.
• Consists of:
• Fetch cycle – The next instruction is fetched by the address stored in program
counter (PC) and then stored in the instruction register.
• Decode instruction – Decoder interprets the encoded instruction from
instruction register.
• Reading effective address – The address given in instruction is read from main
memory and required data is fetched. The effective address depends on direct
addressing mode or indirect addressing mode.
• Execution cycle – consists memory read (MR), memory write (MW), input
output read (IOR) and input output write (IOW)
Niraj Khadka
Machine Cycle
• For every instruction, a processor repeats a set of four basic
operations, which comprise a machine cycle: (1) fetching, (2)
decoding, (3) executing, and, if necessary, (4) storing.
• Fetching is the process of obtaining a program instruction or data
item from memory.
• decoding refers to the process of translating the instruction into
signals the computer can execute.
• Executing is the process of carrying out the commands.
• Storing, in this context, means writing the result to memory.

Niraj Khadka
Machine Cycle

Niraj Khadka
Instruction Description and Format
• Instruction manipulates data.
• Instructions in sequence is called a program.
• Instruction has two parts; operation (op-code) and operands (data or
address field).
• Data can be 8 bit, 16 bit , a register, a memory location.
• The opcode specifies how data is manipulated.

Niraj Khadka
Instruction Description and Format
• For EG:
• MOVE X, Y
where; MOVE= opcode
X = source operand,
Y = destination operand ,
• Instruction format:
• 1 address format (1 byte) = here, 1 byte specifies the operation and the operands are
default. Eg: ADD B, MOV B,D
• 2 address format (2 byte) = First byte = opcode and one operand, 2nd byte = operand
Eg: IN 40H, MVI A, FFH
• 3 address format (3 byte) = First byte = opcode, 2nd byte and 3rd byte = operand/data
• 2nd byte = lower order data, 3rd byte = higher order data.

Niraj Khadka
T- States
• The machine cycle and instruction cycle takes multiple clock periods.
• Single time period of frequency of microprocessor is called t-state.
• A portion of an operation carried out in one single clock period is
called a t-state.
• A t-state is measured from the falling edge of one clock pulse to the
falling edge of the next clock pulse.

Niraj Khadka
8085 Instruction Cycle

Fetch cycle takes four t-states and execution cycle takes three t-
states.

Niraj Khadka
8085 Instruction Cycle
• Timing Diagram of
opcode fetch as an
example:

Niraj Khadka
• Let’s consider the instruction MOV C, A stored at memory location
2005H. The Op-Code for the instruction is 4FH and Op-Code fetch
cycle is of 4 clock cycles.
• Step1: Microprocessor places the 16 bit memory address from
Program Counter on the address bus. At T1, high order address (20) is
placed at A8-A15 and lower order address (05) is placed at AD0- AD7
ALE signal goes high. IO/M goes low and both S0 and Sl goes high for
Op-Code fetch.

Niraj Khadka
• Step 2: The control unit sends the control signal RD to enable the
memory chip and active during T2and T3.
• Step 3: The byte from the memory location is placed on the data
bus .that is 4f into D0-D7 and RD goes high impedance.
• Step4: The instruction 4FH is decoded and content of accumulator
will be copied into register C during clock cycle T4.

Niraj Khadka
8085 Instruction Cycle
• 1st step => Fetch and Decode
• Fetch opcode from memory and place it in IR. Decode it and find its meaning.
• 2nd step => Execute
• Calculate address of operands, fetch operands to perform the decoded
operation, execute the operation and store the result back

Niraj Khadka
8085 Instruction Cycle
• Timing Diagram of
memory read cycle

Niraj Khadka
• Let’s consider the instruction MVI A, 32 H stored at memory location
2000H.

• @ 2000 == MVI A opcode => 3EH

• @ 2001 == Data = > 32H

• 2 cycle: Opcode fetch cycle and memory read cycle.

• 8085 places the address 2001 on the address bus and increments PC to
2002H. ALE is asserted high IO/M =0, S1=1, S0=0 for memory read cycle.
When RD =0, memory places the data byte 32H on the data bus.
Niraj Khadka
Niraj Khadka
8085 Instruction Cycle
• Timing Diagram of
memory write cycle

Niraj Khadka
8085 Instruction Cycle
• Timing Diagram of IO
read cycle
• IN instruction
• IN 40H

Niraj Khadka
8085 Instruction Cycle
• Timing Diagram of IO
write cycle
• OUT instruction
• OUT 40H

Niraj Khadka
Timing Diagram for MVI B, 43H

• Fetching the opcode 06H from the memory 2000H. (OF machine
cycle)
• Read (move) the data ) 43H from memory 2001H. (memory read)

Niraj Khadka
Timing Diagram for MVI B, 43H

Niraj Khadka
IO Read Timing Diagram

Niraj Khadka
IO Write Timing Diagram

Niraj Khadka
Timing diagram for IN 40H
• Let us consider the instruction IN 40H is stored at memory location
0xCAFE. The port address 40H is stored sequentially in the memory
location just after the instruction. The data to be read is “0x9F”. Draw
the timing diagram.
Address Op Codes Mnemonic
0xCAFE 0xDB IN 40H
0xCAFF 0x40 0x40 as port address

• Steps to perform
• Opcode fetch cycle -> Memory read cycle -> port read cycle

Niraj Khadka
Assignment
• Let us consider the instruction OUT CDH is stored at memory location
0xBABE. The port address CDH is stored sequentially in the memory
location just after the instruction. The data to be written is “0xBE”.
Draw the timing diagram.

• Due: September 28, 2020; 19:00 NST

Niraj Khadka
Timing Diagram of STA 4050H
• Let us consider an instruction STA 4050H at memory location 0xF3BA.
The instruction is a 3 byte addressing format instruction where the
first byte is an opcode of 2A and the remaining 16 bit is the memory
address (in little endian) where the content of A is to be stored. The
content of A is “0x5A”. Draw the timing diagram.

• Opcode fetch -> Memory Read -> Memory Read ->Memory Write

Niraj Khadka
Timing diagram of LDA 5F59H
• Let us consider an instruction LDA 5F59H at memory location 0xBEEF.
The instruction is a 3 byte addressing format instruction where the
first byte is an opcode of 3A and the remaining 16 bit is the memory
address (in little endian) from where the content is to be loaded at A.
The content of memory location 0x5F59 is “0x9A”. Draw the timing
diagram.

Niraj Khadka
Addressing modes in 8085
• Instructions used to transfer the data from one register to another
register, from the memory to the register, and from the register to the
memory without any alteration in the content.
• Addressing modes in 8085 is classified into 5 groups −
• Immediate Addressing mode
• Register Addressing mode
• Direct Addressing mode
• Register Indirect Addressing mode
• Implied Addressing mode

Niraj Khadka
Addressing modes in 8085
• Immediate addressing mode
• In this mode, the 8/16-bit data is specified in the instruction itself as one of its
operand.
• For example: MVI K, 20F: means 20F is copied into register K.
• LXI H 3050 (load the H-L pair with the operand 3050H immediately)

Niraj Khadka
Addressing modes in 8085
• Register addressing mode
• In this mode, the data is copied from one register to another.
• For example: MOV A, B: means data in register B is copied to register A.
• ADD B (add contents of registers A and B and store the result in register A)
• INR A (increment the contents of register A by one)

Niraj Khadka
Addressing modes in 8085
• Direct addressing mode
• In this mode, the data is directly copied from the given address to the
register.
• For example: LDB 5000: means the data at address 5000 is copied to register
B.
• LDA 2050 (load the contents of memory location into accumulator A)
• LHLD address (load contents of 16-bit memory location into H-L register pair)
• IN 35 (read the data from port whose address is 01)

Niraj Khadka
Addressing modes in 8085
• Register Indirect addressing mode
• In this mode, the data is transferred from one register to another by using the
address pointed by the register.
• For example: MOV A, M: means data is transferred from the memory address
pointed by the register H-L pair to the register A.
• LDAX B (move contains of B-C register to the accumulator)
• LXIH 9570 (load immediate the H-L pair with the address of the location 9570)

Niraj Khadka
Addressing modes in 8085
• Implied addressing mode
• This mode doesn’t require any operand; the data is specified by the opcode
itself.
• For example: CMA.
• CMA (finds and stores the 1’s complement of the contains of accumulator A in
A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)

Niraj Khadka
Data / Address
bus Multiplexing
• AD0 - AD7
• These multiplexed set of lines used to carry the lower order 8 bit
address as well as data bus.
• During the opcode fetch operation, in the first clock cycle, the lines
deliver the lower order address A0 - A7.
• In the subsequent IO / memory, read / write clock cycle the lines are
used as data bus.
• The CPU may read or write out data through these lines.

Niraj Khadka
Generation of control signals in 8085
• RD’ and WR’ is a control signal but these signal are used both for i/o
operation and memory operation.
• Therefore a separate READ signal for memory and separate READ
signal for io needs to be generated.

Niraj Khadka
Basic Computer Architecture Design
• SAP – I
• SAP – II
• SAP -> Simple as Possible.

Niraj Khadka
SAP – I
• SAP 1 is the first stage in the evolution towards modern computer.
• The main purpose of SAP is to introduce all the crucial ideas behind
computer operations.
• Being a simple computer SAP-1 also covers many advance concepts.
• SAP-1 is a bus organized computer. All registers are connected to the
W bus with the help of tri-state buffers.

Niraj Khadka
Sap – 1 Block Diagram

Niraj Khadka
Components of SAP 1
• Program Counter:
• Part of control unit counts from 0000 to 1111.
• Sends the address from where to fetch the next instruction.
• The PC resets to 0000 before the computer starts.

Niraj Khadka
Components of SAP 1
• Input and MAR:
• Includes address and data switch registers.
• Allows to send the 4 address bit and 8 data bits to RAM.
• MAR is part of SAP-1memory.
• During the computer run, the address in the PC is latched in the MAR, then
the MAR applies the address to the RAM and selects the data.

Niraj Khadka
Components of SAP 1
• RAM:
• 16x8 static TTL RAM.
• Can be programmed by the data and address switch registers.
• During computer run, the RAM receives the 4 bit address from MAR and a
read operation is performed.
• Then the data stored in the RAM is placed in the W bus for use by the
microprocessor.

Niraj Khadka
Components of SAP 1
• Instruction Register
• Part of Control unit.
• Stores the instruction fetched from the address contained in PC.
• The content of IR is split into two halves.
• Lower half nibble goes to W-bus when needed while the upper half nibble
goes to Controller and Sequencer block.

Niraj Khadka
Components of SAP 1
• Controller-Sequencer
• Generates control signals as a 12 bit word.
• Synchronizes the operations of the computer ensuring that things happen
when they are supposed to happen.
• Control word format:

Niraj Khadka
Components of SAP 1
• Accumulator:
• It is a 8 bit buffer register that stores intermediate results during a computer
run.
• It is always one of the operands of ADD, SUB and OUT instructions.

Niraj Khadka
Components of SAP 1
• Adder / Subtractor:
• it is a 2's complement adder-subtractor.
• This module is asynchronous (unclocked), which means that its contents can
change as soon as the input words change.
• When SU is low, the sum out of the adder/subtractor is S = A + B. When SU is
high, the difference appears as A = A + B ’.

Niraj Khadka
Components of SAP 1
• B Register:
• The B register is another buffer register.
• It is used in arithmetic operations.
• A low LB and positive clock edge load the word on the W bus into the B
register.
• The two state output of the B register drives the Adder-subtractor, supplying
the number to be added or subtracted from the content of the accumulator.

Niraj Khadka
Components of SAP 1
• Output Register
• At the end of the computer run, the accumulator contains the answer to the
problem being solved.
• At this point, we need to transfer the answer to the outside world. This is
where the output register is used.
• When EA is high and LO is low, the next positive clock edge loads the
accumulator content to the output register. The output register is often called
an output port because the processed data can leave the computer through
this register.

Niraj Khadka
Components of SAP 1
• Binary display:
• The binary display is a row of eight light emitting diodes (LED’s). Because each
LED connects to one flip-flop of the output port, the binary display shows us
the content of the output port.
• Therefore, after we transferred an answer from the accumulator to the
output port, we can see the answer in binary form.

Niraj Khadka
Instructions of SAP 1

Niraj Khadka
Machine Cycle and Instruction Cycle – SAP1
• SAP1 has six T-states (three fetch and three execute cycles) reserved
for each instruction. Not all instructions require all the six T-states for
execution. The unused T- state is marked as No Operation (NOP) cycle.
• Each T-state is called a machine cycle for SAP1. A ring counter is used
to generate a T-state at every falling edge of clock pulse. The ring
counter output is reset after the 6th T-state.
• FETCH CYCLE – T1, T2, T3 machine cycle
• EXECUTE CYCLE - T4, T5, T6 machine cycle

Niraj Khadka
Machine Cycle and Instruction Cycle – SAP1
• Fetch cycle is generally same for all instructions
• Complete code includes opcode and operand
• Like LDA 04H  0000 0100
• One instruction is executed in one instruction cycle

Niraj Khadka
Fetch Cycle SAP 1
• Fetch Cycle
• Address state: enable PC to bus three-state output, MAR load line
• Increment state: enable PC increment (and perhaps wait for memory access
time)
• Memory state: enable memory CE, IR load line
• IR is loaded on the low-to-high clock transition, so stabilizes before
state 4 is entered
• t1: MAR ← PC
• t2: PC ← PC +1
• t3: IR ← RAM

Niraj Khadka
Execution Cycle SAP 1
• Execution Cycle -- LDA
• t4: MAR ← (IR (Address of operand))
• t5: Accumulator ← RAM
• t6: nothing
• Execution Cycle -- ADD
• t4: MAR ← (IR (Address of B))
• t5: B ← RAM
• t6: Accumulator ← Accumulator + B

Niraj Khadka
SAP 2
• Bidirectional registers
• Includes jump instructions
• All register outputs to W bus are three-state; those not connected to
the bus are two-state

Niraj Khadka
SAP 2 Block Diagram

Niraj Khadka
SAP 2 Components
• Input Ports
• 2 input ports numbered 1 and 2.
• Hexadecimal keyboard encoder connected to port 1, sends READY signal to bit
0 of port 2.
• This signal indicates when the data in port 1 is valid, the SERIAL IN, signal
going to pin 7 or port.

Niraj Khadka
SAP 2 Components
• Program Counter
• Program counter has 16 bits; therefore it can count from PC= 0000 0000 0000
000 to PC=1111 1111 1111 1111.
• Its job is to send to the memory the address of the next instructions to be
fetched and executed.
• A low resets the PC before each computer run; so the data processing starts
with the instruction stored in memory location 0000H.

Niraj Khadka
SAP 2 Components
• MAR and Memory
• During the fetch cycle, the MAR receives 16 bit addresses from PC. The two
state MAR output then addresses memory location.
• The memory has 2K ROM with address 0000H too 07FFH. The ROM contains a
program called monitor that initializes the computer on power-up, interprets
the keyboard inputs and so on.
• The rest of memory is 64 K RAM with addresses from 0800H to FFFFH.

Niraj Khadka
SAP 2 Components
• MDR(Memory Data Register)
• 8 bit buffer register.
• Its output sets up the RAM.
• Receives data from the bus before a write operation and it sends data to the
bus after a read operation.

Niraj Khadka
SAP 2 Components
• IR(Instruction Register)
• Part of control unit.
• Memory read operation performed by computer to fetch an
instruction from memory; this places the contents of the addressed
memory location on W bus.
• Contents split into 2 nibbles.
• SAP 2 use 8 bits for op code which can accommodate 256
instructions.

Niraj Khadka
SAP 2 Components
• Controller Sequencer
• Produces the control words or microinstructions that coordinate and
direct the rest of the computer.
• Has more hardware since SAP 2 has bigger instruction set.
• Microinstruction determines how the registers react to the next
positive clock edge.

Niraj Khadka
SAP 2 Components
• Accumulator
• A buffer register that stores intermediate answers during the
computer run.
• Has two outputs two-state and three-state.
• Two-state output goes to ALU and three-state to W bus.
• Hence the 8 bit word in the accumulator continuously drives the ALU,
but this same word appears on the bus only when EA is active.

Niraj Khadka
SAP 2 Components
• ALU and Flags
• Includes arithmetic and logic operations.
• Has 4 or more control bits that determine the arithmetic or logic
operation performed on words A and B.
• Flag is a flip-flop that keeps track of a changing condition during a
computer run.
• SAP-2 has two flags; sign and zero flag.

Niraj Khadka
SAP 2 Components
• TMP, B and C Registers
• TMP(temporary) register is used instead of register B to hold data
being added or subtracted; which allows us more freedom in using
the B register.
• Besides B and TMP SAP 2 has a register C which gives us more
flexibility in moving data during the computer run.

Niraj Khadka
SAP 2 Components
• Output Ports
• Two output ports numbered 3 and 4.
• Contents of the accumulator can be loaded into port 3, which drives a
hexadecimal display.
• The contents can also be seen through port 4.

Niraj Khadka
Architectural difference SAP 1 and SAP 2
• Major differences:
• Bidirectional registers
• Flags
• Large instruction set having jump, call & loop.
• Standard Input Output devices in SAP 2.
• Large no. of processor registers in SAP 2.
• High memory capacity(64K) in SAP 2.
• Address bus 16 bit in SAP 2.
• Separate MAR & MDR in SAP 2.
• Complex programming possible in SAP 2
• Introduction of ALU in SAP 2
• Serial as well as parallel I/O in SAP 2.
Niraj Khadka
Differences in tabular form Sap1 and Sap2

Niraj Khadka
SAP 2 Instruction Set

Niraj Khadka
SAP 2 Instruction Set

Niraj Khadka
Design CKT to implement the flags for SAP
1.
• Inputs are: 8 bits from the accumulator, clock (use the positive-going edge), 1
LF control line (activehigh).
• Outputs are the flags: ZF (Zero Flag), SF (Sign Flag)
• Hint: Use D flip flops and other logic gates.

Niraj Khadka