A.1 What is Pipelining?

A.2 The Major Hurdle of Pipelining-Structural Hazards

◦ Data Hazards
◦ Control Hazards

1
 Laundry Example
 Ann, Brian, Cathy, Dave A B C D
each have one load of clothes

to wash, dry, and fold

 Washer takes 30 minutes

 Dryer takes 40 minutes

 “Folder” takes 20 minutes

Appendix A - Pipelining 2
 6 PM 7 8 9 10 11 Midnight
Time

30 40 20 30 40 20 30 40 20 30 40 20
T
a A
s
k
B
O
r
d C
e
r
D
Sequential laundry takes 6 hours for 4 loads
If they learned pipelining, how long would laundry take?
3
 6 PM 7 8 9 10 11 Midnight
Time

30 40 40 40 40 20
T
a A
s  Pipelined laundry takes
k 3.5 hours for 4 loads
B
O
r
d C
e
r
D

4
 What Is
Pipelining
Instruction Instr. Decode Execute Memory Write
Fetch Reg. Fetch Addr. Access Back
Calc Passed To Next Stage
IR <- Mem[PC]
NPC <- PC + 4
IR L
M
D

Instruction Fetch (IF):

Send out the PC and fetch the instruction from memory into the instruction
register (IR); increment the PC by 4 to address the next sequential
instruction.
IR holds the instruction that will be used in the next stage.
NPC holds the value of the next PC.

5
 What Is
Pipelining
Instruction Instr. Decode Execute Memory Write
Fetch Reg. Fetch Addr. Access Back
Calc Passed To Next Stage
A <- Regs[IR6..IR10];
B <- Regs[IR10..IR15];
IR L
Imm <- ((IR16) ##IR16-31
M
D

Instruction Decode/Register Fetch Cycle (ID):

Decode the instruction and access the register file to read the registers.
The outputs of the general purpose registers are read into two temporary
registers (A & B) for use in later clock cycles.
We extend the sign of the lower 16 bits of the Instruction Register.

6
 What Is
Pipelining
Instruction Instr. Decode Execute Memory Write
Fetch Reg. Fetch Addr. Access Back
Calc Passed To Next Stage
A <- A func. B
cond = 0;
IR L
M
D

Execute Address Calculation (EX):

We perform an operation (for an ALU) or an address calculation (if it’s a load
or a Branch).
If an ALU, actually do the operation. If an address calculation, figure out
how to obtain the address and stash away the location of that address for
the next cycle.

7
 What Is
Pipelining
Instruction Instr. Decode Execute Memory Write
Fetch Reg. Fetch Addr. Access Back
Calc Passed To Next Stage
A = Mem[prev. B]
or
IR L
Mem[prev. B] = A
M
D

MEMORY ACCESS (MEM):

If this is an ALU, do nothing.
If a load or store, then access memory.

8
 What Is
Pipelining
Instruction Instr. Decode Execute Memory Write
Fetch Reg. Fetch Addr. Access Back
Calc Passed To Next Stage
Regs <- A, B;
IR L
M
D

WRITE BACK (WB):

Update the registers from either the ALU or from the data loaded.

9
 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7

ALU
Ifetch Reg DMem Reg
I
n
s

ALU
t Ifetch Reg DMem Reg

r.

ALU
O Ifetch Reg DMem Reg

r
d

ALU
e Ifetch Reg DMem Reg

10
[Link] Major Hurdle of Pipelining-
Structural Hazards
-- Structural Hazards
– Data Hazards Limits to pipelining: Hazards prevent next
– Control Hazards instruction from executing during its
designated clock cycle
◦ Structural hazards: HW cannot support this
combination of instructions (single person
to fold and put clothes away)
◦ Data hazards: Instruction depends on result
of prior instruction still in the pipeline
(missing sock)
◦ Control hazards: Pipelining of branches &
other instructions that change the PC
◦ Common solution is to stall the pipeline
until the hazard is resolved, inserting one
or more “bubbles” in the pipeline

Appendix A - Pipelining 11
Definition
 conditions that lead to incorrect behavior if not fixed

 Structural hazard

◦ two different instructions use same h/w in same cycle

 Data hazard

◦ two different instructions use same storage

◦ must appear as if the instructions execute in correct order
 Control hazard

◦ one instruction affects which instruction is next

Resolution
 Pipeline interlock logic detects hazards and fixes them

 simple solution: stall ­

 increases CPI, decreases performance

 better solution: partial stall ­

 some instruction stall, others proceed better to stall early than late

Appendix A - Pipelining 12
 When two or
Time (clock cycles) more different
instructions want
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 to use same
hardware
I Load Ifetch

ALU
Reg DMem Reg resource in same
n cycle

s Instr 1

ALU
Ifetch Reg DMem Reg
e.g., MEM uses
t the same memory
r. port as IF as

ALU
Ifetch Reg DMem Reg
Instr 2 shown in this
slide.
O

ALU
r Instr 3 Ifetch Reg DMem Reg

d
e

ALU
Ifetch Reg DMem Reg
Instr 4
r

Figure 3.6
Appendix A - Pipelining 13
 Time (clock cycles)
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 This is another
way of looking
at the effect of
I Load Ifetch

ALU
Reg DMem Reg
a stall.
n
s

ALU
Reg
t Instr 1
Ifetch Reg DMem

r.

ALU
Ifetch Reg DMem Reg
Instr 2
O
r
Stall Bubble Bubble Bubble Bubble Bubble
d
e
r

ALU
Ifetch Reg DMem Reg
Instr 3

Figure 3.7
Appendix A - Pipelining 14
This is another way to represent the stall we saw on
the last few pages.

Appendix A - Pipelining 15
Dealing with Structural Hazards
Stall
 low cost, simple

 Increases CPI

 use for rare case since stalling has performance effect

Pipeline hardware resource

 useful for multi-cycle resources

 good performance

 sometimes complex e.g., RAM

Replicate resource
 good performance

 increases cost (+ maybe interconnect delay)

 useful for cheap or divisible resources

16
Structural hazards are reduced with these rules:
 Each instruction uses a resource at most once

 Always use the resource in the same pipeline stage

 Use the resource for one cycle only

Many RISC ISA’a designed with this in mind

Sometimes very complex to do this. For example, memory of
necessity is used in the IF and MEM stages.

Some common Structural Hazards:

• Memory - we’ve already mentioned this one.
• Floating point - Since many floating point instructions require
many cycles, it’s easy for them to interfere with each other.
• Starting up more of one type of instruction than there are
resources. For instance, the PA-8600 can support two ALU +
two load/store instructions per cycle - that’s how much hardware
it has available.

17
 This is the example on Page 144.

We want to compare the performance of two machines. Which machine is faster?

 Machine A: Dual ported memory - so there are no memory stalls
 Machine B: Single ported memory, but its pipelined implementation has a 1.05
times faster clock rate
Assume:
 Ideal CPI = 1 for both
 Loads are 40% of instructions executed

SpeedUpA = Pipeline Depth/(1 + 0) x (clockunpipe/clockpipe)

= Pipeline Depth
SpeedUpB = Pipeline Depth/(1 + 0.4 x 1)
x (clockunpipe/(clockunpipe / 1.05)
= (Pipeline Depth/1.4) x 1.05
= 0.75 x Pipeline Depth
SpeedUpA / SpeedUpB = Pipeline Depth / (0.75 x Pipeline Depth) = 1.33

 Machine A is 1.33 times faster

Appendix A - Pipelining 18
A.1 What is Pipelining?
A.2 The Major Hurdle of Pipelining-
Structural Hazards
-- Structural Hazards
These occur when at any time, there are
– Data Hazards instructions active that need to access the
– Control Hazards same data (memory or register) locations.
A.3 How is Pipelining Implemented
Where there’s real trouble is when we have:
A.4 What Makes Pipelining Hard to
Implement?
instruction A
A.5 Extending the MIPS Pipeline to instruction B
Handle Multi-cycle Operations

and B manipulates (reads or writes) data

before A does. This violates the order of the
instructions, since the architecture implies
that A completes entirely before B is
executed.

Appendix A - Pipelining 19
Execution Order is:
Read After Write (RAW)
InstrI
InstrJ tries to read operand before InstrI writes it
InstrJ

I: add r1,r2,r3
J: sub r4,r1,r3
 Caused by a “Dependence” (in compiler nomenclature).
This hazard results from an actual need for
communication.

Appendix A - Pipelining 20
Execution Order is:
Write After Read (WAR)
InstrI
InstrJ tries to write operand before InstrI reads i
◦ Gets wrong operand
InstrJ

I: sub r4,r1,r3
J: add r1,r2,r3
K: mul r6,r1,r7

◦ Called an “anti-dependence” by compiler writers.

This results from reuse of the name “r1”.
 Can’t happen in MIPS 5 stage pipeline because:
◦ All instructions take 5 stages, and
◦ Reads are always in stage 2, and
◦ Writes are always in stage 5

Appendix A - Pipelining 21
Execution Order is:
Write After Write (WAW)
InstrI
InstrJ tries to write operand before InstrI writes it
InstrJ
◦ Leaves wrong result ( InstrI not InstrJ )

I: sub r1,r4,r3
J: add r1,r2,r3
K: mul r6,r1,r7

 Called an “output dependence” by compiler writers

This also results from the reuse of name “r1”.

 Can’t happen in MIPS 5 stage pipeline because:

◦ All instructions take 5 stages, and
◦ Writes are always in stage 5
 Will see WAR and WAW in later more complicated pipes

Appendix A - Pipelining 22
 Simple Solution to RAW

• Hardware detects RAW and stalls

• Assumes register written then read each cycle
+ low cost to implement, simple
-- reduces IPC
• Try to minimize stalls

Minimizing RAW stalls

• Bypass/forward/short­circuit (We will use the word “forward”)

• Use data before it is in the register
+ reduces/avoids stalls
-- complex
• Crucial for common RAW hazards

Appendix A - Pipelining 23
 Time (clock cycles)
IF ID/RF EX MEM WB
I

ALU
Reg Reg
add r1,r2,r3Ifetch DMem

n
s

ALU
Ifetch Reg DMem Reg
t sub r4,r1,r3
r.

ALU
Ifetch Reg DMem Reg
and r6,r1,r7
O
r

ALU
Ifetch Reg DMem Reg

d or r8,r1,r9
e

ALU
Ifetch Reg DMem Reg
r xor r10,r1,r11
The use of the result of the ADD instruction in the next three instructions causes a
hazard, since the register is not written until after those instructions read it.

Figure 3.9
Appendix A - Pipelining 24
 Forwarding is the concept of making data
available to the input of the ALU for
subsequent instructions, even though the
generating instruction hasn’t gotten to WB
Forwarding To Avoid in order to write the memory or registers.
Data Hazard
Time (clock cycles)
I
n

ALU
add r1,r2,r3 Ifetch Reg DMem Reg

s
t

ALU
Reg
r. sub r4,r1,r3 Ifetch Reg DMem

ALU
Ifetch Reg DMem Reg
r and r6,r1,r7
d
e

ALU
Ifetch Reg DMem Reg
r or r8,r1,r9

ALU
Ifetch Reg DMem Reg
xor r10,r1,r11

Figure 3.10
Appendix A - Pipelining 25
 The data isn’t loaded until after
the MEM stage.
Time (clock cycles)

ALU
lw r1, 0(r2) Ifetch Reg DMem Reg

n
s
t

ALU
Ifetch Reg DMem Reg
sub r4,r1,r6
r.

ALU
Ifetch Reg DMem Reg
and r6,r1,r7
r
d
e

ALU
Ifetch Reg DMem Reg

r or r8,r1,r9

There are some instances where hazards occur, even with forwarding.
Figure 3.12
Appendix A - Pipelining 26
 The stall is necessary as shown
here.
Time (clock cycles)
I
n
lw r1, 0(r2)

ALU
Ifetch Reg DMem Reg
s
t
r.

ALU
sub r4,r1,r6 Ifetch Reg Bubble DMem Reg

O
r
d Bubble

ALU
Ifetch Reg DMem Reg
e and r6,r1,r7
r

ALU
Bubble Ifetch Reg DMem
or r8,r1,r9

There are some instances where hazards occur, even with forwarding.
Figure 3.13
Appendix A - Pipelining 27
 This is another
representation
of the stall.

LW R1, 0(R2) IF ID EX MEM WB

SUB R4, R1, R5 IF ID EX MEM WB

AND R6, R1, R7 IF ID EX MEM WB

OR R8, R1, R9 IF ID EX MEM WB

LW R1, 0(R2) IF ID EX MEM WB

SUB R4, R1, R5 IF ID stall EX MEM WB

AND R6, R1, R7 IF stall ID EX MEM WB

OR R8, R1, R9 stall IF ID EX MEM WB

Appendix A - Pipelining 28
 Pipeline Scheduling

Instruction scheduled by compiler - move instruction in order to reduce stall.

lw Rb, b ­code sequence for a = b+c before scheduling

lw Rc, c
Add Ra, Rb, Rc ­stall
sw a, Ra
lw Re, e ­code sequence for d = e+f before scheduling
lw Rf, f
sub Rd, Re, Rf ­stall
sw d, Rd

Arrangement of code after scheduling.

lw Rb, b
lw Rc, c
lw Re, e
Add Ra, Rb, Rc
lw Rf, f
sw a, Ra
sub Rd, Re, Rf
sw d, Rd

Appendix A - Pipelining 29
A.1 What is Pipelining?
A.2 The Major Hurdle of Pipelining-
Structural Hazards
-- Structural Hazards
– Data Hazards A control hazard is when
– Control Hazards we need to find the
A.3 How is Pipelining Implemented destination of a branch,
A.4 What Makes Pipelining Hard to
and can’t fetch any new
Implement? instructions until we know
A.5 Extending the MIPS Pipeline to that destination.
Handle Multi-cycle Operations

Appendix A - Pipelining 30
Control Hazards

ALU
10: beq r1,r3,36 Ifetch Reg DMem Reg

ALU
14: and r2,r3,r5 Ifetch Reg DMem Reg

ALU
18: or r6,r1,r7 Ifetch Reg DMem Reg

ALU
Reg
22: add r8,r1,r9 Ifetch Reg DMem

ALU
36: xor r10,r1,r11 Ifetch Reg DMem Reg

Appendix A - Pipelining 31
Control Hazards
 If CPI = 1, 30% branch, Stall 3 cycles => new CPI = 1.9!
(Whoa! How did we get that 1.9???)
 Two part solution to this dramatic increase:
◦ Determine branch taken or not sooner, AND
◦ Compute taken branch address earlier

 MIPS branch tests if register = 0 or ^ 0

 MIPS Solution:
◦ Move Zero test to ID/RF stage
◦ Adder to calculate new PC in ID/RF stage
 must be fast
 can't afford to subtract
 compares with 0 are simple
 Greater-than, Less-than test sign­bit, but not-equal must OR all bits
 more general compares need ALU
◦ 1 clock cycle penalty for branch versus 3

In the next chapter, we’ll look at ways to avoid the branch all together.

Appendix A - Pipelining 32
Control Hazards
#1: Stall until branch direction is clear

#2: Predict Branch Not Taken

◦ Execute successor instructions in sequence
◦ “Squash” instructions in pipeline if branch actually taken
◦ Advantage of late pipeline state update
◦ 47% MIPS branches not taken on average
◦ PC+4 already calculated, so use it to get next instruction

#3: Predict Branch Taken

◦ 53% MIPS branches taken on average
◦ But haven’t calculated branch target address in MIPS
 MIPS still incurs 1 cycle branch penalty
 Other machines: branch target known before outcome

Appendix A - Pipelining 33
Control Hazards Five Branch Hazard
Alternatives
#4: Execute Both Paths

#5: Delayed Branch

◦ Define branch to take place AFTER a following instruction

branch instruction
sequential successor1
sequential successor2
........
sequential successorn Branch delay of length n
branch target if taken

◦ 1 slot delay allows proper decision and branch target

address in 5 stage pipeline
◦ MIPS uses this

Appendix A - Pipelining 34
Control Hazards

Pipeline speedup = Pipeline depth

1 +Branch frequencyBranch penalty

Scheduling Branch CPI speedup v. Speedup v.

scheme penalty unpipelined stall
Stall pipeline 3 1.42 3.5 1.0
Predict taken 1 1.14 4.4 1.26
Predict not taken 1 1.09 4.5 1.29
Delayed branch 0.5 1.07 4.6 1.31

Conditional & Unconditional = 14%, 65% change PC

Appendix A - Pipelining 35
Control Hazards

 Just overlap tasks, and easy if tasks are independent

 Speed Up Š Pipeline Depth; if ideal CPI is 1, then:

Pipeline Depth Clock Cycle Unpipelined

Speedup = X
1 + Pipeline stall CPI Clock Cycle Pipelined

 Hazards limit performance on computers:

◦ Structural: need more HW resources
◦ Data (RAW,WAR,WAW): need forwarding, compiler
scheduling
◦ Control: delayed branch, prediction

Appendix A - Pipelining 36
Control Hazards

 Improves strategy for placing instructions in delay slot

 Two strategies
◦ Backward branch predict taken, forward branch not taken
◦ Profile-based prediction: record branch behavior, predict
branch based on prior run

Appendix A - Pipelining 37
 Interrupts cause
great havoc!

Examples of interrupts: There are 5 instructions executing

 Power failing, in 5 stage pipeline when an
interrupt occurs:
 Arithmetic overflow,
• How to stop the pipeline?
 I/O device request,
• How to restart the pipeline?
 OS call, • Who caused the interrupt?
 Page fault

Interrupts (also known as: faults,

exceptions, traps) often require
 surprise jump (to vectored address)
 linking return address
 saving of PSW (including CCs)
 state change (e.g., to kernel mode)

Appendix A - Pipelining 38
 Hazards limit performance
◦ Structural: need more HW resources
◦ Data: need forwarding, compiler scheduling
◦ Control: early evaluation & PC, delayed branch, prediction
 Increasing length of pipe increases impact of hazards; pipelining
helps instruction bandwidth, not latency
 Interrupts, Instruction Set, FP makes pipelining harder
 Compilers reduce cost of data and control hazards
◦ Load delay slots
◦ Branch delay slots
◦ Branch prediction

Appendix A - Pipelining 39