EE 319K

Introduction to Embedded Systems

Lecture 2: ARM Assembly, More

I/O, Switch and LED interfacing

Bard, Gerstlauer, Valvano, Yerraballi 3-1

 Agenda
 Outline
Assembly – ARM ISA
Reset Specifics
Digital Logic
o GPIO TM4C123/LM4F120 Specifics
Switch and LED interfacing

Bard, Gerstlauer, Valvano, Yerraballi 3-2

 ARM Assembly Language

 Assembly format

Label Opcode Operands Comment

init MOV R0, #100 ; set table size
BX LR

 Comments
 Comments should explain why or how
 Comments should not explain the opcode and its operands
 Comments are a major component of self-documenting code

Bard, Gerstlauer, Valvano, Yerraballi 3-3

 Simple Addressing Modes
 Second operand - <op2>
ADD Rd, Rn, <op2>
Constant
o ADD Rd, Rn, #constant ; Rd = Rn+constant
Shift
o ADD R0, R1, LSL #4 ; R0 = R0+(R1*16)
o ADD R0, R1, R2, ASR #4 ; R0 = R1+(R2/16)
 Memory accessed only with LDR STR
 Constant in ROM: =Constant / [PC,#offs]
 Variable on the stack: [SP,#offs]
 Global variable in RAM: [Rx]
 I/O port: [Rx]
Bard, Gerstlauer, Valvano, Yerraballi 3-4
 Addressing Modes
 Immediate addressing
 Data is contained in the instruction

MOV R0,#100 ; R0=100, immediate

addressing
100
R0
EEPROM
PC 0x00000266 0x00000260
0x00000264 F04F 0064 MOV R0,#100
0x00000268
0x0000026C

Bard, Gerstlauer, Valvano, Yerraballi 3-5

 Addressing Modes

 Indexed Addressing
Address of the data in memory is in a register

LDR R0,[R1] ; R0= value pointed to by R1

EEPROM
0x00000142
PC 0x00000144 0x00000144 6808 LDR R0,[R1]
0x00000146
0x00000148
0x12345678 RAM
R0
0x20000000
0x20000004 12345678
0x20000008
R1 0x20000004 0x2000000C

Bard, Gerstlauer, Valvano, Yerraballi 3-6

 Addressing Modes
 PC Relative Addressing
Address of data in EEPROM is indexed based
upon the Program Counter

First,
LDR R1,=Count 0x2000.0000 ROM space

Second,
Count LDR R0,[R1]
R1 0x2000.0000
RAM space R0

Bard, Gerstlauer, Valvano, Yerraballi 3-7

 Memory Access Instructions

 Loading a register with a constant,

address, or data
LDR Rd, =number
LDR Rd, =label

 LDR and STR used to load/store RAM

using register-indexed addressing
Register [R0]
Base address plus offset [R0,#16]

Bard, Gerstlauer, Valvano, Yerraballi 3-8

 Load/Store Instructions
 General load/store instruction format
LDR{type} Rd,[Rn] ;load memory at [Rn] to Rd
STR{type} Rt,[Rn] ;store Rt to memory at [Rn]
LDR{type} Rd,[Rn, #n] ;load memory at [Rn+n] to Rd
STR{type} Rt,[Rn, #n] ;store Rt to memory [Rn+n]
LDR{type} Rd,[Rn,Rm,LSL #n] ;load [Rn+Rm<<n] to Rd
STR{type} Rt,[Rn,Rm,LSL #n] ;store Rt to [Rn+Rm<<n]

Bard, Gerstlauer, Valvano, Yerraballi 3-9

 ARM ISA : ADD, SUB and CMP

ARITHMETIC INSTRUCTIONS
ADD{S} {Rd,} Rn, <op2> ;Rd = Rn + op2
ADD{S} {Rd,} Rn, #im12 ;Rd = Rn + im12
SUB{S} {Rd,} Rn, <op2> ;Rd = Rn - op2
SUB{S} {Rd,} Rn, #im12 ;Rd = Rn - im12
RSB{S} {Rd,} Rn, <op2> ;Rd = op2 - Rn
RSB{S} {Rd,} Rn, #im12 ;Rd = im12 - Rn
CMP Rn, <op2> ;Rn - op2
CMN Rn, <op2> ;Rn - (-op2)

Addition Subtraction
C bit set if unsigned overflow C bit clear if unsigned overflow
V bit set if signed overflow V bit set if signed overflow

Bard, Gerstlauer, Valvano, Yerraballi 3-10

 ARM ISA : Multiply and Divide

32-BIT MULTIPLY/DIVIDE INSTRUCTIONS

MUL{S} {Rd,} Rn, Rm ;Rd = Rn * Rm
MLA Rd, Rn, Rm, Ra ;Rd = Ra + Rn*Rm
MLS Rd, Rn, Rm, Ra ;Rd = Ra - Rn*Rm
UDIV {Rd,} Rn, Rm ;Rd = Rn/Rm unsigned
SDIV {Rd,} Rn, Rm ;Rd = Rn/Rm signed

Multiplication does not set C,V bits

Bard, Gerstlauer, Valvano, Yerraballi 3-11

 Input/Output: TM4C123
Cortex M4 Systick
System Bus Interface NVIC

GPIO Port A GPIO Port B

PA7 PB7
PA6 Four PB6
PA5/SSI0Tx Eight PB5
PA4/SSI0Rx UARTs I2Cs PB4
PA3/SSI0Fss PB3/I2C0SDA
PA2/SSI0Clk Four PB2/I2C0SCL
PA1/U0Tx CAN 2.0 PB1
SSIs
PA0/U0Rx PB0
GPIO Port C GPIO Port D
PC7
PC6
PC5 USB 2.0 Twelve
PD7
PD6
PD5
6 General-Purpose
PC4
PC3/TDO/SWO
Timers PD4
PD3 I/O (GPIO) ports:
PC2/TDI Six PD2
PC1/TMS/SWDIO
PC0/TCK/SWCLK
JTAG
64-bit wide PD1
PD0
• Four 8-bit ports
GPIO Port E GPIO Port F (A, B, C, D)
PE5
PE4 ADC Two Analog PF4 • One 6-bit port (E)
PE3 2 channels Comparators PF3
PE2
PE1
12 inputs
12 bits Two PWM
PF2
PF1
• One 5-bit port (F)
PE0 Modules PF0

Advanced High Performance Bus Advanced Peripheral Bus

Bard, Gerstlauer, Valvano, Yerraballi 3-12

 TM4C123 I/O Pins
 I/O Pin Characteristics Set AFSEL to 0
Can be employed as an n-bit parallel interface
Pins also provide alternative functions:
o UART Universal asynchronous
receiver/transmitter
o SSI Synchronous serial interface
o I2C Inter-integrated circuit
o Timer Periodic interrupts, input capture,
and output compare
o PWM Pulse width modulation
o ADC Analog to digital converter,
measure analog signals
o Analog Compare two analog signals
Comparator
o QEI Quadrature encoder interface
o USB Universal serial bus
o Ethernet High speed network
o CAN
Set AFSEL to 1
Controller area network

Bard, Gerstlauer, Valvano, Yerraballi 3-13

 TM4C123 LaunchPad I/O Pins
IO Ain 0 1 2 3 4 5 6 7 8 9 14
PA2 Port SSI0Clk
PA3 Port SSI0Fss
PA4 Port SSI0Rx
PA5 Port SSI0Tx
PA6 Port I2C1SCL M1PWM2
PA7 Port I2C1SDA M1PWM3
PB0 Port U1Rx T2CCP0
PB1 Port U1Tx T2CCP1
PB2 Port I2C0SCL T3CCP0
PB3 Port I2C0SDA T3CCP1
PB4 Ain10 Port SSI2Clk M0PWM2 T1CCP0 CAN0Rx
PB5 Ain11 Port SSI2Fss M0PWM3 T1CCP1 CAN0Tx
PB6 Port SSI2Rx M0PWM0 T0CCP0
PB7 Port SSI2Tx M0PWM1 T0CCP1
PC4 C1- Port U4Rx U1Rx M0PWM6 IDX1 WT0CCP0 U1RTS
PC5 C1+ Port U4Tx U1Tx M0PWM7 PhA1 WT0CCP1 U1CTS
PC6 C0+ Port U3Rx PhB1 WT1CCP0 USB0epen
PC7 C0- Port U3Tx WT1CCP1 USB0pflt
PD0 Ain7 Port SSI3Clk SSI1Clk I2C3SCL M0PWM6 M1PWM0 WT2CCP0
PD1 Ain6 Port SSI3Fss SSI1Fss I2C3SDA M0PWM7 M1PWM1 WT2CCP1
PD2 Ain5 Port SSI3Rx SSI1Rx M0Fault0 WT3CCP0 USB0epen
PD3 Ain4 Port SSI3Tx SSI1Tx IDX0 WT3CCP1 USB0pflt
PD6 Port U2Rx M0Fault0 PhA0 WT5CCP0
PD7 Port U2Tx PhB0 WT5CCP1 NMI
PE0 Ain3 Port U7Rx
PE1 Ain2 Port U7Tx
PE2 Ain1 Port
PE3 Ain0 Port
PE4 Ain9 Port U5Rx I2C2SCL M0PWM4 M1PWM2 CAN0Rx
PE5 Ain8 Port U5Tx I2C2SDA M0PWM5 M1PWM3 CAN0Tx
PF0 Port U1RTS SSI1Rx CAN0Rx M1PWM4 PhA0 T0CCP0 NMI C0o
PF1 Port U1CTS SSI1Tx M1PWM5 PhB0 T0CCP1 C1o TRD1
PF2 Port SSI1Clk M0Fault0 M1PWM6 T1CCP0 TRD0
PF3 Port SSI1Fss CAN0Tx M1PWM7 T1CCP1 TRCLK
PF4 Port M1Fault0 IDX0 T2CCP0 USB0epen 3-14
 TM4C123 I/O registers
Address 7 6 5 4 3 2 1 0 Name
$400F.E608 GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_RCGCGPIO_R
$400F.EA08 GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_PRGPIO_R
$4005.8000 PORTA base address
$4005.9000 PORTB base address
$4005.A000 PORTC base address
$4005.B000 PORTD base address
$4005.C000 PORTE base address
$4005.D000 PORTF base address
base+$3FC DATA DATA DATA DATA DATA DATA DATA DATA GPIO_PORTx_DATA_R
base+$400 DIR DIR DIR DIR DIR DIR DIR DIR GPIO_PORTx_DIR_R
base+$420 SEL SEL SEL SEL SEL SEL SEL SEL GPIO_PORTx_AFSEL_R
base+$510 PUE PUE PUE PUE PUE PUE PUE PUE GPIO_PORTx_PUR_R
base+$51C DEN DEN DEN DEN DEN DEN DEN DEN GPIO_PORTx_DEN_R
base+$524 CR CR CR CR CR CR CR CR GPIO_PORTx_CR_R
base+$528 AMSEL AMSEL AMSEL AMSEL AMSEL AMSEL AMSEL AMSEL GPIO_PORTx_AMSEL_R

31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0

base+$52C PMC7 PMC6 PMC5 PMC4 PMC3 PMC2 PMC1 PMC0 GPIO_PORTx_PCTL_R
base+$520 LOCK (32 bits) GPIO_PORTx_LOCK_R

• Four 8-bit ports (A, B, C, D) • PA1-0 to COM port

• One 6-bit port (E) • PC3-0 to debugger
• One 5-bit port (F) • PD5-4 to USB device
Bard, Gerstlauer, Valvano, Yerraballi 3-15
 Reset, Subroutines and Stack
 A Reset occurs immediately after power is applied and
when the reset signal is asserted (Reset button pressed)
 The Stack Pointer, SP (R13) is initialized at Reset to the
32-bit value at location 0 (Default: 0x20000408)
 The Program Counter, PC (R15) is initialized at Reset to
the 32-bit value at location 4 (Reset Vector)
 The Link Register (R14) is initialized at Reset to
0xFFFFFFFF
 Thumb bit is set at Reset
 Processor automatically saves return address in LR when
a subroutine call is invoked.
 User can push and pull multiple registers on or from the
Stack at subroutine entry and before subroutine return.

Bard, Gerstlauer, Valvano, Yerraballi 3-16

 Switch Configuration

negative – pressed = ‘0’ positive – pressed = ‘1’

Bard, Gerstlauer, Valvano, Yerraballi 3-17

 Switch Configuration
+3.3V +3.3V
TM4C TM4C
10k
s Input port t Input port
10k
Negative logic Positive logic

Negative Logic s Positive Logic t

– pressed, 0V, false – pressed, 3.3V, true
– not pressed, 3.3V, true – not pressed, 0V, false
+3.3V +3.3V +3.3V +3.3V
TM4C TM4C TM4C TM4C
10k 10k
3.3V 0V
s Input port s Input port t Input port t Input port
0.0V 3.3V
10k 10k
Pressed Not pressed Pressed Not pressed

Bard, Gerstlauer, Valvano, Yerraballi 3-18

 LED Interfacing

LED current v. voltage

Brightness = power = V*I anode (+)

cathode (1)
“big voltage connects to big pin”
Bard, Gerstlauer, Valvano, Yerraballi 3-19
 LED Configuration

Current
high LM3S +3.3V
2 + a Out R
I I or 1mA
R 1mA TM4C
(mA) 1 - k LM3S LED
or
TM4C LED
voltage low
0 Out
1.5 1.6 1.7
V (volts)
(a) LED curve (b) Positive logic interface (c) Negative logic interface

Bard, Gerstlauer, Valvano, Yerraballi 3-20

 LED Interfacing

R = (3V – 1.5)/0.001 R = (5.0-2-0.5)/0.01

= 1.5 kOhm = 250 Ohm
high LM3S +5V
Out or R 10mA
R 1mA TM4C 7406
LM3S
or +5V LED
TM4C LED
high 0.5V
Out

LED current < 8 ma LED current > 8 ma

LED may contain several diodes in series

Bard, Gerstlauer, Valvano, Yerraballi 3-21

 LaunchPad Switches and LEDs
R1 0
TM4C123 PF0
PF4
Serial PA1 R13 0 5V
PA0 Green
R29 Blue Red
+5  PB1
0
PD5 330 330 330
USB R12 SW1 SW2
R25 PD4 PF3
PB0 0
0
PD0
R9 0 R11
PB6 PF2
0
R10 0
PD1 R2 DTC114EET1G
PF1
PB7 0

 The switches on the LaunchPad

Negative logic
Require internal pull-up (set bits in PUR)
 The PF3-1 LEDs are positive logic
Bard, Gerstlauer, Valvano, Yerraballi 3-22
 I/O Port Bit-Specific
 I/O Port bit-specific
addressing is used to
access port data
register
 Define address offset as
4*2b, where b is the
selected bit position Port F = 0x4005.D000
 256 possible bit
0x4005.D000+0x0004+0x0040
combinations (0-8)
= 0x4005.D044
 Add offsets for each bit
selected to base
Provides friendly and atomic
address for the port
access to port pins
 Example: PF4 and PF0

Bard, Gerstlauer, Valvano, Yerraballi 3-23