Serial Communication

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Universal Asynchronous Receiver and
Transmitter (UART)
 DCD (Data Carrier
Detect) 1

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2

7
3

8
4

9
5

 RXD (Received Data)

 TXD (Transmitted Data)
 DTR (Data Terminal
Ready)
 GND (Signal Ground)
 DSR (Data set ready)
 RTS (Request to send)
 CTS (Clear to send)
 RI (Ring Indicator)
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Universal Asynchronous Receiver and
Transmitter (UART)

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Universal Asynchronous Receiver and
Transmitter (UART)

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Universal Asynchronous Receiver and
Transmitter (UART)
 The USART clock source (usart_ker_ck) can be
selected
from several sources:
 peripheral clock (APB clock PCK)
 SYSCLK
 High Speed Internal 16-MHz oscillator (HSI16)
 Low Speed External Oscillator (LSE)

 Tx and Rx pins are used for data transmission

and
reception.

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Universal Asynchronous Receiver and
Transmitter (UART)
 nCTS and nRTS pins are used for RS-232 hardware flow
control.

 The Driver Enable pin (DE) which is available on the

same I/O as nRTS is used in RS-485 mode.

 Note that the NSS and nCTS signals share the same
pin:
 NSS is the slave selection input applied to the device in
synchronous slave mode

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Universal Asynchronous Receiver and
Transmitter (UART)
 The clock output (CK) is dual purpose:
 When the USART is used in Synchronous
Master/Slave mode, the clock provided to the slave
device is output/input on the CK pin
SYSCLK
 When the USART is used in Smartcard mode, the
clock
provided to the card is output on the CK pin.

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UART or USART
 Universal Synchronous/Asynchronous
Receiver/Transmitter (USART)
 USART1, USART2, USART3
 Universal Asynchronous Receiver/Transmitter
(UART)
 UART4, UART5

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UART or USART

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UART or USART

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UART or USART

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UART or USART

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Universal Asynchronous Receiver and
Transmitter (UART)
 Universal
 UART is programmable.
 Asynchronous
 Sender provides no clock signal to receivers

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Connecting to PC
 FT232R converts the UART port to a standard
USB interface

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Data Frame

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Data Frame

Tolerate 10% clock shift during

transmission
 Data frame
 One logic-low start bit
 Data (LSB first or MSB first, and size of 7, 8, 9 bits)
 One optional parity bit
 One or two logic-high stop bits

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Data Frame

Tolerate 10% clock shift during

transmission
 Receiver must know the transmission rate
 Receiver uses a timer to time when it should sample
 To tolerate clock shift, receiver only samples at the middle of each bit
 The start bit inform receiver to reset its timer
 Receiver is only synchronized with the sender on every start bit.
 Only has to be accurate enough to read up to 9 bits

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Data Frame

Tolerate 10% clock shift during

transmission

 Receiver reports “frame error” if the stop bit is not detected

 Another start bit can appear immediately after stop bit
 Receiver then resynchronizes with sender on the new start bit

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Baud Rate

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Baud Rate

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Baud Rate
 Historically used in telecommunication to
represent the number of pulses physically
transferred per second
 In digital communication, baud rate is the
number of bits physically transferred per
second
 Example:
 Baud rate is 9600
 each frame: a start bit, 8 data bits, a stop bit, and
no parity bit.
 Transmission rate of actual data
9600/8 = 1200 bytes/second
22 9600/(1 + 8 + 1) = 960 bytes/second
Baud Rate
𝑓 𝑃𝐶𝐿𝐾
𝐵𝑎𝑢𝑑 𝑅𝑎𝑡𝑒=
8 ×(2 −𝑂𝑉𝐸𝑅 8)× 𝑈𝑆𝐴𝑅𝑇𝐷𝐼𝑉

 If OVER8 is 0, then the signal is oversampled

by 16, and 4 bits are used for the fractional
part.
 If OVER8 is 1, then the signal is oversampled
by 8, and 3 bits are used.
 If BRR is 0x1BC and OVER8 is 0, then 0x1B is
the integer part and 0xC is the fractional part.

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Baud Rate
 Suppose the processor clock is 16MHz, and
the system is oversampled by 16 (),

 Thus USARTDIV is 104.1875, which is encoded

as 0x683.
 desired baud rate 9600
6
16 × 10
𝐵𝑎𝑢𝑑 𝑅𝑎𝑡𝑒= =9598
8 ×(2 −0) ×104 .1875
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Error Detection
 Even Parity: total number of “1” bits in data and
parity is even
 Odd Parity: total number of “1” bits in data and
parity is odd
 Example: Data = 10101011 (five “1” bits)
 The parity bit should be 0 for odd parity and 1 for
even parity
 This can detect single-bit data corruption
Transmitting 0x32 and 0x3C

1
=0 .10417 × 10
−3 1 start bit, 1 stop bit, 8 data bits,
9600 LSB first, no parity, baud rate =
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9600
Sending Data
void USART_Write(USART_TypeDef * USARTx, uint8_t * buffer, int
nBytes) {
int i;

// TXE is cleared by a write to the USART_DR register.

// TXE is set by hardware when the content of the TDR
// register has been transferred into the shift register.

for (i = 0; i < nBytes; i++) {

// wait until TXE (TX empty) is set
// Writing USART_DR automatically clears the TXE flag
while (!(USARTx->SR & USART_SR_TXE));
USARTx->DR = (buffer[i] & 0x1FF);
}

while (!(USARTx->SR & USART_SR_TC)); // wait until TC bit

is set
USARTx->SR &= ~USART_SR_TC;
}
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 Receiving Data

void USART_IRQHandler(USART_TypeDef * USARTx, uint8_t * buffer, uint8_t * pRx_count

if(USARTx->SR & USART_SR_RXNE) { // Received data
buffer[*pRx_counter] = USARTx->DR;
// Reading USART_DR automatically clears the RXNE flag
(*pRx_counter)++;
if((*pRx_counter) >= BufferSize )
(*pRx_counter) = 0;
}
}

void USART1_IRQHandler(void) {
USART_IRQHandler(USART1, USART1_Buffer_Rx, &Rx1_Counter);
}

void USART2_IRQHandler(void) {
USART_IRQHandler(USART2, USART2_Buffer_Rx, &Rx2_Counter);
}

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UART Interrupt:
Receiving Data

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UART Interrupt:
Receiving Data

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UART DMA:
Receiving & Sending

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UART DMA:
Receiving & Sending

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 Voltage Levels
Number of
Max
Standar Max devices
Voltage signal distanc
d speed supported per
e
port
RS-232 Single end ( 100 feet 115Kbit/ 1 master, 1 receiver
logic 1: +5 to +15V, s
logic 0: -5 to -15 V)
RS-422 Differential 4000 10Mbit/ 1 master, 10
(-6V to +6V) feet s receivers
RS-485 Differential 4000 10Mbit/ 32 masters, 32
(-7V to +12V) feet s receivers
Standards:
• How far can signal transfer?
• How fast can it transfer data?
• How many devices supported per port?
• How many masters allowed?

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Bluetooth

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Registers

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Registers

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Registers

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Registers

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Control Register 1 (CR1)

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Control Register 1 (CR1)
Field Bit Description
M1 D28 M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits
M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits
M[1:0] = 10: 1 Start bit, 7 data bits, n stop bits
OVER8 D15 Oversampling mode
0 = Oversampling by 16
1 = Oversampling by 8
M0 D12 Word length
This bit, with bit 28 (M1), determines the word length

PCE D10 Parity Control Enable bit. This will insert a parity bit right after the MSB bit.
0 = no parity bit
1 = parity bit
PS D9 Parity select (used only if PCE is one.)
0 = even parity bit
1 = odd parity bit
TXEIE D7 TXE interrupt enable
0 = disabled
1 = A USART interrupt is generated whenever the TXE flag of USART_SR
is set.
TCIE D6 Transmission complete interrupt enable
0 = disabled
40 1 = A USART interrupt is generated whenever the TC flag of USART_SR is
set.
Control Register 2 (CR2)

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Control Register 2 (CR2)
Field Bit Description
STOP D12-13 These bits are used for programming the stop bits.
00: 1 stop bit
01: 0.5 stop bit
10: 2 stop bits
11: 1.5 stop bits
CLKEN D11 This bit allows the user to enable the CK pin.
0: CK pin disabled
1: CK pin enabled

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Interrupt and status register
(USART_ISR)

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 Interrupt and status register
(USART_ISR)
Field Bit Description
TXE D7 Transmit data register Empty
0 = Data is not transferred to the shift register yet.
1 = The Data Register is empty and ready for the next
byte.
TC D6 Transmit Complete flag (The flag is set by hardware. To
clear the flag, you can write a zero to it. If you read the
USART_SR and then write to the USART_DR register, the
flag will be automatically cleared.)
0 = Transmission is in progress (shift register is
occupied)
1 = Transmission complete (both shift register and Data
Register are empty)
RXNE D5 Receive Data Register not empty flag. This indicates a
byte has been received and is sitting in USART Data
Register and ready to be picked up.
0 = No data is available in USART Data Register.
44 1 = Data is available in USART Data Register and ready
to be picked up.
USART: Character transmission
procedure

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USART: Single byte communication

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USART: Single byte communication

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USART: Character reception procedure

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USART: Character reception procedure

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Example

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Example

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Example

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Example

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Example

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Example

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Example

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