MICROELECTRONICS-I, ECC 305

UNIT-II
B Tech ECE-B (Odd, 2023)
Dr Pavika Sharma BPIT 27-10-2023
NMOS inverter

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
CMOS inverter

VDD

Vin
Vout

CL
 DELAY DEFINITIONS

Vin

50%

t
t t
pHL pLH
Vout
90%

50%

10% t
tf tr
 7

IDEAL INVERTER
VTC is Voltage Transfer Characteristics
 8

NON IDEAL NOISE MARGIN!

VM 2
MAPPING BETWEEN ANALOG AND DIGITAL SIGNALS

V V(y)
"1" OH
Slope = -1
V V
IH OH

Undefined
Region

V Slope = -1
IL VOL
"0"
V
OL V V VOH V(x)
IL IH
DEFINITION OF NOISE MARGINS

"1"
V
OH
NMH
V
Noise Margin High IH
Undefined
Region
Noise Margin Low
NML V
IL
V
OL
"0"

Gate Output Gate Input

DC characteristics

Vout
NMOS off
PMOS res

2.5
NMOS sat
PMOS res

2
NMOS sat

1.5
PMOS sat

1
NMOS res
PMOS sat NMOS res

0.5
PMOS off

0.5 1 1.5 2 2 .5 Vin

 12
Static load MOS inverter/Resistive
Load Inverter

Short Channel Equations for Resistive and

Saturation regions
 13

Once VOH, VOL, VIH, VIL and VM are found, the noise
margins can be determined

Set VI<VT, VOH=VDD

Applying an input VOH=VDD

Transistor is in resistive region,

Or

Transistor Eqn,
 14

Set VGS=VDD, solve for VDS

Solving gives

For VIH and VIL, gain is -1

For VI=VIL transistor is in saturation,

Equate both equations and set gain=-1 and solve

 15

NOISE MARGINS
Pull up/Pull down ratio
Static power dissipation
Dynamic power dissipation
Body Effect
Latch up in CMOS
 28

Combinational Circuits

Output = f(In) Output = f(In, Previous In)

 29

Transistor Switching
Characteristics
 30

MOSFET Pass Characteristics

31
32
 STATIC CMOS
VDD

In1
In2 PUN PMOS Only
In3

F=G

In1
In2 PDN NMOS Only
In3

VSS

PUN and PDN are Dual Networks

NMOS TRANSISTORS IN SERIES/PARALLEL
CONNECTION

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

 PMOS TRANSISTORS IN SERIES/PARALLEL
CONNECTION

PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

COMPLEMENTARY CMOS LOGIC STYLE
CONSTRUCTION (CONT.)
EXAMPLE GATE: NAND
EXAMPLE GATE: NOR
EXAMPLE GATE: COMPLEX CMOS GATE

VDD

B
A
C

D
OUT = D + A• (B+C)
A
D
B C
40
41
42
43
44
45
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
 DYNAMIC CMOS CIRCUITS

Dr Pavika Sharma BPIT 27-10-2023

49
 50

CASCADING DYNAMIC GATES

V

Clk Mp
Clk Mp Clk
Out2
Out1
In
In

Clk Me Clk Me
VTn
Out1

V
Out2

Only 0  1 transitions allowed at inputs!

Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
 55

PROPERTIES OF DOMINO
LOGIC
• Only non-inverting logic can
be implemented
• Very high speed
• static inverter can be
skewed, only L-H transition
• Input capacitance reduced –
smaller logical effort
• Better noise margin
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
 TSPC DYNAMIC CMOS

Dr Pavika Sharma BPIT 27-10-2023

 CHARGE LEAKAGE

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
 CHARGE SHARING

Dr Pavika Sharma BPIT 27-10-2023