SEWP ZC413 Computer
Organization & Architecture
Purushotham BV
Asst. Prof.
Department of CSE
DSCE, Bangalore – 78
94489 19064
utham74@[Link]
01/24/25 µP Introduction, Addressing Mode 1
s, Instructions
Objectives
8086 – Microprocessor
Architecture
Addressing Modes
Instructions
Programming
01/24/25 µP Introduction, Addressing Mode 2
s, Instructions
8086 µP Architecture
CS
DS
20-bit adder
SS FIFO QUE
ES
IP
BIU
AH AL
Control circuitry and
BH BL 16-bit adder instruction decoder
CH CL
DH DL
SP
BP
SI FLAGS EU
DI
01/24/25 µP Introduction, Addressing Mode 3
s, Instructions
8086 µP Architecture
(contd.,)
8086 can divided into two independent functional
blocks.
BIU – Bus Interface Unit
Execution Unit
The BIU is responsible for all memory accesses and
I/O access otherwise BIU communicates outside the
µP.
The EU is responsible for executing the instructions
fetched by the BIU
01/24/25 µP Introduction, Addressing Mode 4
s, Instructions
BIU
The BIU contains IP(instruction Pointer), the
segment registers and Instruction queue.
IP – points to the instruction to be fetched and
executed next, we expect it to holds 20-bits ML
address but its size is 16 - bits.
The 8086 uses memory segmentation, 1 MB of
memory is divided into segments, a maximum of
64KB. Thus a location within a segment can be
addressed using 16-bits.
IT has Code, Data, Stack and Extra segments.
01/24/25 µP Introduction, Addressing Mode 5
s, Instructions
BIU (contd.,)
The 20-bit Physical address is generated as
The IP contains 16-bits offset value or effective address, let
us say 123CH, Let the CS contents be 2345H called segment
base value i.e. CS starts at 2345 X 10 = 23450H and we
need to fetch an instruction from memory location which is
123CH away, hence BIU calculates PA(physical address as
Segment Base Value in CS = 2345H
20-bit address of the CS = 23450H
16-bits Effective address in IP = 123CH
20-bits Physical address = 23450 + 123C=2468CH
Instruction queue – FIFO based instruction queue
(max length of 6) depends on the length of instruction
it enques and deques
01/24/25 µP Introduction, Addressing Mode 6
s, Instructions
Segment & Offset Address
Combinations
Segment Offset Special Purpose
CS IP Instr. Address
SS SP / BP Stack Address
DS BX, DI, SI Data Address
8-bit/16-bit
ES DI for string String dst address
01/24/25 µP Introduction, Addressing Mode 7
s, Instructions
EU
EU consists of GPRs, SRs, FLAGS, ALU and IR
General Purpose Registers – AX, BX, CX and DX, all
are 16-bits long (8-bit also obtained like AL & AH)
Segment registers – DS, SS(SP), ES Registers there
are BP(base pointer), SI(source index) and
DI(destination index) registers all are 16-bits long
FLAGS - xxxxODITSZxAxPxC 15 down to 0 to make
16-bits respectively
C(carry)
P(parity)
01/24/25 µP Introduction, Addressing Mode 8
s, Instructions
EU (contd.,)
A(auxiliary carry set when LS byte produce carry)
Z(zero)
S(sign)
T(trap)
I(interrupt)
D(direction to move string)
O(overflow).
ALU – 16 bits
IR - Control circuitry and instruction decoder
01/24/25 µP Introduction, Addressing Mode 9
s, Instructions
Memory
All addresses are 20-bits long
All data are 16-bits
AD15-AD0 are dual bus i.e., data and
address bus + A19-A16
Byte addressable
The Memory Locations are 00000H –
FFFFFH
Word is 16bits
01/24/25 µP Introduction, Addressing Mode 10
s, Instructions
Addressing Modes of 8086
Four major groups – Immediate, Register, memory
and I/O port addressing modes
Immediate Addressing – transfer immediate data to
destination
e.g., MOV AL, 22H; AL <- 22H MOV
Before After
(AL) FC 22
MOV DX,0034H; DX <- 0034
(DX) 1024 0034
Data is part of Instruction can be 8 or 16 bits
Immediate operand can be always source
01/24/25 µP Introduction, Addressing Mode 11
s, Instructions
Addressing Modes (contd.,)
Register Addressing mode – Transfer byte/word
from source to destination, (memory / register)
Data can be 8 or 16 bits
8 bits can be in any one of AH,AL,BH,BL,CH,
CL,DH or DL and 16 bits can be in any one of
AX,BX,CX,DX,SI,DI,BP or SP, even segment
registers CS,DS,ES and SS
e.g. MOV CX, DX; CX <- [DX]
MOV LOC, BL;
MOV DS,SI;
01/24/25 µP Introduction, Addressing Mode 12
s, Instructions
Addressing Modes (contd.,)
Memory Addressing mode – access data in memory,
20-bits address need to be generated
The 20-bit address is Physical Address(PA) = 16-bit
EA + Starting address of segment
Generally DS is used as segment register
In string instructions ES is generally used as the
segment register
EA is derived using BP and PA is generated using
SS as segment register
There are two types – Direct and Indirect addressing
modes
01/24/25 µP Introduction, Addressing Mode 13
s, Instructions
Addressing Modes (contd.,)
Direct Addressing – transfer a data between a ML
and a register
Here 16-bit EA is provided in the instruction, the 20-
bit PA is generated using DS
e.g., MOV BL,LOC; BL <- (DS:LOC)
MOV CX, LIST; CX <- (LIST)
Indirect addressing – the EA is calculated from the
contents of one or two registers, along with a
displacement value, if any
Types – register, base plus index, register relative,
base relative plus index
01/24/25 µP Introduction, Addressing Mode 14
s, Instructions
Addressing Modes (contd.,)
Register Indirect addressing – transfer data
between register and ML EA is provided in
index or base registers. Index can be SI or DI
but base can only be BX, cannot be BP
e.g., MOV AX,[BX];AX <- [ML=BX +DS]
MOV [DI], 0AC24H
Before After
(DI) A3D2 A3D2
(DS:A3D2) 1246 AC24
01/24/25 µP Introduction, Addressing Mode 15
s, Instructions
Addressing Modes (contd.,)
Base-plus-index – transfer data between a
register and ML addressed by BP/BX and
DI/SI
e.g. MOV [BX+DI],CL;ML=BX+DI+DS<-[CL]
MOV CX,[BP+SI];
MOV [BX+SI],SP;
MOV [BP+DI],AH;
01/24/25 µP Introduction, Addressing Mode 16
s, Instructions
Addressing Modes (contd.,)
Register relative addressing – transfers data
between register and ML addressed by an
index or base + displacement
e.g. MOV AX,[BX+4];
AX <- [ML=DS+BX+ 4]
MOV AX,ARRAY[BX];
AX <- [ML=DS + ARRAY +
BX]
01/24/25 µP Introduction, Addressing Mode 17
s, Instructions
Addressing modes (contd.,)
Base relative-plus-index addressing –
transfer data from register to ML addressed
by an index or base register plus a
displacement
e.g., MOV AX, ARRAY[BX+DI]
or MOV AX, [BX+DI+4]
MOV AX, BX; AX <- [BX]
MOV CL, DH
MOV AX, CS;
MOV DS, AX; copy CS to DS
01/24/25 µP Introduction, Addressing Mode 18
s, Instructions
Addressing modes (contd.,)
I/O Port addressing – ports are the places
with 8-bit registers so that µP can
communicate quickly
Two types – Fixed and Variable port
addressing
01/24/25 µP Introduction, Addressing Mode 19
s, Instructions
Addressing modes (contd.,)
In fixed port addressing, one byte port
address will be provided in the instruction,
change of port is not allowed.
e.g. IN AL, 83H Before After
(AL) 34 78
(port 83) 78 78
IN AX, 83H Before After
(AX) 1234 5678
(port 83) 78 78
(port 84) 56 56
01/24/25 µP Introduction, Addressing Mode 20
s, Instructions
Addressing modes (contd.,)
In variable port addressing, port address will not be in
the instruction, the address of the port is implied to be
the contents of DX always
The program can change the port address as the
execution of program proceeds
e.g. IN AL, DX Before After
(AL) 34 78
(DX) ACBC ACBC
(port ACBC) 78 78
IN AX, DX Before After
(AX) 1234 5678
(DX) ACBC ACBC
(port ACBC) 78 78
(port ACBC) 56 56
01/24/25 µP Introduction, Addressing Mode 21
s, Instructions
A complete ALP
ML MLL OPCODE OPERAND COMMENT
.MODEL TINY; choose single segment model
0000 .CODE ; indicate start of code segment
.STARTUP; indicate start of program
0100 B8 0000 MOV AX,0; place 0000H into AX
0103 BB 0000 MOV BX, 0000H; place 0000H into BX
0106 B9 0000 MOV CX,0; place 0000H into CX
0109 8B F0 MOV SI,AX; copy AX into SI
010B 8B F8 MOV DI,AX; copy AX into DI
010D 8B MOV BP,AX; copy AX into BP
.EXIT; exit to DOS
END; end of file
01/24/25 µP Introduction, Addressing Mode 22
s, Instructions
Model
.Model - provides shortcuts in defining
segments
Model Code Segments Data Segments
Small One One
Medium Multiple One
Compact One Multiple
Large Multiple Multiple
01/24/25 µP Introduction, Addressing Mode 23
s, Instructions
Program
DATA1 DB 23H; define DATA1 as a byte of 23H
DATA2 DW 1000H; define DATA2 as a word of 1000H
START: MOV AL,BL; copy contents of BL to AL
MOV BH,AL; copy contents of AL to BH
MOV CX,200; move 200 decimal to CX
01/24/25 µP Introduction, Addressing Mode 24
s, Instructions
.MODEL SMALL ;SMALL model
0000 . DATA ;start of DS
0000 10 DATA1 DB 10H ;place 10H to DATA1
0001 00 DATA2 DB 0 ;place 0 to DATA2
0002 0000 DATA3 DW 0 ;place 0 to DATA3
0004 AAAA DATA4 DW 0AAAAH; AAAAH to DATA4
0000 .CODE ;start of CS
.STARTUP ; start of programs
0017 A0 0000 R MOV AL, DATA1 ; copy DATA1 to AL
001A 8A 26 0001 R MOV AH, DATA2 ; copy DATA2 to AH
001E A3 0002 R MOV DATA3, AX ; copy DATA3 to BX
0021 88 1E 0004 R MOV BX, DATA4 ; copy DATA4 to BX
.EXIT
END
01/24/25 µP Introduction, Addressing Mode 25
s, Instructions
Instructions
Many instructions will work on 16 as well as 8 bit
data
Instruction template looks like
Byte 1 Byte 2
xxxxxxDW MOD REG R/M
D = 1 then operand1 is destination
D = 0 then operand2 is destination
W = 1 then word operation
w = 0 then byte operation
01/24/25 µP Introduction, Addressing Mode 26
s, Instructions
Instructions (contd.,)
Types
Data movement
Arithmetic & Logical
Program control
Data movement involves transfer between
register and a memory location, immediate,
I/O, stack
01/24/25 µP Introduction, Addressing Mode 27
s, Instructions
Data Transfer Instructions
MOV AX, BX
MOV DS:246H[BP], DX
MOV AX, 25H
MOV LOC, 1234H
MOV AX,DS:34H;
MOV SS:34H, AL;
MOV LOC, AX
01/24/25 µP Introduction, Addressing Mode 28
s, Instructions
Data Transfer Instructions (contd.,)
MOV DS, BX
MOV SS,1234H[BX+SI]
PUSH SI; Before After
(SI) 1234 1234
(SP) 5678 5676
(SS:5676) C5 34
(SS:5677) B2 12
PUSH 83H[SI]
PUSH DS
PUSHF
01/24/25 µP Introduction, Addressing Mode 29
s, Instructions
Data Transfer Instructions (contd.,)
POP SI
POP 83H[SI]
POPF
XCHG AX, SI;
XCHG AX,AX;
XCHG BL, 83H[SI]
IN AL, 83H
IN AL, DX
01/24/25 µP Introduction, Addressing Mode 30
s, Instructions
Data Transfer Instructions (contd.,)
OUT 83H, AX
OUT DX, AL
LEA BX,83H[SI]; BX <- EA
LEA CX,LOCN
LDS BX,82H[SI]; load a register and DS with the
contents of two memory
Before After
(SI) 4600 4600
(DS:4682) 5683 5683
(DS:4684) 6789 6789
(BX) 1234 5683
(DS) 3456 6789
01/24/25 µP Introduction, Addressing Mode 31
s, Instructions
Data Transfer Instructions (contd.,)
LES BX,42H[SI]; load a register and ES with
the contents of two memory
Before After
(SI) 4600 4600
(DS:4642) 5683 5683
(DS:4644) 6789 6789
(BX) 1234 5683
(ES) 3456 6789
LAHF; Load the LS byte of flag register to AH
SAHF; Store the AH contents to Flag
01/24/25 µP Introduction, Addressing Mode 32
s, Instructions
Arithmetic Instructions
ADD AX, BX; Z,S,P,C,A,O are affected
ADD DS:246H[BP],DX
(BP) 0100 0100
(DS:346) 122F 8326
(DX) 70F7 70F7
ADD CL,83H
ADC CX,83H
ADC CL, 43H
INC CL; INC CX
DAA
01/24/25 µP Introduction, Addressing Mode 33
s, Instructions
Subtract Instruction
SUB AX, BX; AX <- [AX] – [BX]
SUB DS:F26H[BP],DX
SUB CL,83H
SUB AX, 83H
SBB DS:F26H[BP],DX
SBB CX,83H
DEC CL; DEC CX
DAS
01/24/25 µP Introduction, Addressing Mode 34
s, Instructions
#Write 8086 ALP to find the
sum of N elements in an array.
.Model SMALL
.DATA
ARRAY DB 63H, 73H, 83H, 93H, F3H
SUM DW 0000H
.CODE
START: MOV AX, @DATA;
MOV DS, AX; For Initializing to Data Segment to Code Segment
XOR DI, DI; Clear DI
MOV CL, N; Initialize a counter
LEA BX, ARRAY; Make BX to point the first location of
ARRAY
MOV AX, SUM; Clear AX
LOOP: ADD AX, [BX+DI]; Add array element storing result in AX
INC DI; Increment DI
DEC CL; Decrement CL
JNZ LOOP; If counter is 00 then stop; otherwise repeat the loop
MOV SUM, AX; Finally move sum to Location SUM
END START; end
END
01/24/25 µP Introduction, Addressing Mode 35
s, Instructions
#Write 8086 ALP to copy N
elements stored at LOC1 to
LOC2.
.MODEL SMALL
.DATA
LOC1 DB 63H, 73H, 83H, 93H, F3H
LOC2 DB 00H, 00H, 00H, 00H, 00H
.CODE
START: MOV AX, @DATA;
MOV DS, AX; For Initializing to Data Segment
XOR DI, DI; Clear DI
MOV CL, 05; Initialize a counter
LEA BX, LOC1; BX to act as a pointer to LOC1
LEA DX, LOC2; DX to act as a pointer to LOC2
LOOP: MOV AX, [BX+DI]; Take element of LOC1 to AX
MOV [DX+DI], AX; Move to LOC2
INC DI; Increment Index value
DEC CL; Decrement counter
JNZ LOOP; If not zero loop back; otherwise end loop
END START; End
01/24/25 µP Introduction, Addressing Mode 36
s, Instructions
Negate & Compare
Instructions
Negate the register or memory contents
NEG DS:246H[BP]
NEG CX; NEG CL
CMP AX, BX;
(AX) 122F 122F
(BX) 70F7 70F7; S = 1, C = 1
CMP DS:246H[BP], DX
CMP CX, 83H; CMP BL, 43H
CBW converts byte to word of AL only
01/24/25 µP Introduction, Addressing Mode 37
s, Instructions
Multiplication Instructions
MUL DS:246H[BP]; DX_AX<-[AX]*ML
(BP) 0100 0100
(DS:346) 0030 0030
(AX) 9180 4800
(DX) 2345 001B
MUL CL; MUL CX
IMUL for signed multiplication
01/24/25 µP Introduction, Addressing Mode 38
s, Instructions
Divide Instructions
DIV DS:0F246H[BP];AX Quo, DX rmdr of
DX_AX ÷ [ML]
If 8-bit AL Quotient and AH rmdr
DIV CL; DIV CX
IDIV for signed division
01/24/25 µP Introduction, Addressing Mode 39
s, Instructions
Logical Instructions
AND AX, BX; AX <- [AX] ^ [BX]
AND DS:0F246H[BP], DX
AND CX,83H;AND CL,83H
OR AX, BX; AX <- [AX] V [BX]
OR DX, DS:0F246H[BP]
OR AX,83H, OR CL, 43H
01/24/25 µP Introduction, Addressing Mode 40
s, Instructions
Logical Instructions (contd.,)
XOR AX,BX
XOR CX, 83H
XOR CX, DS:0F246[BP]
XOR AL,84H
TEST AX, BX; ands AX and BX contents and
store the result in a register not accessible to
programmer, flags are affected
01/24/25 µP Introduction, Addressing Mode 41
s, Instructions
Not and Rotate Instructions
NOT DS:0F246H[BP]
ROL CX,1
ROL BYTE PTR DS:0F246H[BP], CL
ROL BX, CL
ROR CX, 1
ROR WORD PTR DS:0F246[BP], CL
ROR BC, CL
RCL CX,2;RCR CX,2
01/24/25 µP Introduction, Addressing Mode 42
s, Instructions
Shift Instructions
SHR CX,1
SHR BYTE DS:0F246H[BP], CL
SHL CX, 1;SHL BYTE DS:0F246H[BP],CL
SAR CX,1; shift arithmetic right with sign bit
SAR BYTE DS:0F246H[BP], CL
SAL CX,1;
01/24/25 µP Introduction, Addressing Mode 43
s, Instructions
Process Control Instructions
STC set carry; CLC Clear Carry
CMC complement carry
CLI clear the interrupt enable flag
STI set the interrupt enable flag
HLT halt state stops fetching and executing
instructions
01/24/25 µP Introduction, Addressing Mode 44
s, Instructions
Summary
Architecture of 8086
Addressing modes
Instructions
Assembly Language Programming Examples
01/24/25 µP Introduction, Addressing Mode 45
s, Instructions
