DDR

(Double Data Rate)

SRUTHI
Contents
 History
 What is DDR?
 WHY DDR?
 What is DRAM?
 DRAM types
 Commands
 Timing parameters
 On-Die termination
 DRAM Initialization
 Calibration & Trainings
 Error Handlings
 RAS (Reliability, Accessibility, Serviceability)
 History

 Vacuum tubes were the first electronic devices used for memory. Tubes were plagued with problems like
excessive heat, size, and voltage as well as being unreliable and temperamental. This set the stage for
magnetic "core memory".
 Core memory technology used the magnetic properties of ferrite rings, which were manipulated using electrical
currents to store data. While core memory was a significant improvement over vacuum tubes, it was still bulky
and relatively slow.
 Unlike core memory, which required multiple wires to read, write, and erase data, DRAM used a single capacitor
and transistor per bit, which drastically reduced the size and cost of memory while improving speed.
What is DDR?

 DDR SDRAM : Double Data Rate Synchronous Dynamic Random Access Memory.
 Provides ability to read or write two pieces of information in each clock cycle.
 Doubles the bandwidth of the device without increasing the clock speed or Bus width.
 DDR also called system memory.
Why DDR?

1. Faster data transfer rates: DDR memory can transfer data on both the rising and falling edges of the clock
signal allowing faster data transfer rates than SDR memory.
2. Increased bandwidth: The faster data transfer rates of DDR memory also result in increased bandwidth, which
is the amount of data that can be transferred in a given period.
3. Improved power efficiency: DDR memory is more power-efficient than SDR memory, which means that
devices that use DDR memory will consume less power and generate less heat.
4. Higher capacity: DDR memory is available in different versions, such as DDR1, DDR2, DDR3, DDR4, and
DDR5. For example, DDR1 memory has a maximum capacity of 1 GB, while DDR5 memory has a maximum
capacity of 64 GB.
5. Synchronized with the system clock: DDR memory is also known as DDR SDRAM which means that the
memory is synchronized with the system clock.
6. Widely used in various applications: DDR memory is used in many devices, including personal computers,
servers, gaming consoles, and mobile devices.
 DRAM

 DRAM is a dynamic memory (Need continuous refresh) and volatile memory(turn off the power, it looses the
data).

Fig: DRAM cell

Read operation:
 Applying voltage to word line(WL=1), by turning ON the transistor, then the charge across this capacitor
will be available at bit line. This will change the charge on bit line.
 This change in charge will used to determine if we have a 0 or 1 value.
 Capacitor will lose some of its charge during the read operation.
Write operation:
 WL =1,All bit lines are pre charge with some finite values. We want to write particular bit line, in that bit
voltage is applied.
 If applying bit voltage =1(bit line) then transistor turn ON. So whatever voltage is available at bit line that is
transferred to this capacitor.
Hold operation:
 WL=0, transistor is turned off, charge is held on a capacitor.
 It causes leakage currents due to discharging of a capacitor.
DDR SDRAM Basic Structure
 Sense Amplifier
 Sense amplifier is responsible for detecting and amplifying the very small voltage
differences on the bit lines that represent the stored data in a memory cell.

Working of Sense Amplifiers:

 Before a memory read operation, the bitlines are precharged to a reference voltage
(around half of the supply voltage VDD/2)
 When a read operation is initiated, the wordline corresponding to the selected memory
cell is activated. This causes the access transistor to turn on, allowing the charge stored
in the capacitor to be shared with the bitlines.
 The charge sharing creates a small voltage difference between the bitline connected to
the memory cell and its complementary bitline.
 The sense amplifier works in a differential mode, meaning it compares the voltage on
one bitline to the voltage on the complementary bitline.
 The difference is very small (mv), but the sense amplifier can quickly amplify this
difference to full logic levels (0 orVDD​).
 The sense amplifier consists of cross-coupled inverters. When the voltage difference
between the bitlines is detected, the inverters latch onto this difference and quickly
amplify it to the full logic level.
DDR device

Sense
Amplifier
Operation:

 In the above diagram shows the DDR Device, contains timing and controller, Row address buffer, column
address buffer, row address decoder, column address decoder and data buffer blocks are there.
 Example, take 6 bit address bus(3 bits for rows and 3 bits for columns). 0 to 63 cells are present.
 Memory cell is structurally independent, so the arrangement like this. First 3 bits are connected to eight rows
and another 3 are connected to eight columns.
 The address given to arbiter, arbiter select the row and column addresses(If address is 000-000, row and
column address decoder select memory cell 0. If address is 000010(2), address decoder select memory cell 2
can be accessed).
 Based on row address that row will be moved to sense amplifier, after that based on column address select the
column in that cell we can perform read/write.
 DRAM cell

Bank

X8 configuration

Page(amount of data can read/write at a time) No. chips= Rank

DRAM TYPES
Asynchronous DRAM: RAM is not synchronized with the CPU clock
Synchronous DRAM or SDRAM: RAM is synchronized with the CPU clock
SDR: Single data rate. 1 Byte of data for each clock cycle either Pos-edge clock or Neg-edge clock. Same as
synchronous DRAM.
DDR:
 DDR is the primary memory that is directly accessible by CPU. DDR also called system memory.
 Provides ability to read or write two pieces of information in each clock cycle
 Doubles the bandwidth of the device without increasing the clock speed or bus width.
DDR1:
 Double data rate. 2 bytes of data for each clock cycle. One data at posedge and 2 nd data at negedge.
 The voltage has been reduced from 3.3v to 2.5v.
 Operated at 133-200 MHz both clock frequency and internal RAM clock frequency.
 Data rate is doubled so data rate is 266 mega transfer per sec(MTPS).
 184 pins are available.
 Ex : bus frequency=200MHz, data rate is 400 MTPS; i/o bus is 64 bit wide then the data rate is
400*64/8=3200 MBPS.
DDR2:
 Double data rate 2nd generation 4 bytes of data for each clock cycle. 2 bytes at Pos-edge and 2 bytes at Neg-edge.
 It is operated at 1.8v instead of 2.5v. here 4 bits are prefetched during each cycle. Internal bus width is doubled.
 Internal clock frequency =100 MHz; clock frequency =200(2 times); data rate =400 MTPS
 240 pins
DDR3:
 Double data rate 3rd generation 8 bytes of data for each clock cycle. 4 bytes at Pos-edge and 4bytes at Neg-edge.
 Operate at 1.5v/1.35v.
 Internal clock frequency =100 MHz; clock frequency =400(4 times); data rate =800 MTPS
 240 pins
DDR4:
 Double data rate 4th generation 16 bytes of data for each clock cycle. 8 bytes at Pos-edge and 8 bytes at Neg-edge.
 It is operated at 1.2 V. here 8 bits are prefetched during each cycle.
 Internal clock frequency =400 MHz; clock frequency =1600(4 times); data rate =3200 MTPS
 288 pins
MDDR/LPDDR: Low power DDR
 Different generations are there: LPDDR1,LPDDR2,LPDDR3,LPDDR4/LPDDR4X: These are operating
voltage is less compared to DDR RAMS which are used inside laptops and desktops.
GDDR: Graphic DDR
 The rams which are used for the graphic cards is known as the graphic DDR
 GDDR1/GDDR2/GDDR3/GDDR4/GDDR5.
 GDDR operated at higher frequencies so used in higher application scenarios.
 DDR1 DDR2 DDR3 DDR4 DDR5

Released: Around 2000 Around 2003 Around 2007 Around 2014 Around 2020

Speed: 200-400 MHz 400-800 MHz 800-2133 MHz 1600-3200 MHz 3200-6400 MHz
(I/O)
Data Rate: 1.6-3.2 GB/s 3.2-6.4 GB/s 6.4-17 GB/s 12.8-25.6 GB/s 25.6-51.2 GB/s

Voltage: 2.5V 1.8V 1.5V 1.2V 1.1V

Prefetch: 2n 4n 8n 8n 16n

Burst length: 2, 4, or 8 4 or 8 8 8, BC4 16,BC8

Density: 1 GB per DIMM 4 GB 8GB 64GB 128GB

Commands

Function CS’ RAS’ CAS’ WE’ ADDR

Deselect(DES) H X X X X
No operation(NOP) L H H H X
ACTIVE L L H H Bank/Row
READ L H L H Bank/Col
WRITE L H L L Bank/Col
Burst terminate L H H L X
Pre charge L L H L Code
Auto Refresh/Self refresh L L L H X
Mode Register Set L L L L Op-code
Deselect:
The DDR SDRAM cannot execute a commands due to the DESELECT function (CS = High).
No Operation:
This prevents unwanted commands from being registered during idle or wait states.
Active:
The ACTIVE command is used to open a row in a particular bank for access.
Read:
The READ command is used to initiate a burst read operation.
Write:
The WRITE command is used to initiate a burst write operation.
Burst terminate:
The burst terminate command is used to truncate read bursts.
Mode Register set:
Defines operating mode of SDRAM.
Pre-charge:
Deactivates open row in a specified bank.

What is Refresh:
DDR bit cells are made up of capacitors. Capacitor has leakages(charging and discharging), so capacitor
requires periodic refresh(bring it backs to original charge level) is called refresh.

There are 2 types

SELF REFRESH:

There are no commands coming from DDRC to DDR device, at that time DDR Device goes into self refresh
mode is called self refresh.

AUTO REFRESH:

DDRC give a command to DDR Device get into refresh mode is called Auto refresh.
By using both refreshes we can reduce the power consumption.
Timing parameters

 tRAS : Row Active time

 No. of clock cycles required between a row active Cmd and issuing the pre-charge Cmd
 tRP : Row pre-charge time
 No. of clock cycles taken between the issuing the pre-charge cmd and activate cmd
 tCL: CAS latency(Read)
 The No. of clock cycles between read cmd issued to read data present at the memory interface
 tCWL: CAS write latency
 The No. of clock cycles between write cmd issued to write data present at the memory interface
 tWR: write recovery time
No. of clock cycles taken between write data and issuing the pre-charge cmd(data in the write buffer can be
safely written to the memory core.

 tRCD: Row address to Column address delay

 The minimum No. of clock
 Cycles required between opening a row of memory and accessing column within it.

 tCCDL: Command to Command delay

 No. of clock cycles taken between two consecutive commands on the same rank or bank group.

 AL : Additive latency

 With AL, the device allows a READ command to be issued immediately after the ACTIVATE command.
 The command is held for the time of AL before it is issued inside the device. This feature is supported to
sustain higher bandwidths/speeds in the device.
ON-DIE Termination

 A signal propagating from the DDRC to the DRAM encounters an impedance discontinuity at the stub leading to
the DRAM on the module.
 The signal propagates along the stub to the DRAM will be reflected back on to the signal line, thereby
introducing unwanted noise into the signal.
 Why reflections exist in DRAMs?

Multiple DRAMs sharing the same data lines.

Data is targeted to few DRAMs, other DRAMs are in standby mode.

 How this issue resolved?

DDR has termination implemented on the motherboard.

Strating with DDR2 , ODT is implemented to have termination inside of DRAM to minimize the reflection and
improve the signal quality.

Fig: ODT Configuration for DRAM WRITEs Fig: ODT Configuration for DRAM READs
DDR Initialization
STEPS
• Step1: Apply power and assert RESET_n.
• Step2: De assert RESET_n and Wait at least 500us with CKE LOW
• Step3: Start and enable the clock
 assert CKE and drive DES commands
 CKE must remain high at rising CK until initialization is finished
 Issue DES commands
• Step4: Keep ODT off
(Hi-Z until RESET_n is deasserted and CKE is asserted, regardless of ODT pin or MR setting)
• Step 5: Wait
 Wait at least txpr reset CKE Exit time
• Step 6-12 : Load mode registers configuration
• Step 13 : ZQ cal
 Issue ZQCL cmd to start ZQ calibration\
• Step14 : Wait
 Wait until both tDDLk and tZQinit finish
 CKE may now be driven LOW
• Step 15: DONE
 DRAM is now ready for normal operation
Calibration & Training
 ZQ Calibration

 Calibration is required to meet the required signal integrity while DQ and DQS are being driven and being
sampled by DRAM.
 Calibration in DRAM mostly refers to adjusting the impedance values by means of dedicated steps during the
initialization.

2 types of calibration commands:

 ZQ calibration long (512 clocks):ZQCL ZQ calibration long compensates for any amount of drift
 ZQ calibration short (64 clocks):ZQCS ZQ calibration short compensates for small drifts 0.5%.
 ZQ calibration is related to data pins DQ. This pin is
bidirectional.
 It is responsible for sending data back during reads and
receiving data during writes
 ZQ pin to which an external precision (+/- 1%)240Ω
resistor is connected.
 When a ZQCL command is issued during initialization, this
DQ calibration control block gets enabled and it produces a
tuning value. This value is then copied over to each DQ's
internal circuitry.
 This external precision resistor is the ”reference" and it
remains at 240Ω at all temperatures.
 This tuning capability is required to improve signal
integrity, maximize the signal's eye-size and allow the
DRAM to operate at high-speeds.
Vref Training

 Vref (Reference Voltage) Training in DDR memory is a critical step in ensuring reliable data transmission
between the memory controller and the DDR memory modules.
 Vref training optimizes the reference voltage level that the memory controller and the memory devices use to
correctly interpret the voltage levels on the data lines (DQ) during read and write operations.
 Why this training is required?
 Devices are not perfectly alike
 Each device in a rank may need a different VREFDQ setting in

order to achieve the same voltage.

 This Voltage set via MRS commands
 Read/Write Training

 The Controller and PHY have to perform a few more important steps before data can be reliably written-to or
read-from the DRAM. This important phase is called Read/Write Training (or Memory Training or Initial
Calibration) wherein the controller (or PHY)
 Steps:

1. Runs algorithms to align clock [CK] and data strobe [DQS] at the DRAM
2. Runs algorithms and figures out the correct read and write delays to the DRAM
3. Centers the data eye for reads
4. Reports errors if the signal integrity is bad and data cannot be written or read reliably
Why Training is required?

 The picture shows how the data signals and address/command

signals are connected between the ASIC/Soc/Processor and the
DRAMs on the DIMM.
 The Data and Data Strobe (DQ & DQS) are connected to each memory
in a star topology because each memory is connected to a different
portion of the different data lines
 The Clock, Command & Address lines (A, CK, CKE, WE, CSn) on a
DIMM are connected using a technique called fly-by
routing topology.
 This is done because all DRAMs on the DIMM share the same address
lines and fly-by routing is required to achieve better signal integrity
and the high speeds.
Write/Read Levelling

 Since the Clock to Data/Data Strobe skew is different for each DRAM on the DIMM, the memory controller needs
to train itself so that it can compensate for this skew and maintain tDQSs at the input of each DRAM on the
DIMM.
Fig: Write levelling
 Steps:
1. Does a Mode Register write to MR1 to set bit 7 to 1. This puts the DRAM into write-leveling mode. In write-
leveling mode, when the DRAM sees a DataStrobe (DQS), it uses it to sample the Clock (CK) and return the
sampled value back to the controller through the DQ bus.
2. The controller then sends a series of DQS pulses. Since the DRAM is in write-leveling mode, it samples the
value of CK using DQS and returns this sampled value (either a 1 or 0), back to the controller, through the
DQ bus.
3. The controller then
 looks at the value of the DQ bit that is returned by the DRAM
 either increments or decrements the DQS delay and
 launches the next set of DQS pulses after some time

4. The DRAM once again samples CK and returns the sampled value through DQ bus
5. Steps 2 to 4 are repeated until the controller sees a 0-to-1 transition. At this point the controller locks the
DQS delay setting and write-leveling is achieved for this DRAM device.
6. Steps 2 to 5 are then repeated for each DQS for the whole DIMM to complete the write-leveling procedure
7. The DRAMs are finally removed out of write-leveling mode by writing a 0 to MR1[7]
During the read operation, the memory controller must compensate for the delays introduced by the fly-by
topology.
 CA Training

 The purpose of CA training is to ensure that the Command/Address signals are correctly aligned with the clock
signals to guarantee reliable data transfer between the memory controller and the DRAM devices.
 Process of CA Training:
 Initial Setup:
 During the initialization of the DDR memory system, the memory controller and DRAM are in an idle state.
 Pattern Transmission:
 The memory controller sends specific training patterns on the Command/Address bus to the DRAM. These
patterns are carefully chosen to test the timing and integrity of the signals.
 Sampling by DRAM:
 The DRAM devices sample the incoming Command/Address signals based on the received clock signal. Since
there may be timing skew between the clock and data signals due to differences in trace lengths, signal delays, and
other factors, the DRAM needs to adjust its internal timing to correctly interpret the incoming signals.
Adjustment of Delay:

 The memory controller adjusts the delay on the Command/Address signals to ensure they are sampled
correctly by the DRAM. This adjustment is typically done by shifting the phase of the Command/Address
signals relative to the clock signal until the DRAM consistently interprets the training patterns correctly.

Feedback Loop:

 The memory controller monitors the response from the DRAM to determine if the signals are being
correctly sampled. If errors are detected, the controller continues to adjust the delay until the errors are
minimized or eliminated. This process may involve multiple iterations to find the optimal delay setting.

Finalization:

 Once the optimal timing is found, the memory controller locks in the delay settings for the
Command/Address signals. These settings are then used for normal operation of the memory system.
Error Handlings
Errors
 Errors are 2 types
 Hard errors: Errors in cell array

bad cells(permanent hardware faults)

other damage to internal circuit
 Soft errors: Errors which will occur occasionally even when design and fabrication are good
unexpected temperature changes effecting cell leakage
radiation inside the DRAM package
ECC is common method to detect and correct all soft errors
 ECC in DDR memory is a technology designed to detect and correct errors that occur during data storage and transmission.
 ECC ensures data integrity and reliability, particularly in mission-critical applications like servers, data centers, and high-
performance computing.
 ECC in DDR memory involves adding extra bits to the data that can be used to detect and correct single-bit errors, as well as
detect multi-bit errors.
ECC

 ECC in DDR memory is a technology designed to detect and correct errors that occur during data storage and
transmission.
 ECC ensures data integrity and reliability, particularly in mission-critical applications like servers, data centers,
and high-performance computing.
 ECC in DDR memory involves adding extra bits to the data that can be used to detect and correct single-bit errors,
as well as detect multi-bit errors.
How ECC Works:

ECC in DDR memory works by storing additional parity bits alongside the data bits. These parity bits are
generated based on specific error-correcting algorithms, such as Hamming Code or Reed-Solomon code.

[Link] Write Operation:

1. When data is written to the DDR memory, additional parity or check bits are generated based on the
original data.
2. These extra bits are stored in memory alongside the original data.

[Link] Read Operation:

1. When data is read from memory, the ECC circuitry checks the stored data against the parity bits.
2. If a single-bit error is detected, ECC can correct the error on the fly, allowing the correct data to be
returned to the CPU.
3. If a multi-bit error occurs, ECC can detect it, but it may not be able to correct it (depending on the
specific ECC implementation). In such cases, an error report is typically generated.
 CRC

 Cyclic Redundancy Check (CRC) in DDR memory is a feature used to improve data integrity by detecting
transmission errors during data transfers between the memory controller and the DDR memory modules.
 CRC adds a checksum to the data being transferred. This checksum is a value calculated based on the data bits
using a specific algorithm. The memory controller and the DDR module both compute this checksum.
 When data is sent from the memory controller to the DDR memory, or vice versa, the checksum is sent alongside
the data. Upon receipt, the destination device recalculates the checksum and compares it to the transmitted
checksum.
 If the checksums match, the data is considered error-free. If there’s a mismatch, it indicates that an error occurred
during transmission.
 For example, a CRC-8 algorithm is commonly employed in DDR4&5 memory, where an 8-bit checksum is
calculated for every 64 bits of data.
 RAS (Reliability, Accessibility, Serviceability)

 In DDR memory, RAS (Reliability, Availability, and Serviceability) features are designed to improve the
system's overall reliability, ensure continuous availability, and enhance ease of service and maintenance.

 Reliability: RAS features ensure that memory errors are detected and corrected, which is critical for maintaining
data integrity, especially in systems that process sensitive information.
 Availability: By employing techniques like memory mirroring and sparing, RAS features ensure that systems can
continue to operate even when there are memory faults, reducing downtime.
 Serviceability: Technologies like data scrubbing, PPR, and ECC allow for proactive maintenance and error
correction, reducing the need for manual intervention and improving overall system uptime.