Lecture 2
VLSI Testing Process and
Equipment
Types of Testing
Test Specifications and Plan
Test Programming
Test Data Analysis
Automatic Test Equipment
Parametric Testing
Summary
Original slides copyright by Mike Bushnell and Vishwani Agrawal 1
Types of Testing
Verification testing, characterization
testing, or design debug (prototypes)
Verifies correctness of design and of
test procedure – usually requires
correction to design
Manufacturing testing (production test)
Factory testing of all manufactured
chips for parametric faults and for
random defects
Acceptance testing (incoming inspection)
User (customer) tests purchased parts
to ensure quality
2
Testing Principle
3
Characterization Testing
Ferociously expensive (done on
prototypes before mass production)
May comprise:
Scanning Electron Microscope tests
Electron beam testing
Artificial intelligence (expert system)
methods
Repeated functional tests
4
Characterization Testing
Worst-case test
Choose test that passes/fails chips
Select statistically significant sample of chips
Repeat test for every combination of 2+
environmental variables (Temp, Freq, Volt…)
Plot results in Shmoo plot
Diagnose and correct design errors
Less comprehensive characterization testing
continues throughout production life of chips to
improve design and process to increase yield
5
Shmoo Plot
CS
tOTD
DATA
SRAM read operation:
tOTD = time to DATA
tristated after
chip deselect
6
Manufacturing Test
Determines whether every manufactured
chip meets specs
Must cover high % of modeled faults
Must minimize test time (to control cost)
No fault diagnosis (go/no-go decision)
Tests every device on chip
Perform test at the speed required by the
application or at speed guaranteed by the
supplier
7
Burn-in or Stress Test
Process:
Subject chips to high temperature &
over-voltage supply, while running
production tests
Catches:
Infant mortality cases (10-30 hours) –
these are damaged chips that will fail in
the first 2 days of operation – causes bad
devices to actually fail before chips are
shipped to customers
Freak failures – They require longer
burn-in hours (100-1000)
8
Incoming Inspection
Can be:
Similar to production testing or
More comprehensive than production
testing or even
Tuned to specific systems application
Often done for a random sample of devices
Sample size depends on device quality
and system reliability requirements
Avoids putting defective device in a
system where cost of diagnosis exceeds
incoming inspection cost
9
Types of Manufacturing
Tests
Wafer sort or probe test – done before
wafer is scribed and cut into chips
Includes test site characterization –
specific test devices are checked with
specific patterns to measure:
Gate threshold
Polysilicon field threshold
Poly sheet resistance, etc.
Packaged device tests
10
Sub-types of Tests
Parametric – measures electrical
properties of pin electronics – delay,
voltages, currents, etc. – fast and cheap
Functional – used to cover very high % of
modeled faults – test every transistor and
wire in digital circuits – long and
expensive – main topic of tutorial
11
Test Specifications & Plan
Test Specifications are based on:
• Device functional Characteristics
(algorithms implemented, timing
waveforms, clock rate)
• Type of Device Under Test (DUT) (logic,
memory, microprocessor, analog)
• Physical Constraints – Package, pin
numbers, etc.
• Environmental Characteristics – supply,
temperature, humidity, etc.
• Reliability – acceptance quality level
(defects/million), failure rate per 1000
hours, etc.
12
Test Specifications & Plan
Test plan generated from specifications
• Type of test equipment to use
• Types of tests
• Fault coverage requirement
13
Test Programming
Test program contains sequence of instructions that
a tester would follow to conduct testing
14
Test Data Analysis
ATE test data serve 3 purposes:
• Reject bad DUTS
• Fabrication process information
• Design weakness information
Devices that did not fail are good only if
tests covered 100% of faults
Failure mode analysis (FMA)
• Diagnose reasons for device failure, and
find design and process weaknesses
• Allows improvement of logic & layout
design rules
15
Automatic
Automatic Test
Test Equipment
Equipment
(ATE)
(ATE)
16
Automatic Test Equipment
Components
Consists of:
• Powerful computer
• Powerful 32-bit Digital Signal
Processor (DSP) for analog testing
• Test Program (written in high-level
language) running on the computer
• Probe Head (actually touches the bare
or packaged chip to perform fault
detection experiments)
• Probe Card or Membrane Probe
(contains electronics to measure
signals on chip pin or pad)
17
ADVANTEST Model T6682
ATE
18
T6682 ATE Specifications
Uses 0.35 m VLSI chips in
implementation
1024 pin channels
Speed: 250, 500, or 1000 MHz
Timing accuracy: +/- 200 ps
Drive voltage: -2.5 to 6 V
Pattern multiplexing: write 2 patterns in
one ATE cycle (double operating freq)
Pin multiplexing: use 2 pins to control 1
DUT pin (double data transfer rate)
19
T6682 ATE Block Diagram
20
Pattern Generation
Sequential pattern generator (SQPG): stores
16 Mvectors of patterns to apply to DUT,
vector width determined by # DUT pins
Algorithmic pattern generator (ALPG): 32
independent address bits, 36 data bits
• For memory test – has address
descrambler
Address failure memory (AFM): records
addresses in memory that failed
Scan pattern generator (SCPG) supports
JTAG boundary scan, greatly reduces test
vector memory for full-scan testing
• Can have 2 Gvector or 8 Gvector sizes
21
Response Checking and
Frame Processor
Response Checking:
• Pulse train matching – ATE matches
patterns on 1 pin for up to 16 cycles
• Pattern matching mode – matches
pattern on a number of pins in 1 cycle
• Determines whether DUT output is
correct, changes patterns in real time
Frame Processor – combines DUT input
stimulus from pattern generators with
DUT output waveform comparison
Strobe time – interval after pattern
application when outputs are sampled
22
Probing
Pin electronics (PE) – electrical buffering
circuits, put as close as possible to DUT
Test head interface through custom printed
circuit board to wafer prober (unpackaged
chip test) or package handler (packaged
chip test)
Uses liquid cooling
Can independently set VIH , VIL , VOH , VOL ,
IH , IL , VT for each pin
Parametric Measurement Unit (PMU)
• It applies signals at pins and measure
electrical responses on same pin
23
T6682 ATE Software
Runs Solaris UNIX on UltraSPARC 167
MHz CPU for non-real time functions
Runs real-time OS on UltraSPARC 200
MHz CPU for tester control
Peripherals: disk, CD-ROM, floppy disk,
monitor, keyboard, HP GPIB, Ethernet
interface
Viewpoint software provided to debug,
evaluate, & analyze VLSI chips
24
LTX FUSION HF ATE
25
Specifications
Intended for SOC test – digital, analog, and
memory test – supports scan-based test
Modular – can be upgraded with additional
instruments as test requirements change
enVision Operating System
1 or 2 test heads per tester, maximum of
1024 digital pins, 1 GHz maximum test rate
Maximum 64 Mvectors memory storage
Analog instruments: DSP-based synthesizers,
digitizers, time measurement, power test, RF
measurement …
26
Multi-site Testing – Major
Cost Reduction
One ATE tests several (usually identical)
devices at the same time
Done for both probe and package test
DUT interface board has > 1 sockets
Add more instruments to ATE to handle
multiple devices simultaneously
Usually test 2 or 4 DUTS at a time, usually
test 32 or 64 memory chips at a time
Limits: # instruments available in ATE,
type of handling equipment available for
a given package type
27
Electrical
Electrical Parametric
Parametric
Testing
Testing
28
Typical Test Program
1. Probe test (wafer sort) – catches gross
defects
2. Contact electrical test
3. Functional & layout-related test
4. DC parametric test
5. AC parametric test
6. 1, 2, 4, 5 are electrical tests:
• Unacceptable voltage/current/delay at
pin
• Unacceptable device operation limits
29
DC
DC Parametric
Parametric Tests
Tests
30
Contact Test
Verify that pins have no shorts or opens
1. Set all inputs to 0 V
2. Force current Ifb out of pin (expect Ifb to
be 100 to 250 A)
3. Calculate pin resistance R
Contact short (R = 0 ) Failure
No problem Pass
Pin open circuited (R huge) Failure
31
Power Consumption Test
1. Set temperature to worst case, open
circuit DUT outputs
2. Measure maximum device current
drawn from supply ICC at specified
voltage
ICC > 70 mA (fails)
40 mA < ICC 70 mA (ok)
32
Output Short Current Test
1. Make chip output a 1
2. Short output pin to 0 V in PMU
3. Measure short current (but not for long,
or the pin driver burns out)
Short current > 40 A (ok)
Short current 40 A (fails)
33
Output Drive Current Test
1. Apply vector forcing pin to 0
2. Simultaneously force VOL voltage
(0.4V) and measure IOL
3. Repeat Step 2 for logic 1, VOH(2.4V),
IOH
IOL < 2.1 mA (fails)
IOH < -1 mA (fails)
34
Threshold Test
1. For each I/P pin, write logic 0 followed by
propagation pattern to output. Read
output. Increase input voltage in 0.1 V
steps until output value is wrong
2. Repeat process, but stepping down from
logic 1 by 0.1 V until output value fails
Wrong output when 0 input > 0.8 V (ok)
Wrong output when 0 input 0.8 V
(fails)
Wrong output when 1 input < 2.0 V (ok)
Wrong output when 1 input 2.0 V
(fails)
35
AC
AC Parametric
Parametric Tests
Tests
36
Rise/fall Time Tests
37
Set-up and Hold Time Tests
38
Propagation Delay Tests
1. Apply standard output pin load (RC or
RL)
2. Apply input pulse with specific rise/fall
3. Measure propagation delay from input
to output
Delay between 5 ns and 40 ns (ok)
Delay outside range (fails)
39
Summary
Parametric tests – determine whether pin
electronics system meets digital logic voltage,
current, and delay time specs
Functional tests – determine whether internal
logic/analog sub-systems behave correctly
ATE Cost Problems
Pin inductance (expensive probing)
Multi-GHz frequencies
High pin count (1024)
ATE Cost Reduction
Multi-Site Testing
DFT methods like Built-In Self-Test
40
