MOS Transistor Switches
MOS Technology
• MOS technology derives its name from the basic structure of a metal
electrode, over an oxide insulator, over a semi-conductor substrate.
• Transistors of MOS technology are field-effect transistors—called MOSFETs.
NMOS operation
• Body is commonly tied to ground (0 V)
• When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2
0
n+ n+
S D
p bulk Si
• When the gate is at a high voltage:
• Positive charge on gate of MOS capacitor
• Negative charge attracted to body
• Inverts a channel under gate to n-type
• Now current can flow through n-type silicon from source through channel
to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2
1
n+ n+
S D
p bulk Si
Advantages and Disadvantages
MOSFETs are relatively
• simple and inexpensive to fabricate,
• small, and
• consume very little power.
• The principal disadvantage of MOS devices is their susceptibility to
static-electricity damage
Enhancement and Depletion mode
• Enhancement-mode MOSFETs are the common switching elements in
most MOS.
• These devices are OFF at zero gate–source voltage,
• NMOS can be turned on by pulling the gate voltage higher than the
source voltage,
• PMOS can be turned on by pulling the gate voltage lower than the
source voltage.
• In a depletion-mode MOSFET, the device is normally ON at zero gate–
source voltage.
NMOS PMOS
NMOS Inverter PMOS Inverter
NMOS inverter
NMOS NAND GATE NMOS NOR GATE
CMOS
• P-MOS & N-MOS transistors in the same circuit.
• Complementary MOS, or CMOS, technology.
CMOS INVERTER
• The CMOS INVERTER has two MOSFETs in series.
• The P-channel device source is connected to VDD .
• The N-channel device has its source connected to ground—usually labeled
VSS.
CMOS NAND GATE
Vdd Vdd
Vdd
ON ON OFF ON
Y
Y=1 Y=1
A A=0 A=0
OFF OFF
B
B=0 B=1
OFF ON
Vdd Vdd
OFF OFF OFF
ON
Y=1 Y=0
A=1 A=1
ON ON
B=0 B=1
OFF ON
CMOS NOR GATE
CMOS characteristics
• combines high speed with low power consumption
• usually operates from a single supply of 5 – 15 V
• excellent noise immunity of about 30% of supply voltage
• High fan-out : can be connected to a large number of gates (about 50)
• CMOS gates have equal [Link] PMOS and NMOS
• CMOS inverter has a very high input resistance
ECL
• The emitter-coupled logic (ECL) family operates on the principle of
current switching
• A fixed bias current less than IC (sat) is switched from one transistor’s
collector to another.
• Also referred to as current-mode logic (CML).
Basic ECL Circuit
VCC
VI VBB QI is OFF VINV is High
QR is FA VNINV is Low
VI VBB QI is FA VINV is Low
VNINV is High
Basic ECL Circuit
with emitter follower
OR/NOR GATE
ECL Characteristics
• Very fast switching with typical propagation delay of 360 ps—faster than TTL or
CMOS.
• The standard ECL logic levels are nominally -0.8 V and -1.7 V for logical 1 and 0
respectively. - Negative power supply
• Worst-case noise margins approximately 150 mV.
• ECL logic gates usually produce an output and its complement, eliminating the need
for inverters.
• Current flow remains constant, eliminating noise spikes
• High power dissipation due to constant current flow
Logic families: Comparison
TTL ECL CMOS
Base Gate NAND OR/NOR NAND/NOR
Fan-in 12-14 >10 >10
Fan-out 10 25 50
Power dissipation (mW) 10 175 0.001
Propagation Delay (ns) 10 <3 lowest 15 Highest
Noise Margin 0.5V 0.16V (lowest) 1.5 V(Highest)
Noise immunity Very good good excellent
