DIGITAL VLSI

DESIGN
PROGRAM ELECTIVE-1
Course Code: R5EL3101T
MODULE 1: DIGITAL VLSI
CIRCUITS
 What is VLSI?
 VLSI Very Large Scale Integration
 VLSI refers to the process of integrating thousands to millions of transistors on a single chip to create complex electronic
circuits.
 How Large?
Year Integration Level Transistor Count
1950s Small Scale Integration (SSI) : 1 – 100 transistors
1960s Medium Scale Integration (MSI) 100 – 1000 transistors
1970s Large Scale Integration (LSI) 1000 – 100,000 transistors
1980s VLSI Several million transistors
1990s Ultra Large Scale Integration Over 1 million transistors
(ULSI)
2010 Giga Scale Integration (GSI) Over 1 billion transistors

Table contents: "Unraveling the Chip Evolution: From SLI to GSI - A Journey through Integration Milestones!
 So, why do we study VLSI?
1. Foundation of Modern Electronics

VLSI enables the design of microprocessors, memory chips, smartphones, laptops, and IoT devices.

2. Career Opportunities

High demand in companies like Intel, AMD, Qualcomm, NVIDIA, Apple, Samsung, and startups.

3. Design Thinking & Innovation

Teaches how to build complex systems from simple logic gates.

4. Miniaturization and Speed

VLSI is the reason why devices are getting faster, smaller, and more power-efficient.

5. Practical Applications

Used in AI/ML accelerators, biomedical implants, automotive electronics, communication systems, and defense.
 Moore’s Law
 Moore’s Law is an empirical observation made by Gordon Moore, co-founder of Intel, in 1965.

 He quoted “The number of transistors on a chip doubles approximately every 18 to 24 months, leading to exponential
growth in computational power and reduction in cost per function”.

 Moore’s Law is driven primarily by scaling down the size of transistors and, to a minor extent, by building larger chips.

 Fig. 1 shows that the number of transistors in Intel microprocessors has doubled every 26 months.

Fig. 1. Transistors in Intel microprocessors [Intel10]

PC:”CMOS VLSI Design” by Neil H.E. Weste and David Harris
 VLSI Design Flow
SPECIFICATIONS
F
R
ARCHITECTURAL DESIGN O
N
T
RTL CODING
E
N
FUNCTIONAL D
VERIFICATION

LOGIC SYNTHESIS
B
A Fig. 2. Design Hierarchy
PHYSICAL DESIGN C
K
FABRICATION
E
N
TESTING AND PACKAGING D

PC: [Link]
Specification

LOGIC Synthesis: Gate-Level Netlist

RTL Coding and Simulation

Floorplanning

Physical Design Transistor Level

Layout
IC Fabrication
 Specification – Defining the functionality, performance, and interfaces.

 Architecture Design – High-level description of system components.

 RTL Design (Register Transfer Logic) – Behavioral modeling using languages like Verilog or VHDL.

 Logic Synthesis – Converting RTL into a gate-level netlist.

 Physical Design – Placement and routing of components on silicon.

 Fabrication – Manufacturing the chip in a semiconductor foundry.

 Testing & Packaging – Testing chips for defects and encapsulating for deployment.
 Companies that hire for VLSI/Semiconductor manufacturing:
1. Ansys (now merged into Synopsys) 12. Texas Instruments India
2. Analog Devices
13. MediaTek
3. NVIDIA
14. Samsung Semiconductor
4. Qualcomm
15. Micron Technology
5. Synopsys Inc
16. Marvell Technology
6. Cadence

7. STMicroelectronics 17. NXP India

8. IBM 18. Renesas Electronics

9. Intel Corporation 19. Western Digital

10. AMD
20. GlobalFoundries
11. Broadcom
Introduction to MOS transistor theory
 Fig. 3. Baisc Elements
• Advantages of semiconductors over conductors is their ability to control the flow of current.

• This is achieved by doping the semiconductor with impurities, which creates an excess or deficiency of
electrons, resulting in the formation of p-type and n-type semiconductors.

• While conductors are materials that generally allow electricity to flow, the actual flow of current depends
on the presence of an electrical potential difference (voltage) across the conductor and the ability to
establish a complete circuit.
PC: [Link]
 What is a Transistor?
 A transistor is a miniature device that is used to control or regulate the flow of electronic
signals.
OR
A transistor is a semiconductor that amplifies or switches electronic signals and serves as the
basic building blocks of modern electronics.

BIPOLAR JUNCTION METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR

TRANSISTOR (BJT) (MOSFET)

NPN PNP
N-CHANNEL P-CHANNEL
 Why MOSFET is preferred or used over BJTs?

BJTs MOSFETs

1. Low switching speed 1. Faster switching speed

2. High power consumption 2. Low power consumption

3. Cannot be easily scaled down. 3. Can be easily scaled down for compact
circuitry
4. Input impedance is low 4. Input impedance is nearly infinite.

5. Current controlled device 5. Voltage controlled device

6. Current can be controlled by controlling 6. Current can be controlled by only

the Base Width controlling the Gate Voltage
 MOS transistor theory
ENHANCEMENT MOSFET

N-CHANNEL P-CHANNEL

DEPLETION MOSFET

N-CHANNEL P-CHANNEL
Fig. 9. N-channel MOSFET

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
o The MOS transistor is a majority-carrier device.

o The transistor consists of the MOS stack between two n-type regions called the source and drain.

o The current conducting between the source and drain is controlled by a voltage applied to the gate.

o In an nMOS transistor, the majority carriers are electrons; in a pMOS transistor, the majority carriers are holes.

o The top layer of the structure is a good conductor called the gate made up of polysilicon.

o Polysilicon: Silicon formed from many small crystals.

o The middle layer is a very thin insulating film of SiO2 called the gate oxide.

o The bottom layer is the doped silicon body, here p-type in which the carriers are holes.

o The body is grounded and a voltage is applied to the gate.

o The gate oxide is a good insulator so almost zero current flows from the gate to the body.

• The simple operation principle of MOSFET: It control the current conduction between the
source and the drain, using the electric field generated by the gate voltage.
Accumulation: Transistor is OFF Depletion: Negatively charged ions are Surface Inversion: The surface of
now present at the surface of the p-substrate the p-type has now inverted as the substrate
due to formation of the Depletion region semiconductor becomes n-type

Fig. 9. Effect of VGS on N channel-MOSFET

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 NMOS OPERATION
 At , the channel is depleted; no carrier flow can be observed in the channel.

 At , an n-type conducting channel forms between S and D, which can carry .

 If a , an will flow from S to D through the conducting channel, called the linear mode.

o If is small, the transistor acts as a linear resistor in which the current flow () is proportional to

 As the inversion layer charge and the channel depth at the drain end start to decrease.

 For , the inversion charge at the drain is reduced to zero, which is called the pinch-off point.

 Beyond the pinch-off point, i.e., for , a depleted surface region forms adjacent to the drain.

 This operation mode of the MOSFET is called the saturation mode or the saturation region.

 A high-field region forms between the channel-end and the drain boundary.

 Electrons arriving from the S to the channel-end are injected into the drain-depletion region and are accelerated
toward the drain in this high electric field, usually reaching the drift velocity limit.
 Fig. 10. NMOS operating in the linear Fig. 11. NMOS at the edge of saturation
region

Fig. 12. NMOS beyond saturation

The value of the gate-to-source voltage VGS needed to cause surface inversion (to create the conducting channel) is called
the threshold voltage Vth.
 PMOS voltages:

Threshold voltage,

Fig. 13. P channel-MOSFET

PMOS Operation
o The PMOS transistor in Fig. 13 operates in just the opposite fashion as that of NMOS.
o The n-type body is tied to a high potential so the junctions with the p-type source and drain are normally reverse-
biased.
o When the gate is also at a high potential, no current flows between drain and source.
o When the gate voltage is lowered by a threshold , holes are attracted to form a p-type channel immediately
beneath the gate.
o current flow between drain and source.
PC: CMOS VLSI design a circuits and systems perspective (4th edition solution) by Neil H. E. Weste and David Harris
 MOSFET Modes of Operation

SATURATION
CUT-OFF
CONDITIONS:
CONDITIONS: N-Channel: ; ;
N-Channel: ; ; P-Channel: ; ;
P-Channel: ; ;
TRIODE/LINEAR

CONDITIONS:
N-Channel: ; ;
P-Channel: ; ;

= Threshold value of the MOSFET

 MOSFET Current-Voltage Characteristics

Fig. 14. Channel charge with equal/zero source and drain voltages

 Considering ,

 We assume the ONSET of inversion layer takes place at .

 The inversion charge density is proportional to (effective voltage that creates the inversion layer)

PC: Design of Analog CMOS Integrated Circuits, Second Edition by Razavi

 Channel charge density (charge per unit length along the source-drain path) equal to

where is multiplied by W to represent the total capacitance per unit length.

 On applying a positive voltage.

 Since the channel potential varies from zero at the source to at the drain, the local voltage difference between the
gate and the channel varies from (near the source) to − (near the drain).

Fig. 15. Channel charge with unequal source and drain voltages
Current density at a point x along the channel:

For semiconductors, , where is the mobility of charge carriers and is the electric field, equal to .

𝑑𝑉
𝐼 𝐷 =𝑊𝐶
Applying the boundary condition as (because𝑜𝑥 [𝑉 and
Vs=0) −𝑉 𝑥 − 𝑉 𝑇h ] 𝜇
𝐺𝑆 V(L)=
𝑑𝑥

𝐿 𝑉 𝐷𝑆

∫ 𝐼 𝐷 𝑑𝑥= ∫ 𝑊𝐶𝑜𝑥 [ 𝑉 𝐺𝑆 −𝑉 − 𝑉 𝑇h ] 𝜇 𝑑𝑉
0 0

𝐼 𝐷 =𝜇(𝑊 / 𝐿)𝐶 𝑜𝑥 ¿
 MOSFET as a Linear Resistor
If

𝑰 𝑫 =𝝁(𝑾 / 𝑳)𝑪 𝒐𝒙 (𝑽 ¿ ¿ 𝑮𝑺 −𝑽 𝑻𝒉 )𝑽 𝑫𝑺 ¿
that is, the drain current is a linear function of .

The linear relationship implies that the path from the source to the drain can be represented by a linear resistor equal
to

With the condition we say the device operates in the deep triode region.

PC: Design of Analog CMOS Integrated Circuits, Second Edition by Razavi

 Output Characteristics of MOSFET

gion
Re
de
io
Tr

Fig. 16. Output characteristics

At,

Fig. 17. Pinch-off behaviour

PC: Design of Analog CMOS Integrated Circuits, Second Edition by Razavi
 Input Characteristics of MOSFET

(a) (b)

Fig. 19. N-Channel Enhancement type MOSFET (a) Transfer and (b) Output Characteristics
PC: [Link]
From the graph:
At low 𝑉𝐷𝑆=0.1 𝑉: The curve is nearly linear once 𝑉𝐺𝑆>𝑉𝑡ℎ​.
At moderate 𝑉𝐷𝑆=0.5 𝑉: The transition from linear to saturation is visible.
At high 𝑉𝐷𝑆=1.5 𝑉: The MOSFET enters saturation early, and 𝐼𝐷​ rises quadratically with
𝑉𝐺𝑆.
Fig. 20. P-Channel Enhancement type MOSFET (a) Transfer and (b) Output Characteristics
 Depletion and Enhancement type of MOSFETS
ENHANCEMENT TYPE MOSFETs DEPLETION TYPE MOSFETs
1. OFF device at =0 V 1. Always ON device
2. At to be at a positive 2. At to be at a positive
potential, the device is ON and potential, the device is already
flows for > 0 ON and Ids is flowing for > 0
3. At = -, device is OFF 3. At = -, device is OFF
 Threshold Voltage
 The most general expression of the threshold voltage VT can be found as follows:

where,
 The substrate Fermi potential is negative in NMOS, positive in PMOS.

 The substrate bias coefficient is positive in NMOS, negative in PMOS.

 The substrate bias voltage is positive in NMOS, negative in PMOS.

 Typically, the of an enhancement-type n-channel MOSFET is a positive quantity,

whereas the threshold voltage of a p-channel MOSFET is negative.
 Channel Length Modulation
 Channel length modulation (CLM) is an effect in FETs, a shortening of the length of the inverted channel region with
increase in large drain biases.
 The result of CLM is an increase in current with drain bias.
 As increases, the triode region transitions to the saturation region, in which is (ideally) independent of .
 With pinch-off the channel length decreases by (where L=Channel Length)
 The resistance of the channel is inversely proportional to its W/L ratio; reducing the length leads to decreased resistance and
hence higher current flow.
 CLM means that the saturation-region drain current will increase slightly as increases.
 One of the prominent effects in short-channel FETs.

Fig. 21. NMOS in saturation

PC: [Link] articles/mosfet-channel-length-modulation/
 Ideally, at saturation region:

On introducing CLM,

, where =CLM factor

By Taylor series expansion:

So, the saturation current equation due to CLM is:

 MOSFET Capacitances
• The channel length, L due to G-S and G-D
overlap:

MOSFET capacitances can be classified

into three major groups:
1. Oxide Capacitance = (
2. Overlap Capacitances
3. Junction capacitances
Fig. 21. Cross-sectional view and top view of a typical n-channel
MOSFET
PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 Overlap Capacitance: The two oxide capacitances that arise because of the
structural arrangement are called (overlap) and (overlap), respectively.
 and are voltage-independent and always exists.

Fig. 22. Schematic representation of MOSFET oxide capacitances during cut-off

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 Oxide Capacitance: The GATE is connected to the S, D, and substrate, three capacitances
between the G and these regions, i.e.,, and respectively.

 In cut-off region, and

 In linear-mode operation, the inverted channel extends across the MOSFET, between S and D.

Fig. 23. Schematic representation of MOSFET oxide capacitances during linear

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 When the MOSFET is operating in saturation mode, the inversion layer on the surface does not
extend to the drain, but it is pinched off
,

Fig. 24. Schematic representation of MOSFET oxide capacitances during saturation

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 Fig. 25. Variation of the distributed (gate-to-channel) oxide capacitances as functions of VGS.

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 Junction Capacitances: The source-substrate and drain-
substrate junction capacitances are and , respectively.

 These capacitances are due to the depletion charge

surrounding the respective source or drain diffusion regions
in the substrate.

 NOTE: These junctions are reverse-biased under normal

operating conditions of the MOSFET and that the amount of Fig. 26. Lumped representation of
the parasitic MOSFET capacitances.
junction capacitance is a function of the applied terminal
voltages.

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 CMOS (Complementary MOSFET)

Fig. 27. Basic Inverter

Fig. 28. Ideal Inverter Voltage Transfer Characteristics

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 Voltage Transfer Characteristics (VTC) of CMOS
Critical
voltages

Fig. 30. General circuit structure of an NMOS inverter

Fig. 31. VTC of the NMOS inverter

 For very low input voltage levels, the output voltage = high value of
(output high voltage)

 In this case, the NMOS is in cut-off, and hence, does not conduct any
current.

 The voltage drop across the load is very small in magnitude, and the
output voltage level is high.

 As the increases, the NMOS starts conducting a certain drain current,

and the output voltage starts to decrease.

 Two critical voltage points on this curve, where the slope of VTC is-
1, i.e., Fig. 31. VTC of the NMOS inverter
 The smaller input voltage value satisfying this condition is called the input low voltage and the larger input
voltage satisfying this condition is called the input high voltage .

 Inverter threshold voltage,, is considered as the transition voltage at the point where Vin = Vout

 VOH: Maximum output voltage when the output level is logic " 1"

VOL: Minimum output voltage when the output level is logic "0"

VIL: Maximum input voltage which can be interpreted as logic "0"

VIH: Minimum input voltage which can be interpreted as logic " 1"

 Logic levels in digital circuits are not represented by quantized voltage values, but rather by voltage ranges

corresponding to these logic levels.

 Noise Margin of CMOS Inverter
 The ability of an inverter to interpret an input signal within a voltage range as either a “0" or "1"
allows digital circuits to operate with a certain tolerance to external noises.

 Here the circuit noise corresponds to

 unwanted signals that are coupled to some part of the circuit
 Neighboring lines (usually interconnection lines) by capacitive or inductive coupling
 outside of the system

 The result of this interference is that the signal level at one end of an interconnection line may be
 Assume all inverters are identical, and that the input voltage of the first inverter .

 The output voltage of the first inverter

 Now, is being transmitted to the next inverter input via an interconnect, which could be a metal or
polysilicon line connecting the two gates.

 On-chip interconnects are generally prone to signal noise.

 Due to noise the input to the next inverter or

 Hence, = Maximum allowable voltage which is low enough to ensure a logic "1" output.

Fig. 32. Propagation of digital signals under the influence of noise.

 Second inverter produces an output voltage level of .

 Due to noise the voltage level at the input of the third inverter will be different from .

 If the input voltage of third inverter then this signal will be interpreted correctly as a logic " 1".

 If the voltage level due to noise, however, the input cannot be interpreted as a logic "1."

 Consequently, = Minimum allowable voltage at the input of the third inverter which is logic "0" output.
 Noise immunity of the circuit increases with
NM.

 Two noise margins will be defined: noise

margin for low signal levels () and noise
margin for high signal levels ().

Fig. 33. Definition of Noise margin and

 The important/critical voltages are given below:

VOH: Maximum output voltage when the output level is logic “1”

VOL Minimum output voltage when the output level is logic "0"

VIL: Maximum input voltage which can be interpreted as logic "0"

VIH: Minimum input voltage which can be interpreted as logic "1”

 = Any input voltage level between the lowest available voltage in the system (usually ground)
and is interpreted as a logic "0" input.

 = Any input voltage level between the highest available voltage in the system (usually ) and is
interpreted as a logic " 1 " input.

 = Any output voltage level between the lowest available voltage in the system and is
interpreted as a logic "0" output,

 = Any output voltage level between the highest available voltage in the system and is
interpreted as a logic " 1 " output.
 CMOS Inverter Operation
 COMPLIMENTARY MOSFET: Consists of an enhancement-type NMOS transistor and an enhancement-type
PMOS transistor.

 The circuit topology is complementary push-pull network.

 For high input, the NMOS transistor drives (pulls down) the output node while the PMOS transistor acts as the
load.

 For low input, the PMOS transistor drives (pulls up) the output node while the NMOS transistor acts as the load.
 ADVANTAGES:
 Steady-state power dissipation of the CMOS inverter circuit is negligible.
 VTC exhibits a full output voltage swing between 0 V and VDD. Ratio less functionality?
 VTC transition is usually very sharp and resembles an ideal INVERTER.
 NM is high
Voltage Transfer Characteristics (VTC) of CMOS
 REGION A: : NMOS IS OFF AND PMOS IS IN LINEAR
 REGION B: : NMOS IS SATURATION AND PMOS IS IN LINEAR

begins to decrease,
 REGION C: : NMOS IS SATURATION AND PMOS IS ALSO IN SATURATION
 REGION D: NMOS IS IN LINEAR AND PMOS IS ALSO IN SATURATION
 REGION E: : PMOS IS OFF AND NMOS IS IN LINEAR and
Calculation of (Inverter Switching Threshold):
The inverter threshold voltage is defined as .
Inverter threshold voltage emerges as an important parameter characterizing the DC performance of the inverter.
Since the CMOS inverter exhibits large noise margins and a very sharp VTC transition.
For , both transistors are in saturation mode; hence, we write:

=
=
The inverter switching threshold is given by:
 Fig. 34 Typical VTC and the power supply current of a CMOS inverter circuit.

• CMOS inverter does not draw any significant current from the power source, except for small leakage and
subthreshold currents.
• The NMOS and the PMOS transistors conduct a nonzero current in Regions B, C, and D.
• This nonzero current being drawn from the power source reaches its peak value when V = Vth.
• In other words, the maximum current is drawn when both transistors are operating in saturation mode.
 Propagation Delay of CMOS Inverter
Combined Capacitance at the output node
will be called the load capacitance,

Fig. 35 CASCADED CMOS INVERTER

Fig. 36. First-stage CMOS inverter with lumped

output load capacitance
 Delay time definitions:

The propagation delay times, and determine the input-to-output signal delay during the
high-to-low and low-to-high transitions of the output, respectively.
• is the time delay between the -transition of the rising input voltage and the -transition of
the falling output voltage.
• is defined as the time delay between the -transition of the falling input voltage and the -
transition of the rising output voltage.
 becomes the time required for the output voltage to fall from to the level

 becomes the time required for the output voltage to rise from to the level.

 The propagation delay times and are given by:

= -
= -
 Design of Symmetric CMOS Inverters
 Given VDD, the NMOS and the PMOS threshold voltages, and the desired inverter threshold voltage , the
corresponding ratio can found as follows:

 Putting and the operations of the nMOS and the pMOS transistors of the CMOS inverter are fully complementary, we can
achieve completely symmetric input-output characteristics by setting the threshold
voltages as
 Hence, an ideal symmetric inverter requires:

Bad
NMOS
Good
Good PMOS
NMOS
Bad
PMOS

Fig. 37 VTC for different kr values

 The Theory of Logical efforts

PC: CMOS VLSI design a circuits and systems perspective (4th edition solution) by Neil H. E. Weste and David Harris
 Introduction to Logical Efforts
 Logical Effort is a technique in digital circuit design (especially CMOS) to:

1. Estimate delay,

2. compare different logic styles, and

3. optimize path delays

It helps designers size gates, choose gate types, and minimize propagation delay in critical paths.

 Logical effort of a gate is defined as the ratio of the input capacitance of the gate to the input capacitance of an
inverter that can deliver the same output current.

 Logical effort indicates how much worse a gate is at producing output current as compared to an inverter, given
that each input of the gate may only present as much input capacitance as the inverter.
Logical Effort model describes delays caused by:
o Capacitive load that the logic gate drives,
o Topology of the logic gate

 The delay in a gate is affected by how complex the gate is and by how much load it needs to drive (like fanout).

 More complex gates (e.g., NOR3) or heavier loads lead to higher delay.

 The absolute delay of a gate can be expressed as:

where d is the unitless delay of the gate and is the delay unit that is characterized by the process technology. For
example, a 0.6 µm process technology has 50ps of delay and a 0.18 µm process technology has 12ps


 Delay, logic gates can be expressed as:

where g is the Logical effort, p is the parasitic delay inherent to the gate when no load is attached, and h is the
Electrical effort.

So, d is the unitless delay and is then scaled by the technology-dependent delay unit.

 f is the effort delay or stage effort that depends on the complexity and fanout of the gate:

Logical effort, g: Logical Effort is a measure of how much more effort (input capacitance) a gate requires to deliver
the same output current as a simple inverter.

g=1 for a CMOS inverter.

More complex gates → higher g → slower than an inverter

 Electrical Effort ( ℎ ): Also called fanout, electrical effort measures how hard the gate has to drive its load.

: Total load capacitance (includes next gate(s), wires, etc.)

: Input capacitance of the gate

o Large fanout = larger ℎ = slower gate

o Reducing fanout helps reduce delay

 Parasitic Delay (p)=Parasitic delay is the delay due to the gate’s own internal capacitance, even when driving no external
load.

𝑝=delay due to internal diffusion, wiring, etc.

It depends only on gate topology (number of series transistors).It is independent of load.

 Logical Effort Calculation

g=1 (w.r.t itself inverter NAND3

drives the exactly same NOR3
g= 5/3 g= =7/3
amount of load as an
inverter) Cin=5 (Each input sees an input Cin=7
capacitance)
Cin=3

Larger inputs leads to larger logical effort

Logical effort is a way to compare the speed of different logic gates by estimating how much more effort a gate requires to
drive a load compared to an inverter.

NAND2 NOR3
g= =4/3 g= =5/3
Cin=4 Cin=5
Table: Typical Values of p, parasitic delay:
Gate Parasitic Delay More series transistors → higher parasitic delay
Inverter 1
NAND2 2 Calculation of logical effort:
NOR2 2 CMOS Inverter: PMOS: size = 2 NMOS: size = 1→ This ensures equal
rise and fall delay.
NAND3 3
Input capacitance, =2+1=3 (sum of gate capacitances)
NOR3 3 NAND2: Two NMOS in series → each must be size = 2 (to match
inverter pull-down strength)
Two PMOS in parallel → each PMOS = 2 (same as inverter PMOS)
Table: Typical Values of g, logical effort: Input capacitance per input: Each input sees one NMOS + one PMOS
= 2+2=4
Gate Parasitic Delay
So average input capacitance = 4
Inverter 1 Logical Effort of NAND2:
NAND2 4/3
NOR2 5/3
NAND3 5/3
NOR3 7/3
 Table: Parasitic Delay of common gates

The effort tends to increase with the number of inputs. NAND gates are better than NOR gates because the series
transistors are NMOS rather than PMOS.
PC: CMOS VLSI design a circuits and systems perspective (4th edition solution) by Neil H. E. Weste and David Harris
 EXAMPLE 1: Calculate the delay for FO4 inverter

 f=g*h=1*4=4

 d=f+ =4+1=5
 d(abs)=d.
 12ps for 180nm technology Fig. 38. One NOT gate driving 4 such NOT gates
 So, d(abs)=d.=60 ps
 EXAMPLE 2: Calculate the delay for 4-input NOR gate which drives 10, 4input NOR gates:
 f=g*h=9/3*10=30

 d=f+ =30+4=34
 d(abs)=d.
 12ps for 180nm technology
 So, d(abs)=d.=34*12 ps=408 ps

Fig. 39. One 4-input NOR gate driving 10 such NOR gates
 Interconnect Analysis
 The wires linking transistors together are called interconnect and play a major role in the performance of modern
electronic systems.

 In the early days of VLSI, transistors were relatively slow. Wires were wide and thick and thus had low resistance.

 In modern VLSI processes, transistors switch much faster.

 Wires have become narrower, driving up their resistance to the point, that in many signal paths, the wire RC delay
exceeds gate delay.

 Wires are packed very closely together and thus a large fraction of their capacitance is to their neighbors.

 Wires also account for a large portion of the switching energy of a chip.

 Considering all of these factors, circuit design is now as much about engineering the wires as the transistors that sit
underneath.

 Why Wires Were Thick in Early VLSI?

PC: CMOS VLSI design a circuits and systems perspective (4th edition solution) by Neil H. E. Weste and David Harris
 In the early days (e.g., 3–5 µm CMOS), the feature sizes were large, and the metal interconnects were correspondingly wider
and thicker.

 This was due to:

o Relaxed design rules

o Minimum wire width and spacing were large (e.g., 3–5 µm).

o Wires were physically fat, resulting in: Low resistance 𝑅= 𝜌

o Delay from wires was small compared to gate delay.

o Early VLSI chips had 1–2 metal layers.

o Less routing congestion → allowed generous wire sizing.

o No Serious Scaling Pressure for Power, area, and delay budgets were not as constrained as today.
 With CMOS scaling (down to 5nm, 3nm etc.), the situation has changed drastically:

 Shrinking Feature Size To increase transistor density, the entire layout — including metal lines — must shrink.

 Wire width and thickness are scaled down according to design rules (DRC from foundries like TSMC, Intel, etc.)

 More Interconnect Layers

 Modern chips may have 10–15 metal layers, with:

 Upper layers (M7–M15) wide/thick (for global wires and power)

 Lower layers (M1–M4) very narrow and resistive

 For local routing (between transistors), wires are extremely narrow, increasing resistance drastically.

 Billions of transistors = extremely dense routing.

 Can't afford wide wires everywhere → must use minimum-width wires to fit all signals.

 This causes RC delay of wires to dominate.

 Wire Geometry
 The wires have width w, length l, thickness t, and spacing of s from their neighbors and have a dielectric of height h
between them and the conducting layer below.

 The sum of width and spacing is called the wire pitch.

 The thickness to width ratio t/w is called the aspect ratio.

Fig. Interconnect geometry

Wire cross-sections in Intel’s (a) 90 nm and (b) 45 nm processes

PC: CMOS VLSI design a circuits and systems perspective (4th edition solution) by Neil H. E. Weste and David Harris
 Interconnect Modelling
Every wire, however short, physically behaves like a distributed network of:
Component Symbol Comes from
Resistance R The wire's material and geometry
Capacitance C Electric field coupling to substrate or other wires
Inductance L Magnetic fields generated by changing current

Resistance: The resistance relates to the wire’s cross-sectional area.

The resistance of a uniform slab of conducting material can be expressed as:

where, is the resistivity. The equation can be rewritten as:

where, is the sheet resistance and is equal to .

Fig. Interconnect geometry
Resistivity and thickness are characteristics of the process outside the control of the circuit designer
 Effects due to wire resistance:
o Voltage drop
o Signal attenuation (Signal strength (voltage amplitude) decreases over long wires with resistance)
o Power dissipation (P=
o Longer propagation delay ()

Capacitance: An isolated wire over the substrate can be modeled as a conductor over a ground plane.
o The wire capacitance has two major components: the parallel plate capacitance of the bottom of the wire to ground and the
fringing capacitance arising from fringing fields along the edge of a conductor with finite thickness.

o A wire adjacent to a second wire on the same layer can exhibit capacitance to that neighbor.

Fig. Interconnect geometry

o Effects due to wire capacitance:
o Increases signal delay:
o High dynamic power consumption: P=
o High wire capacitance slows down signal transitions.
o Wires add to the fanout load seen by a driving gate.

 Inductance: We generally discuss current flowing from a gate output to charge or discharge a load capacitance.
o If the current changes quickly (which happens in fast switching), it creates a changing magnetic field.
o This changing field resists the change—this is inductance.
o The result: a voltage spike or noise can appear due to this opposition.
o Can damage sensitive gates, or cause logic malfunction (false switching).

𝒅𝒊
𝑽=𝑳
𝒅𝒕
 (a)
Fig. An inverter driving three other
inverters over interconnection lines.

(b)

Fig. (a) An RLCG interconnection tree. (b) Typical signal waveforms at the nodes A
and B, showing the signal delay.
 Combinational Circuit Design
Combinational circuits are those whose output is
dependent only on the state of its inputs.

CMOS LOGIC CIRCUITS

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 CMOS Logic Circuits
 CMOS stages are inherently inverting, so AND and OR functions must be built from NAND and NOR gates.
 By De morgan’s Law:
and

CMOS NOR2 (Two-Input NOR) Gate

TRUTH TABLE
VA VB Vout

0 (MI is OFF, M3 is ON) 0 (M2 is OFF, M4 1

is ON)
0(MI is OFF, M3 is ON) 1(M2 is ON, M4 is 0
OFF)
1(MI is ON M3 is OFF) 0(M2 is OFF, M4 is 0
ON)
1 (MI is ON, M3 is ON) 1(M2 is ON, M3 is 0
OFF)

Fig. A CMOS NOR2 gate and its complementary operation

CMOS NAND2 (Two-Input NAND) Gate

TRUTH TABLE

VA VB Vout

0 (MI is OFF, M3 is ON) 0 (M2 is OFF, M4 1

is ON)
0(MI is OFF, M3 is ON) 1(M2 is ON, M4 is 1
OFF)
1(MI is ON M3 is OFF) 0(M2 is OFF, M4 is 1
ON)
1 (MI is ON, M3 is ON) 1(M2 is ON, M3 is 0
OFF)

Fig. A CMOS NAND 2 gate and its complementary

operation
 Fig. AND-OR-INVERT (AOI) gate and the corresponding
Fig. A CMOS XOR gate
pull-down net
Fig. OR-AND-INVERT (OAI) gate and the corresponding pull-down net
Static CMOS Characteristics
 Static CMOS uses complementary pairs of p-type and n-type MOSFETs to form pull-up and pull-down networks.

 Static CMOS circuits are the circuits whose outputs are always dependent on the present inputs.

 Low Power: Static CMOS circuits consume power only during state transition and not during steady state

 Number of transistors are 2n

 High Noise Margin

 A typical static logic gate generates its output corresponding to the applied input voltages after a certain time delay

 In Static CMOS, the output level (or state) is maintained as long as the power supply is provided to inputs.

 High Input Capacitance

 Higher Area
 The important/critical voltages are given below:

VOH: Maximum output voltage when the output level is logic “1”

VOL Minimum output voltage when the output level is logic "0"

VIL: Maximum input voltage which can be interpreted as logic "0"

VIH: Minimum input voltage which can be interpreted as logic "1”

 Pseudo NMOS
 Pseudo-NMOS logic is a logic family that uses a single PMOS device as a pull-up device for a multi-transistor N-
Logic block.

 It's called "pseudo-NMOS" because it's like NMOS

logic, but not the same.

 In PSEUDO NMOS: is always ON

because its Gate is connected to ground or Zero potential always.

 Depending on the input conditions: NMOS circuitry can

be on or off.

Fig. Pseudo NMOS circuit for

Pseudo NMOS Logic Advantages:
 No of transistor is lesser than CMOS Logic.
Pseudo NMOS Logic has a transistor count of n+1 as compared to 2n in the case of CMOS Logic. (n= number of
input variables in the logic)
 High Speed
 Low Area
 Less Capacitance

Pseudo NMOS Logic Disadvantages:

 High Static Power Dissipation

 Reduced logic levels: Pseudo-NMOS logic has lower noise immunity because of its reduced logic levels.

 Ratioed Logic: Transistor sizing is critical for the correct operation of pseudo-NMOS logic circuits.

 Reduced output voltage swing

 Low Noise Margin

 Dynamic Circuits
 Dynamic circuits uses a clocked pullup transistor rather than a PMOS that is always ON.

 Dynamic logic is a style of digital circuit design in MOS technology where logic operation relies on
temporarily stored charge (usually on a capacitance) rather than a continuous direct path to power or ground
like in static CMOS.

 Instead of using both pull-up and pull-down networks active all the time (like static CMOS), dynamic logic
precharges a node and then conditionally discharges it depending on the inputs.

 It’s called “dynamic” because the logic does not hold its output statically — the correct output exists only because
of the dynamic storage of charge on a capacitor and the timing of the clock.
 Dynamic Logic
 The operation of all dynamic logic gates depends on temporary storage of charge in parasitic node
capacitances, instead of relying on steady-state circuit behavior.

 Low Power

 Low Area, number of transistors: (n+2)

 Low input Capacitance

 No static power dissipation

 Dynamic logic works by charging and selectively discharging the load capacitance:

 PRECHARGE: Clock to charge the capacitance

 EVALUATE: Clock to discharge the capacitance depending on condition

DYNAMIC LOGIC
of logic inputs
 PRECHARGE: When CLK = 0, the output node Out is precharged to VDD by the PMOS transistor Mp. During
that time, the evaluate NMOS transistor Me is off, so that the pull-down path is disabled. The Me eliminates any
static power that would be consumed during the precharge period .

 EVALUATION: For CLK = 1, the precharge transistor Mp is off, and the evaluation transistor Me is turned on.
The output is conditionally discharged based on the input values
and the pull-down topology. If the inputs are such that the PDN
conducts, then a low resistance path exists between Out and GND and
the output is discharged to GND.
 LOGIC DESIGN USING DYNAMIC LOGIC
 1. Implement using Dynamic logic
STEPS:
1. First implement the Pull-Down network (PDN)
2. Then, we add the Mp and Mn to the PDN
3. Add the input clock and the output capacitance
Lets understand the working of this circuitry:
CLK=0: PRECHARGE PHASE
• Mp is ON and Mn is OFF
• f= charges to
• No direct path from to f so static power dissipation
CLK=1: EVALUATE PHASE
• Mn is ON and Mp is OFF: At this point,
INPUTS OUTPUT=f=
f will change depending on the A, B and C A B C CLK f
inputs
0 0 0 1 1=
0 0 1 1 0
0 1 0 1 1
0 1 1 1 0
1 0 0 1 1
1 0 1 1 0
1 1 0 1 0
 F=
CLK =0: PRECHARGE PHASE

• Mp IS ON and Mn is OFF

• charges to

• No direct path from to f so static power dissipation

=1: EVALUATE PHASE

• Mn is ON and Mp is OFF: At this point,

will change depending on the A, B and C

Dynamic CMOS logic gate implementing and working of the inputs
Boolean function: F=
If the input signals create a conducting path between

and the ground, the will discharge to 0 V.

Otherwise, Vout, remains at VDD.

 VDD VDD

1. DYNAMIC NAND= 2. DYNAMIC NOR= 3. DYNAMIC XOR=

VDD

4. DYNAMIC XNOR=
 ADVANTAGES OF DYNAMIC LOGIC
 The number of transistors required here are less (N+2) as compared to 2N in the Static CMOS
circuits.

 This circuit is ratio less circuit

 The static power loss is very less in a dynamic logic circuit.

 Faster switching speed because of lower load capacitance

 SUMMARY
 Static CMOS: Simple, robust, but slower for high fan-in gates.

 Pseudo NMOS: Faster and smaller than static, but wastes static power.

 Dynamic CMOS: Very fast and compact, but needs clocking, is sensitive to leakage/noise, and
consumes dynamic power every cycle.

 F= implement the Boolean expression using Static, Pseudo and Dynamic CMOS logic and
report the number of transistors required for each.
 Sequential Circuit Design
 Sequential circuits in which the output depends on previous as well as current inputs; such circuits are said to
have state.
 Sequential circuits are usually designed with flip-flops or latches, which are sometimes called memory elements,
that hold data.
 The purpose of these elements is not really memory; instead, it is to enforce sequence, to distinguish the current
data from the previous or next data.
 Therefore, we will call them sequencing elements
 In other words, a sequential circuit remembers the past history

Output=f(Current Inputs, Previous State)

Fig. Basic FSM Block
 Why do we need a clock in sequential circuits and not in combinational circuits?

o The clock provides a timing reference to sequential circuits.

o Synchronize when the state should be updated

o Ensure data is sampled only at specific times

o Prevent errors from asynchronous changes

o Clock: It tells the circuit "update now!

o "Without it, all the feedback loops (used to store state) might oscillate or produce glitches

o Combinational: Like a calculator — gives instant output based on what you type in.

o Sequential: Like a stopwatch — remembers previous time, needs you to hit a button (clock) to move
forward.
 Basic Memory Element: Latch
 Bistable Latch: It is called “bistable” because it has two stable states, which allows it to store one bit of
information — either 0 or 1.
 It uses feedback — the output of one gate feeds into another in a loop — to hold its state.

“A latch needs a clock

(or an enable signal) to
control when it is
allowed to capture and
store data.”
Fig. Bistable memory element Fig. Bistable memory element with NOR
gates

Fig. SR NOR latch with level triggered

clock

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
Fig. SR NOR latch with level triggered
clock
Fig. AOI-based implementation of the clocked NOR-based
SR latch circuit and its truth table

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 Because of the NOT ALLOWED state in SR Latch we have JK flip flop with all finite state outputs

J K Q
0 0 HOLD
0 1 0 1
1 0 1 0
1 1 TOGGLE

Fig. All-NAND implementation of the clocked JK latch circuit.

Fig. Truth Table of JK Flip Flop

While there is no not-allowed input combination for the JK latch, there is still a potential problem. If both inputs are equal
to logic " 1 " during the active phase of the clock pulse, the output of the circuit will oscillate (toggle) continuously until
either the clock becomes inactive (goes to zero), or one of the input signals goes to zero.

JK FF is used in practical application?

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 Limitation of JK Latch can be overcome in two ways:

1. To prevent this undesirable timing problem, the clock pulse width must be made smaller than the input-to-output propagation
delay of JK latch. However, clock constraints are difficult to be adjusted in modern day VLSI circuits.

2. Master Slave Latch or Edge Triggered JK Flipflop

Fig. Master-slave flip-flop consisting of NAND-based JK latches.

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 Fig. Master-slave flip-flop consisting of NAND-based JK
latches.

Fig. Sample input and output waveforms of the master-slave

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici flip-flop circuit.
 CMOS D Latch and Edge Triggered Flip-Flop

Fig. Gate-level schematic and the block diagram view of the D-latch.

The D-latch finds many applications in digital circuit design, primarily for temporary
storage of data or as a delay element.

PC: CMOS Digital Integrated Circuits by Sung-Mo Kang and Yusuf Leblebici
 Fig. CMOS implementation of the D-latch Fig. CMOS negative edge-triggered master-slave D flip-flop
(DFF).
• Initially CLK = 1: TG1 and TG4 are ON; TG2 and TG3 are OFF: Qm=D
For the D to travel through two NOT gates and reach Qm takes some time, this data, D at Qm should be available
some time before the first negative edge of clock to avoid any METASTABILITY
This extra time is called SETUP TIME in D Flip-Flop.

• First NEGEDGE of clock occurs so CLK: 1  0: Now: TG1 and TG4 are OFF; TG2 and TG3 are ON
The data, D moves from Qm to Qs now.
However, TG1 takes some to go to OFF and TG3 takes some to go to ON, within this time the previous Data, D at
D input should be stable otherwise if a new input enters Qm will be replaced by the new input and the previous
data, D won’t be available at output, Qs.
This time is called HOLD time in D Flipflop
 Fig. Simulated waveforms of the CMOS DFF circuit,
Fig. Simulated input and output waveforms of the CMOS showing a set-up time violation for the master stage input at
DFF circuit 10 ns.
 Delay Constraints
Setup Time ():
The minimum amount of time before the clock edge that the data input (D) must be held stable (not change), so that it is reliably
sampled by the flip-flop.

If data changes too close to the clock edge, the flip-flop might not latch the correct value, leading to a setup time violation.

Hold Time ():

The minimum amount of time the data input (D) must be held stable after the clock edge, to ensure the flip-flop correctly
captures the data.

If data changes immediately after the clock edge, the flip-flop may not capture it reliably, resulting in a hold time violation.

SETUP TIME IS WITH RESPECT TO NEXT CLOCK PULSE AND HOLD TIME IS WITH RESPECT TO
PRESENT CLOCK PULSE

Clock to Q Delay(): The time taken for the output Q of a flip-flop to respond after a clock edge triggers a state change.

Combinational Delay (): The total propagation delay through a combinational logic block — from input to output.
 Fig. Pipelined Datapath Circuit and timing parameters.

The maximum propagation delay of the register .

• The set-up () and hold time () for the registers.
• The contamination delay and maximum delay of the combinational logic.
 Setup SLACK: Difference between data required time – data arrival time
Data required time=
Data arrival time=
If the difference is positive we call it a POSITIVE Setup slack without any timing violations
 HOLD SLACK: Difference between data arrival time – data required time
Data arrival time=
Data arrival time=
If the difference is positive we call it a POSITIVE Hold slack without any timing violations
Datapath & Array Subsystems
 Chip functions generally can be divided into the following categories:
Datapath operators
Memory elements
Control structures
Special-purpose cells
○ I/O
○ Power distribution
○ Clock generation and distribution
○ Analog and RF
 Adders
 Half Adder:

Full Adder

Fig. (a) Half Adder and b) Full

Adder
Fig. STATIC CMOS IMPLEMENTATION OF FULL ADDER
USING 28 TRANSISTORS
 The full adder employs 32 transistors.
 A more compact design is based on the observation that S can be factored to reuse the Cout term as follows:

Fig. Full adder with 28 Transistors ONLY

 Ripple Carry Adder (RCA): An N-bit adder can be constructed by cascading N full
adders.
A: 1101 (13)
B: 1111 (15)
+ Cin: 0
11100 (28)
Cou
t Su
Fig. Ripple Carry Adder m
 Subtraction: An N-bit subtracter uses the two’s complement relationship:

Fig. a) Subtractor, b) Adder Cum Subtractor

One/Zero Detectors:
 The use of one/zero detectors in IC VLSI Design:
1. Checking if a register or memory word is all 1s or all 0s (e.g., in initialization, error checking).
2. Fast bitmask evaluation: e.g., skip processing if mask = 0
3. A one/zero detector circuit is used to check whether a given binary word contains at least one
logic ‘1’ (one detector) or at least one logic ‘0’ (zero detector).

Fig. One/Zero Detector

 Magnitude Comparators:
 A magnitude digital Comparator is a combinational circuit that compares two digital or binary numbers in order to
find out whether one binary number is equal, less than, or greater than the other binary number.

Fig. N-bit Comparator Block Diagram

A B A>B A=B A<B

0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
Fig. Circuit Diagram of 1-bit Comparator
Fig. Truth Table of 1-bit Comparator
PC: [Link]
 Counters: Truth Table for 4-bit Asynchronous
counter
Clk Q3 Q2 Q1 Q0
 Counter stores the number of times a particular event or process has - 0 0 0 0
occurred, often in relationship to a clock signal. 0 0 0 1


0 0 1 0
Counters are used in digital electronics for counting purpose, they can
0 0 1 1
count specific event happening in the circuit.
0 1 0 0
 Counters are also used as frequency dividers. 0 1 0 1
1 0 0 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Fig. Circuit Diagram of 4-bit Negative Edged Asynchronous

Counter

PC: [Link]
 Fig. Circuit Diagram of 4-bit Johnson Counter

Clk QA QB QC QD
Fig. Frequency Division Divide-by-2 Counter
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
MODULE 3: HDL
 Importance of HDLs (Hardware Description
Language)
 Designers can write their RTL description without choosing a specific fabrication technology.

 Logic synthesis tools can automatically convert the design to any fabrication technology.

 If a new technology emerges, designers do not need to redesign their circuit.

 They simply input the RTL description to the logic synthesis tool and create a new gate-level netlist, using the
new fabrication technology.

By describing designs in HDLs, functional verification of the design can be done early in the design cycle.

 Since designers work at the RTL level, they can optimize and modify the RTL description until it meets the
desired functionality.
 Popularity of Verilog HDL
 Verilog HDL is a general-purpose hardware description language that is easy to learn and easy to use. It is similar
in syntax to the C programming language.

 Verilog HDL allows different levels of abstraction to be mixed in the same model. Thus, a designer can define a
hardware model in terms of switches, gates, RTL, or behavioral code.
 Basic Concepts
 Module: Verilog provides the concept of a module.

 A module is the basic building block in Verilog. A

module can be an element or a collection of lower-level
design blocks.

 In Verilog, a module is declared by the keyword

module.

 A corresponding keyword endmodule must appear at

the end of the module definition.

 Each module must have a module-name, which is the

identifier for the module, and a module-terminal-list,
which describes the input and output terminals of the
module.

PC:Verilog HDL: A Guide to Digital Design and Synthesis, 2nd Edition by Samir Palnitkar
 Verilog is both a behavioral and a structural language.

Internals of each module can be defined at four levels of abstraction, depending on the needs of the design.

Behavioral or algorithmic level :This is the highest level of abstraction provided by Verilog HDL. A module can be
implemented in terms of the desired design algorithm without concern for the hardware implementation details. Designing at
this level is very similar to C programming.

Dataflow level : At this level the module is designed by specifying the data flow. The designer is aware of how data flows
between hardware registers and how the data is processed in the design.

Gate level : The module is implemented in terms of logic gates and interconnections between these gates. Design at this
level is similar to describing a design in terms of a gate-level logic diagram.
Instances module ripple_adder (X, Y, S, Co);
input [3:0] X, Y;// Two 4-bit inputs
 Instantiation allows the creation of hierarchy in Verilog description output [3:0] S;
output Co;
wire w1, w2, w3;
// instantiating 4 1-bit full adders in Verilog
fulladder u1(X[0], Y[0], 1'b0, S[0], w1);
fulladder u2(X[1], Y[1], w1, S[1], w2);
fulladder u3(X[2], Y[2], w2, S[2], w3);
fulladder u4(X[3], Y[3], w3, S[3], Co);
endmodule
4-bit Ripple Carry Adder module full_adder (a,b,cin,sum,carry);
input a, b, cin;
output sum, carry;
wire c,c1,s;

half_adder ha0 (a, b, s, c);

half_adder ha1(cin, s, sum, c1);
assign carry = c | c1 ;
endmodule
module half_adder (a,b,sum,carry);
input a, b,];
output sum, carry;
Full Adder using Half adder xor x1(sum, a, b);
And A1(carry, a, b);
endmodule
[Link]
 Data Types: Verilog Basics
 Net :The size of a net is explicitly specified in a net declaration. Nets have values continuously driven on them by the outputs
of devices that they are connected to. Nets are one-bit values by default unless they are declared explicitly as vectors.
 The default value of a net is z
wire [4:0] D; // A 5-bit wire net
wor A; // 1-bit wor net
When no size is explicitly specified in a net declaration, the default size is one bit.
Here are the different kinds of net data types that are supported for synthesis are:
wire wor wand tri supply0 supply1

module WireExample (BpW, Error, Wait, Valid,

Clear);
input Error, Wait, Valid, Clear;
output BpW;
wire BpW;
assign BpW = Error & Wait;
assign BpW = Valid| Clear;
endmodule
PC: "Verilog® HDL Synthesis: A Practical Primer" by J. Bhasker Synthesized Netlist of WireExample
module UsesGates (BpW, BpR, Error, Wait, Clear);
input Error, Wait, Clear;
output BpW, BpR;
wor BpW;
wand BpR;
assign BpW = Error & Wait;
assign BpW = Valid| Clear;
assign BpR = Error^ Valid;
assign BpR = ! Clear;
endmodule

A Verilog wand (wired-AND) net type means that if multiple

drivers are connected to a wand net, the resulting value of
the net is the bit-wise AND of all the driving values.

Synthesized Netlist of UsesGates

 Register (reg): The different kinds of register types that are supported for synthesis are:
reg integer
A reg declaration explicitly specifies the size, that is, the corresponding number of bits of the variable in hardware.
Registers represent data storage elements.
Registers retain value until another value is placed onto them.
In Verilog, the term register merely means a variable that can hold a value.
Unlike a net, a register does not need a driver.
Register data types are commonly declared by the keyword reg. The default value for a reg data type is X.
For example,
reg [1:25] Cpt; // 25-bit variable
reg Bxr; // 1-bit variable When no size is explicitly specified in a reg declaration, the default is one bit.
. reg reset; // declare a variable reset that can hold its value
initial
begin
reset = 1’b1; //initialize reset to 1 to reset the digital circuit
#100 reset = l1’b0; // after 100 time units reset is deasserted
end
 Integer, and real data types are supported in Verilog.
 Integer: An integer is a general-purpose register data type used for manipulating quantities.
 Integers are declared by the keyword integer.
 Although it is possible to use reg as a general-purpose variable, it is more convenient to declare an integer variable for
purposes such as counting.
 The default width for an integer is 32 bits.
 Registers declared as data type reg store values as unsigned quantities, whereas integers store values as signed quantities.

In Verilog, numbers are unsigned by default, but you can declare

them as signed so that arithmetic is handled using two’s complement
representation.

reg signed [7:0] a = -5;

reg signed [7:0] b = 3;
reg signed [7:0] result;

initial begin
result = a + b; // result = -2
end
 Real: Real number constants and real register data types are declared with the keyword real.
 They can be specified in decimal notation (e.g., 3.14) or in scientific notation (e.g., 3e6, which is 3 X ).
 Real numbers cannot have a range declaration, and their default value is 0.
 When a real value is assigned to an integer, the real number is rounded off to the nearest integer.

real delta; // Define a real variable called delta

initial
begin
delta = 4e10; // delta is assigned in scientific notation
delta = 2.13; // delta is assigned a value 2.13
end
Few more important concepts:
 Vectors: Nets or reg data types can be declared as vectors (multiple bit widths). If bit width is not specified, the default
is scalar (1-bit)
The left number in the squared brackets is always the MSB of the vector.
In the example shown, bit 0 is the most significant bit of vector virtual-addr.
For the vector declarations shown above, it is possible to address bits or parts of vectors.

EXAMPLE 1:
wire a; // scalar net variable, default
wire [7:0] bus; // 8-bit bus
wire [31:01 busA, busB, busC; // 3 buses of 32-bit width.
reg clock; // scalar register,
reg [0 : 40] virtual-addr; // vector register, virtual address 41 bits width

EXAMPLE 2:
busA[7] // bit # 7 of vector busA
bus[2:0] // Three least significant bits of vector bus, // using virtual-
addr[0:l] //TWO most significant bits of vector virtual-addr
 Arrays: Arrays are allowed in Verilog for reg, integer, and vector register data types. Arrays are not allowed for
real variables.
integer count[0:7]; / / array of 8 count variables
reg B[31:0]; //Array of 32 one-bit Boolean register variables
reg [4:0] port [0:7] ; //Array of 8port-ids; each port-id is 5 bits wide

Count [5]; // 5th element of array of count variables

port_id[3]=port_id[2] | port_id[1]

 Memories: One often needs to model register files, RAMs, and ROMs.
Memories are modeled in Verilog simply as an array of registers.
Each element of the array is known as a word. Each word can be one or more bits.

reg [7 : 0] membyte [0 : 1023]; // memory membyte with 1K 8-bit words (1 byte)

 Verilog Operators
 Logical Operators : Used mainly as condition in if-else statements.
 They return either 0 (FALSE) or 1 (TRUE)

Symbol Operation
&& Logical AND
! Logical NOT
|| Logical OR

 Symbol Operation
Bitwise Operators: Operands operates on Bits
& AND
~ NOT
| OR
^ XOR
~^ XNOR
~& NAND
module logical_example; module logical_ifelse;
reg a, b; reg a, b, c;
reg [3:0] x, y; initial begin
reg result1, result2, result3, result4; a = 1; b = 0; c = 1;
if (a && c)
initial begin $display("Condition (a && c) is TRUE");
a = 1'b0; else
b = 1'b1; $display("Condition (a && c) is FALSE");
result1 = !a; // logical NOT: !0 = 1 if (a || b)
result2 = a && b; // logical AND: 0 && 1 = $display("Condition (a || b) is TRUE");
0 else
result3 = a || b; // logical OR : 0 || 1 = 1 $display("Condition (a || b) is FALSE");
x = 4'b0000; // treated as FALSE if (!b)
y = 4'b1010; // treated as TRUE (non-zero) $display("Condition (!b) is TRUE");
result4 = (x || y); // since x=0, y≠0 => TRUE else
end $display("Condition (!b) is FALSE");
endmodule end
endmodule
module bitwise_example;
reg [3:0] a, b;
reg [3:0] and_result, or_result, xor_result, xnor_result,
not_result;

initial begin
a = 4'b1100; // 12 in decimal
b = 4'b1010; // 10 in decimal

and_result = a & b; // bitwise AND

or_result = a | b; // bitwise OR
xor_result = a ^ b; // bitwise XOR
xnor_result = a ~^ b; // bitwise XNOR
not_result = ~a; // bitwise NOT
 Arithmetic Operators: + (add) , - (subtractor) , * (multiply), / (division), % (modulus)

module adder(A,B,Y);
input [2:0] Arb, Bet;
output [2:0] Lot;
assign Y=A+B;
endmodule

Synthesized Netlist of adder

module arithmetic_example (a,b,sum,diff,mod,prod,quotient;
input [4:0] a, b; // 4-bit inputs
output [5:0] sum, diff;
output [4:0] mod;
output [7:0] prod; // product can be larger than 8 bits

assign sum = a + b; // Addition

assign diff = a - b; // Subtraction
assign prod = a * b; // Multiplication
assign mod = a % b; // Modulus

$display("a = %d, b = %d", a, b);

$display("a+b = %d", sum);
$display("a-b = %d", diff);
$display("a*b = %d", prod);
$display("a/b = %d", quotient);
$display("a%%b = %d", mod);
end
endmodule
 Relational Operators: The relational operators // unsigned relational ops
assign a_lt_b = (a < b);
supported for synthesis are: >, <, <=, >=
assign a_gt_b = (a > b);
 assign a_le_b = (a <= b);
If variables of a reg type or a net type are compared,
assign a_ge_b = (a >= b);
an unsigned relational operator is synthesized. (==, !=) — treats x/z as unknown (can propagate X)

 If integer variables are compared, then a signed assign a_eq_b = (a == b);

relational operator is synthesized. assign a_ne_b = (a != b);
// case equality (===, !==) — compares bit-for-bit
 = = = and ! = = are case equality / inequality they including X/Z

compare bit patterns including x and z. assign a_case_eq_b = (a === b);

assign a_case_ne_b = (a !== b);
 Use these when you need to distinguish x/z from 0/1.

 In synthesis, = = =/! = = are not synthesizable to

simple hardware in the same way; they are mainly for
testbenches and simulation checks.
 Equality operators: ==, ==!

 The operators === (case equality) and !== (case inequality) are not supported for synthesis.

 Equality operators are modeled similar to arithmetic operators in terms of whether signed or unsigned comparison is to
be made.

 Here is an example that uses signed numbers. Note that in this case, the operands of the equality operator are of integer
type because values of this type represent signed numbers.
 Shift operators: Right shift << and Left shift >> and Arithmetic right shift <<< and Arithmetic left shift >>>
 The vacated bits are filled with 0. << and <<< behave the same (just shift left and pad with 0).
 >> pads with 0s (logical shift). >>> pads with sign bit (arithmetic shift, keeps the sign of signed numbers).

module shift_operator (a, b, result);

input [7:0] a;
input signed [7:0] b;
output reg [7:0] result;
initial begin
a = 8'b00110110; // 54 in decimal
b = -8'd6; // signed -6 in decimal (11111010 in 2's complement)

// Logical left shift (adds zeros on the right)

result = a << 2; // 00110110 << 2 = 11011000

// Logical right shift (adds zeros on the left)

result = a >> 2; // 00110110 >> 2 = 00001101

// Arithmetic left shift (same as logical left shift)

result = b <<< 2; // -6 (11111010) <<< 2 = 11101000

// Arithmetic right shift (fills with sign bit instead of 0)

result = b >>> 2; // -6 (11111010) >>> 2 = 11111110 (-2)
end
endmodule
Part Select: In Verilog, part-select is used to pick a subset of bits from a vector Bit select:
module part_select_example (b0, b1, n0, n1, data);
output [15:0] data;
output [7:0] b0, b1; module bit_select_example (data, bit3, bit7);
input [3:0] n0, n1,n2; input [7:0] data;
output bit3, bit7;
initial begin
data = 16'b1101_1010_0110_1111; initial begin
data = 8'b10110110;
// Fixed part-select
b0 = data[7:0]; // lower 8 bits
b1 = data[15:8]; // upper 8 bits
bit3 = data[3];
n0 = data[3:0]; // lowest 4 bits bit7 = data[7];
n1 = data[11:8]; // bits [11:8] end
n2= {data[15], data [2:0]}; endmodule
end
endmodule

Output:
data = 1101101001101111
b0 = 01101111 (lower byte)
b1 = 11011010 (upper byte)
n0 = 1111 (lowest 4 bits)
n1 = 0110 (bits [11:8])
N2=1111
Conditional Expression: <condition>: <expression1>: <expression2>

If the condition is true then expression 1 is select otherwise expression 2

module conditional_example (a,b,max);

input [3:0] a, b;
output [3:0] max;

initial begin
a = 4'd7;
b = 4'd9;

// Conditional expression: if a > b then max = a else max = b

max = (a > b) ? a : b;
end
endmodule
Structural/ Gate Level Hardware Description