"Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based ..."

Alexandre M. Amory et al. (2005)

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DOI: 10.1109/DATE.2005.304

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno:
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. DATE 2005: 62-63

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