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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.6k 653

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.7k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.8k 272

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.3k 374

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 928 236

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 748 180

Repositories

Showing 10 of 112 repositories
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    SystemVerilog 41 771 0 0 Updated Feb 26, 2026
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 360 ISC 86 47 (4 issues need help) 22 Updated Feb 26, 2026
  • chips-alliance-website Public
    chipsalliance/chips-alliance-website’s past year of commit activity
    SCSS 4 MIT 7 8 8 Updated Feb 26, 2026
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 44 Apache-2.0 23 19 4 Updated Feb 26, 2026
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 141 Apache-2.0 89 216 (11 issues need help) 83 Updated Feb 26, 2026
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 130 Apache-2.0 79 105 (2 issues need help) 30 Updated Feb 26, 2026
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,590 Apache-2.0 653 350 (1 issue needs help) 143 Updated Feb 26, 2026
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 24 Apache-2.0 44 143 (6 issues need help) 25 Updated Feb 26, 2026
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge’s past year of commit activity
    SystemVerilog 44 Apache-2.0 11 20 7 Updated Feb 26, 2026
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 8 6 0 0 Updated Feb 26, 2026
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