Open-source NPU (Neural Processing Unit) for LLM inference - runs GPT-2, LLaMA, Mistral, Qwen2

Big Cedar Invitational Golf Tournament Site - March 2026

Config files for my GitHub profile.

A library for neural networks implemented with only MTNCL gates

Extract cells on critical path from netlist using STA report

Determine the profitability parameters for individuals or businesses to white-label Tesla Superchargers.

A simple web app with useful conversion tools for Computer Engineers

A foray into simple formal verification tasks in SystemVerilog

Ethan's CPU - A simple CPU based on the RISCV platform with the RV32I ISA

A sample project to leverage cursor features in structural MTNCL development

For an arbitrary boolean function, enumerate over all/some netlists and run comparisions

A RISCV CPU

Generates all possible Polymorphic MTNCL gates combinations.

This chrome extension looks for QR codes and makes them clickable by the user

This repo is used as a workspace for condensing dissertations into papers suitable for a confrence

Advent of Code 2024

An HDL Documentation tool for Verilog (and others coming soon)

A simple simulator to recreate the data in "basic strategy"

A simple logic synthesis tool based on Yosys

A portfolio website for my projects

Advent of Code 2023 - https://adventofcode.com/2023

This is the final project for the class CSCE 5013 - Wearable & Ubiquitous Computing. It is used for tracking and assisting a developer throughout their daily workflow