Latex source files of the open-source book FREE RANGE VHDL

A stochastic circuit optimizer for Cadence Virtuoso, using the NSGA-II genetic algorithm.

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Yosys Open SYnthesis Suite

Extension integrating digital logic simulator DigitalJS with Visual Studio Code

Digital logic design tool and simulator

List of awesome open source hardware tools, generators, and reusable designs

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…

List of awesome open source hardware projects

List of awesome semiconductor startups

This is a tutorial on standard digital design flow

CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.

4 stage, in-order, compute RISC-V core based on the CV32E40P

Build your hardware, easily!

Silicon Layout Wizard

Converts GDSII files to STL files.

A simple but powerful Python package for creating photolithography masks in the GDSII format.

Python script to convert image files to GDSII files

Learning FPGA, yosys, nextpnr, and RISC-V

PicoRV32 - A Size-Optimized RISC-V CPU

A Python toolbox for building complex digital hardware

Python EDA

D3.js based wave (signal) visualizer

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Modular hardware build system

Submission template for Tiny Tapeout 03

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here: