CSCE 3730: Reconfigurable Logic Instructor: Prof. Saraju P.
Mohanty
Page 1 of 9 Due Date: 1011/2021
Student Name: Hemnarayan Sah
Student UNT email ID: HemnarayanSah@[Link]
Requirements:
1. Using Behavioral Modeling design an ALU to perform the operations: Add,
Subtract, multiply, Divide, less than, greater than, Logical AND, Logical OR.
2. Using testbench test the designed ALU using at least two testcases for each operation.
Verify the results from the waveforms.
3. In1 operand should be connected to Switches SW0 (LSB) - SW3 (MSB) on Nexys 4
DDR board. In2 operand should be connected to Switches SW4 (LSB) –
SW7(MSB) on Nexys 4 DDR board. Type of operation should be selected based on
select lines SW8 (LSB) – SW10 (MSB) on Nexys 4 DDR board. The output of Adder
and subtractor are connected RESULT0 (LSB) – RESULT4 (MSB). Output of Multiplier
will be 8 bits and should be connected to RESULT0 (LSB) – RESULT7 (MSB).
Divider output should be connected to RESULT0 (LSB) – RESULT3 (MSB). The
output of less than and greater than should be connected to RESULT0 and RESULT1
Respectively. Logical AND and logical OR outputs should be connected to RESULT0
(LSB) – RESULT3 (MSB). Follow the Switch and RESULT assignments as given.
Learning Objectives:
The general learning objectives of this lab were to create ALU operation using VHDL and
program the FPGA device to implement that VHDL code on it and verify it against the given
inputs.
General Steps:
The general steps needed to complete this lab were as follows:
1. first, we created the behavioral model of ALU using VHDL in Xilinx Vivado.
2. Then we created the truth table for the ALU.
3. We then simulate the VHDL code to generate the waveform.
4. Then we run synthesis, implementation and bitstream.
5. Then we program the device and check the ALU function in Nexys 4 DDR device.
Detail Steps:
Some detailed steps to complete this lab were as follows
1. Step one, we drew the truth table of ALU.
Operation Opcode RESULT Output
Opcode2 Opcode1 Opcode0 Resu Resu Resu Resu Resu Resu Resu Resu
lt7 lt6 lt5 lt4 lt3 lt2 lt1 lt0
Addition 0 0 0 0 0 0 ‘0’ & A +B
Subtraction 0 0 1 0 0 0 ‘0’ & A -B
Multiply 0 1 0 A *B
Divide 0 1 1 0 0 0 0 A/B
CSCE 3730: Reconfigurable Logic Instructor: Prof. Saraju P. Mohanty
Page 2 of 9 Due Date: 1011/2021
Student Name: Hemnarayan Sah
Student UNT email ID: HemnarayanSah@[Link]
Less than 1 0 0 0 0 0 0 0 0 A<B
Greater than 1 0 1 0 0 0 0 0 0 A>B
And 1 1 0 0 0 0 0 A AND B
Or 1 1 1 0 0 0 0 A OR B
2. Step two, we created new RTL project in Xilinx Vivado software.
3. Step three, we created VHDL file, created code using behavioral Model. The is shown
below:
entity ALU is
Port ( clk : in STD_LOGIC;
In1 : in STD_LOGIC_VECTOR (3 downto 0);
In2 : in STD_LOGIC_VECTOR (3 downto 0);
opcode : in STD_LOGIC_VECTOR (2 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end entity;
architecture Behavioral of ALU is
begin
process(clk,in1,in2,opcode) begin
if (rising_edge(clk)) then
case (opcode) is
--Addition
when "000" =>
RESULT(4 downto 0) <= ('0' & In1) + In2;
RESULT(7 downto 5) <= (others=>'0');
--Subtraction
when "001" =>
RESULT(4 downto 0) <= ('0' & In1) - In2;
RESULT(7 downto 5)<= (others=>'0');
-- Multiplication
when "010" =>
RESULT <= (In1) * In2;
--Division
when "011" =>
RESULT(3 downto 0) <= std_logic_vector( to_unsigned(to_integer(unsigned(In1)) /
to_integer(unsigned(In2)),4));
RESULT(7 downto 4) <= (others=>'0');
--Less than
when "100" => if In1 < In2 then
Result<= "00000001";
CSCE 3730: Reconfigurable Logic Instructor: Prof. Saraju P. Mohanty
Page 3 of 9 Due Date: 1011/2021
Student Name: Hemnarayan Sah
Student UNT email ID: HemnarayanSah@[Link]
else
Result(7 downto 0) <= "00000000";
end if;
-- Greater than
When "101" => if In1 > In2 then
Result <= "00000010";
else
Result(7 downto 0) <= "00000000";
end if;
--And
when "110" =>
Result(3 downto 0) <= (In1) AND (In2);
Result(7 downto 4)<= "0000";
--Or
when "111" =>
Result(3 downto 0) <= (In1) OR (In2);
Result(7 downto 4)<= "0000";
when others =>
Result(7 downto 0)<= "00000000";
end case;
end if;
end process;
end Behavioral;
4. Step four, we wrote the test bench for alu as shown below
wait until falling_edge(clock);
--Addition
opcode<="000";In1<="0001"; In2<="0001";
wait until falling_edge(clock); -- wait for 1 clock cycle
opcode<="000";In1<="0011"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
--Subtraction
opcode<="001";In1<="0001"; In2<="0001";
wait until falling_edge(clock); -- wait for 1 clock cycle
opcode<="001";In1<="0101"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
--multiply
opcode<="010";In1<="0001"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
CSCE 3730: Reconfigurable Logic Instructor: Prof. Saraju P. Mohanty
Page 4 of 9 Due Date: 1011/2021
Student Name: Hemnarayan Sah
Student UNT email ID: HemnarayanSah@[Link]
opcode<="010";In1<="0001"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
--Divide
opcode<="011";In1<="0001"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
opcode<="011";In1<="0001"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
-- less than
opcode<="100";In1<="0001"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
opcode<="100";In1<="0001"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
--greater than
opcode<="101";In1<="0001"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
opcode<="101";In1<="0001"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
--and
opcode<="110";In1<="0001"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
opcode<="110";In1<="0001"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
--Or
opcode<="111";In1<="0001"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
opcode<="111";In1<="0001"; In2<="0010";
wait until falling_edge(clock); -- wait for 1 clock cycle
wait; -- end the simulation
end process;
end Behavioral;opcode<="111";In1<="0001"; In2<="0001";
clk<='0';
wait for 10 ms;
clk <='1';
wait for 10 ms;
opcode<="111";In1<="0011"; In2<="0010";
clk<='0';
wait for 10 ms;
5. Then we added constraint file to download above code into NEXYS 4 DDR chip and
made following changes.
CSCE 3730: Reconfigurable Logic Instructor: Prof. Saraju P. Mohanty
Page 5 of 9 Due Date: 1011/2021
Student Name: Hemnarayan Sah
Student UNT email ID: HemnarayanSah@[Link]
(Include selected code snippets/procedures that were written by you that are important, do not
include code from libraries or pre-defined functions)
Observations:
Some important observations while completing/testing this lab were the behavior of ALU. We
get to see the wave form for input and output of ALU operation.
CSCE 3730: Reconfigurable Logic Instructor: Prof. Saraju P. Mohanty
Page 6 of 9 Due Date: 1011/2021
Student Name: Hemnarayan Sah
Student UNT email ID: HemnarayanSah@[Link]
We get to generate the ALU on FPGA board and shown below:
1. Addition: OPCODE = “000”, In1 = 0001, In2 =0001, RESULT=”00000010”
2. Subtraction: OPCODE = “001”, In1 = 0001, In2 =0001, RESULT=”00000000”
CSCE 3730: Reconfigurable Logic Instructor: Prof. Saraju P. Mohanty
Page 7 of 9 Due Date: 1011/2021
Student Name: Hemnarayan Sah
Student UNT email ID: HemnarayanSah@[Link]
3. Multiplication: OPCODE = “010”, In1 = 0010, In2 =0011, RESULT=”00000110”
4. Division: OPCODE = “011”, In1 = 0010, In2 =0110, RESULT=”00000011”
CSCE 3730: Reconfigurable Logic Instructor: Prof. Saraju P. Mohanty
Page 8 of 9 Due Date: 1011/2021
Student Name: Hemnarayan Sah
Student UNT email ID: HemnarayanSah@[Link]
5. Less than: OPCODE = “100”, In1 = 0010, In2 =0100, RESULT=”00000000”
6. Greater than: OPCODE = “101”, In1 = 0010, In2 =0100, RESULT=”00000000”
7. And: OPCODE = “110”, In1 = 0011, In2 =0011, RESULT=”00000011”
CSCE 3730: Reconfigurable Logic Instructor: Prof. Saraju P. Mohanty
Page 9 of 9 Due Date: 1011/2021
Student Name: Hemnarayan Sah
Student UNT email ID: HemnarayanSah@[Link]
8. Or: OPCODE = “111”, In1 = 0000, In2 =0010, RESULT=”00000000”
Summary:
In this lab we learned to program ALU in FPGA device using VHDL and use of opcode in
selection process. And we get to learn the ALU process where we get input from switches and
output using RESULT.
Reference:
1. [Link]
types/
2. [Link]
%[Link]
