Fundamental Concepts

Pr ocessor •Fastest access is to the data held in

processor registers. Registers are at
Registers the top of the memory hierarchy.
Increasing Increasing Increasing •Relatively small amount of memory that
size speed cost per bit can be implemented on the processor
Primary L1
cache chip. This is processor cache.
•Two levels of cache. Level 1 (L1) cache
is on the processor chip. Level 2 (L2)
cache is in between main memory and
Secondary L2 processor.
cache
•Next level is main memory, implemented
as SIMMs. Much larger, but much slower
than cache memory.
Main •Next level is magnetic disks. Huge amount
memory of inexepensive storage.
•Speed of memory access is critical, the
idea is to bring instructions and data
Magnetic disk that will be used in the near future as
secondary close to the processor as possible.
memory
 Maximum size of the Main Memory
 byte-addressable
 CPU-Main Memory Connection
Processor Memory
k-bit
address bus
MAR
n-bit
data bus Up to 2 k addressable
MDR locations

Word length = n bits

Control lines
( R / W, MFC, etc.)
 Measures for the speed of a memory:
▪ memory access time.
▪ memory cycle time.
 An important design issue is to provide a
computer system with as large and fast a
memory as possible, within a given cost
target.
 Several techniques to increase the effective
size and speed of the memory:
▪ Cache memory (to increase the effective speed).
▪ Virtual memory (to increase the effective size).
Semiconductor RAM memories
 Each memory cell can hold one bit of information.
 Memory cells are organized in the form of an array.
 One row is one memory word.
 All cells of a row are connected to a common line, known as the
“word line”.
 Word line is connected to the address decoder.
 Sense/write circuits are connected to the data input/output lines
of the memory chip.
 7 7 1 1 0 0
W0

•
•
•
FF FF
A0 W1

•
•
•
A1
Address Memory
• • • • • • cells
decoder • • • • • •
A2
• • • • • •
A3

W15
•
•
•

Sense / Write Sense / Write Sense / Write R /W

circuit circuit circuit
CS

Data input /output lines: b 7 b1 b0

 Two transistor inverters are cross connected to implement a basic flip-flop.
 The cell is connected to one word line and two bits lines by transistors T1 and T2
 When word line is at ground level, the transistors are turned off and the latch
retains its state
 Read operation: In order to read state of SRAM cell, the word line is activated to
close switches T1 and T2. Sense/Write circuits at the bottom monitor the state of
b and b’ 
b b

T1 T 2
X Y

Word line
Bit lines
 Static RAMs (SRAMs):
▪ Consist of circuits that are capable of retaining their state as long as the power
is applied.
▪ Volatile memories, because their contents are lost when power is interrupted.
▪ Access times of static RAMs are in the range of few nanoseconds.
▪ However, the cost is usually high.

 Dynamic RAMs (DRAMs):

▪ Do not retain their state indefinitely.
▪ Contents must be periodically refreshed.
▪ Contents may be refreshed while accessing them for reading.
 In order to store information in the cell, the transistor T is turned “on‟ & the
appropriate voltage is applied to the bit line, which charges the capacitor.
 After the transistor is turned off, the capacitor begins to discharge which is
caused by the capacitor’s own leakage resistance.
 Hence the information stored in the cell can be retrieved correctly before the
threshold value of the capacitor drops down.
 During a read operation, the transistor is turned “on”& a sense amplifier
connected to the bit line detects whether the charge on the capacitor is above
the threshold value.
 If charge on capacitor > threshold value -> Bit line will have logic value “1‟.
 If charge on capacitor < threshold value -> Bit line will set to logic value “0‟.
 How many 128x8 RAM chips are needed to provide a memory capacity of 2048
bytes.
 How many lines of address bus must be used to access 2048 bytes of memory.
 How many of these lines will be common to all chips.
 How many lines must be decoded for the chip select ? specify the size of the
decoder.

 2048/128 =16 chips.

 2048 = (2 power 11) = 11 address lines are needed to address 2048 bytes.
 128 = (2 power 7) = 7 lines to address the chip.
4 lines to decoders for selecting the16 chips.
 4x16 decoder.
 Design 64K X 8 memory using 16K X 1 static
memory chip.
 21-bit
addresses 19-bit internal chip address Implement a memory unit of 2M
A0
A1 words of 32 bits each.
Use 512kx8 static memory chips.
A 19 Each column consists of 4 chips.
A 20
Each chip implements one byte
position.
A chip is selected by setting its
chip select control line to 1.
Selected chip places its data on the
2-bit
decoder data output line, outputs of other
chips are in high impedance state.
21 bits to address a 32-bit word.
High order 2 bits are needed to
512K  8
memory chip
D 31-24 D 23-16 D 15-8 D 7-0
select the row, by activating the
four Chip Select signals.
512K  8 memory chip
19 bits are used to access specific
byte locations inside the selected
19-bit 8-bit data
address input/output chip.

Chip select
Read-Only Memories (ROMs)
 SRAM and SDRAM chips are volatile:
▪ Lose the contents when the power is turned off.
 Many applications need memory devices to retain contents after
the power is turned off.
▪ For example, computer is turned on, the operating system must be
loaded from the disk into the memory.
▪ Store instructions which would load the OS from the disk.
▪ Need to store these instructions so that they will not be lost after the
power is turned off.
▪ We need to store the instructions into a non-volatile memory.
 Non-volatile memory is read in the same manner as volatile
memory.
▪ Separate writing process is needed to place information in this
memory.
▪ Normal operation involves only reading of data, this type
of memory is called Read-Only memory (ROM).
 Read-Only Memory:
▪ Data are written into a ROM when it is manufactured.
 Programmable Read-Only Memory (PROM):
▪ Allow the data to be loaded by a user.
▪ Process of inserting the data is irreversible.
▪ Storing information specific to a user in a ROM is expensive.

▪ Providing programming capability to a user may be better.

 Erasable Programmable Read-Only Memory

(EPROM):
▪ Stored data to be erased and new data to be loaded.
▪ Flexibility, useful during the development phase of digital systems.
▪ Erasable, reprogrammable ROM.
▪ Erasure requires exposing the ROM to UV light.
 Electrically Erasable Programmable Read-Only Memory
(EEPROM):
▪ To erase the contents of EPROMs, they have to be exposed to ultraviolet light.
▪ Physically removed from the circuit.
▪ EEPROMs the contents can be stored and erased electrically.
 Flash memory:
▪ Has similar approach to EEPROM.
▪ Read the contents of a single cell, but write the contents of an
entire block of cells.
▪ Flash devices have greater density.
▪ Higher capacity and low storage cost per bit.
▪ Power consumption of flash memory is very low, making it
attractive for use in equipment that is battery-driven.
▪ Single flash chips are not sufficiently large, so
larger memory modules are implemented using
flash cards and flash drives.
 A big challenge in the design of a computer system
is to provide a sufficiently large memory, with a
reasonable speed at an affordable cost.
 Static RAM:
▪ Very fast, but expensive, because a basic SRAM cell has a complex circuit making it
impossible to pack a large number of cells onto a single chip.
 Dynamic RAM:
▪ Simpler basic cell circuit, hence are much less expensive, but significantly slower than
SRAMs.
 Magnetic disks:
▪ Storage provided by DRAMs is higher than SRAMs, but is still less than what is
necessary.
▪ Secondary storage such as magnetic disks provide a large amount
of storage, but is much slower than DRAMs.
Cache Memories
 Processor is much faster than the main memory.
▪ As a result, the processor has to spend much of its time waiting while instructions
and data are being fetched from the main memory.
▪ Major obstacle towards achieving good performance.
 Speed of the main memory cannot be increased
beyond a certain point.
 Cache memory is an architectural arrangement
which makes the main memory appear faster to
the processor than it really is.
 Cache memory is based on the property of
computer programs known as “locality of
reference”.
 Analysis of programs indicates that many
instructions in localized areas of a program are
executed repeatedly during some period of time,
while the others are accessed relatively less
frequently.
▪ These instructions may be the ones in a loop, nested loop or few procedures
calling each other repeatedly.
▪ This is called “locality of reference”.
 Temporal locality of reference:
▪ Recently executed instruction is likely to be executed again very soon.
 Spatial locality of reference:
▪ Instructions with addresses close to a recently instruction are likely
to be executed soon.
 Main
Processor Cache memory

• Processor issues a Read request, a block of words is transferred from the

main memory to the cache, one word at a time.
• Subsequent references to the data in this block of words are found in the
cache.
• At any given time, only some blocks in the main memory are held in the
cache. Which blocks in the main memory are in the cache is determined by
a “mapping function”.
• When the cache is full, and a block of words needs to be transferred
from the main memory, some block of words in the cache must be
replaced. This is determined by a “replacement algorithm”.
• Existence of a cache is transparent to the processor. The processor
issues Read and Write requests in the same manner.
• If the data is in the cache it is called a Read or Write hit.
• Read hit:
▪ The data is obtained from the cache.

• Write hit:
▪ Cache has a replica of the contents of the main memory.
▪ Contents of the cache and the main memory may be updated
simultaneously. This is the write-through protocol.
▪ Update the contents of the cache, and mark it as updated by setting a
bit known as the dirty bit or modified bit. The contents of the main
memory are updated when this block is replaced.
▪ This is write-back or copy-back protocol.
• If the data is not present in the cache, then a Read miss or Write miss
occurs.
• Read miss:
▪ Block of words containing this requested word is transferred from the
memory.
▪ After the block is transferred, the desired word is forwarded to the processor.
▪ The desired word may also be forwarded to the processor as soon as it is
transferred without waiting for the entire block to be transferred. This is called
load-through or early-restart.

• Write-miss:
▪ Write-through protocol is used, then the contents of the main memory are
updated directly.
▪ If write-back protocol is used, the block containing the
addressed word is first brought into the cache. The desired word
is overwritten with new information.
• A bit called as “valid bit” is provided for each block.
• If the block contains valid data, then the bit is set to 1, else it is 0.
• Valid bits are set to 0, when the power is just turned on.
• When a block is loaded into the cache for the first time, the valid bit is set to 1.
• Data transfers between main memory and disk occur directly bypassing the cache.
• When the data on a disk changes, the main memory block is also updated.
• However, if the data is also resident in the cache, then the valid bit is set to 0.
• What happens if the data in the disk and main memory changes and the write-back
protocol is being used?
• In this case, the data in the cache may also have changed and is indicated by the
dirty bit.
• The copies of the data in the cache, and the main memory are different. This is
called the cache coherence problem.
• One option is to force a write-back before the main memory is updated from the
disk.
 Mapping functions determine how memory
blocks are placed in the cache.
 A simple processor example:
▪ Cache consisting of 128 blocks of 16 words each.
▪ Total size of cache is 2048 (2K) words.
▪ Main memory is addressable by a 16-bit address.
▪ Main memory has 64K words.
▪ Main memory has 4K blocks of 16 words each.
 Three mapping functions:
▪ Direct mapping
▪ Associative mapping
▪ Set-associative mapping.
 Main
memory Block 0 •Block j of the main memory maps to j modulo 128 of
Block 1
the cache. 0 maps to 0, 129 maps to 1.
Cache
tag
•More than one memory block is mapped onto the same
Block 0 position in the cache.
tag •May lead to contention for cache blocks even if the
Block 1
cache is not full.
Block 127
•Resolve the contention by allowing new block to
Block 128 replace the old block, leading to a trivial replacement
tag
Block 127 Block 129
algorithm.
•Memory address is divided into three fields:
- Low order 4 bits determine one of the 16
words in a block.
- When a new block is brought into the cache,
Block 255 the the next 7 bits determine which cache
Tag Block Word
5 7 4 Block 256 block this new block is placed in.
- High order 5 bits determine which of the possible
Main memory address Block 257
32 blocks is currently present in the cache. These
are tag bits.
•Simple to implement but not very flexible.
Block 4095
 Main Block 0
memory

Block 1
•Main memory block can be placed into any cache
Cache
tag
position.
Block 0 •Memory address is divided into two fields:
tag
Block 1 - Low order 4 bits identify the word within a block.
- High order 12 bits or tag bits identify a memory
Block 127
block when it is resident in the cache.
Block 128 •Flexible, and uses cache space efficiently.
tag
Block 127 Block 129
•Replacement algorithms can be used to replace an
existing block in the cache when the cache is full.
•Cost is higher than direct-mapped cache because of
the need to search all 128 patterns to determine
whether a given block is in the cache.
Block 255
Tag Word
12 4 Block 256

Main memory address Block 257

Block 4095
 Cache
Main Block 0 Blocks of cache are grouped into sets.
memory
tag Block 0 Mapping function allows a block of the main
Block 1
tag
memory to reside in any block of a specific set.
Block 1
Divide the cache into 64 sets, with two blocks per set.
tag Block 2 Memory block 0, 64, 128 etc. map to block 0, and they
tag Block 3 can occupy either of the two positions.
Block 63 Memory address is divided into three fields:
Block 64 - 6 bit field determines the set number.
tag - High order 6 bit fields are compared to the tag
Block 126 Block 65
fields of the two blocks in a set.
tag Set-associative mapping combination of direct and
Block 127
associative mapping.
Number of blocks per set is a design parameter.
Tag Set Word
Block 127 - One extreme is to have all the blocks in one set,
Block 128 requiring no set bits (fully associative mapping).
6 6 4
- Other extreme is to have one block per set, is
Block 129
Main memory address the same as direct mapping.

Block 4095
A two-way set-associative cache has lines of 16 bytes and a total size of 8
kbytes. The 64-Mbyte main memory is byte addressable. Show the format of
main memory addresses.
Sol:
There are a total of 8 kbytes/16 bytes = 512 lines in the cache.

Thus the cache consists of 256 sets of 2 lines each. Therefore 8 bits are needed
to identify the set number.
For the 64-Mbyte main memory, a 26-bit address is needed.

Main memory consists of 64-Mbyte/16 bytes = 222 blocks. Therefore, the set
plus tag lengths must be 22 bits, so the tag length is 14 bits and the word field
length is 4 bits.
Performance considerations
 A key design objective of a computer system is to achieve
the best possible performance at the lowest possible cost.
▪ Price/performance ratio is a common measure of success.
 Performance of a processor depends on:
▪ How fast machine instructions can be brought into the processor for
execution.
▪ How fast the instructions can be executed.
 Consider a system with 2 level caches. Access times of
Level 1 cache, Level 2 cache and main memory are 1 ns,
10ns, and 500 ns, respectively. The hit rates of Level 1
and Level 2 caches are 0.8 and 0.9, respectively. What is
the average access time of the system ignoring the
search time within the cache?
 Consider a system with 2 level caches. Access times of Level 1 cache, Level 2
cache and main memory are 1 ns, 10ns, and 500 ns, respectively. The hit rates
of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the
average access time of the system ignoring the search time within the cache?
 First, the system will look in cache 1. If it is not found in cache 1, then cache 2 and
then further in main memory (if not in cache 2 also).
 The average access time would take into consideration success in cache 1, failure
in cache 1 but success in cache 2, failure in both the caches and success in main
memory.
 Average access time = [H1*T1]+[(1-H1)*H2*T2]+[(1-H1)(1-H2)*Hm*Tm]
 where,
 H1 = Hit rate of level 1 cache = 0.8
T1 = Access time for level 1 cache = 1 ns
H2 = Hit rate of level 2 cache = 0.9
T2 = Access time for level 2 cache = 10 ns
Hm = Hit rate of Main Memory = 1
Tm = Access time for Main Memory = 500 ns
 So, Average Access Time = ( 0.8 * 1 ) + ( 0.2 *
0.9 * 10 ) + ( 0.2 * 0.1 * 1 * 500)
= 0.8 + 1.8 + 10
= 12.6 ns
Q. Consider the total level cache with access
time of 5 ns, and 80 ns respectively. If the hit
rate is 95% and 75 % respectively in the 2
caches, and memory access time is 250 ms,
what is the average access time?
 Want lowest page-fault rate.
 Evaluate algorithm by running it on a
particular string of memory references
(reference string) and computing the
number of page faults and page
replacements on that string.
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1

7 7 7 2 2
HI
0 0 0 0
T
1 1 1
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1

7 7 7 2 2 2 4 4 4 0 0 0 7 7 7
0 0 0 3 3 3 2 2 2 1 1 1 0 0
1 1 1 0 0 0 3 3 3 2 2 2 1
 Replaces the page that has not been
referenced for the longest time:
▪ By the principle of locality, this should be the
page least likely to be referenced in the near
future.
▪ performs nearly as well as the optimal policy.
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1

7 7 7 2 2 4 4 4 0 1
0 0 0 0 0 0 3 3 3
1 1 3 3 2 2 2 2
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1

7 7 7 2 2 4 4 4 0 1 1 1
0 0 0 0 0 0 3 3 3 0 0
1 1 3 3 2 2 2 2 2 7
 Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5

1 1 1 1 5
2 2 2 2 2
8 page faults
3 5 5 4 4
4 4 3 3 3
 A two-level memory system has ten different
virtual pages on a disk to be mapped into four-
page frames in the main memory. A certain
program generated the following page
trace:1,0,2,2,1,7,6,7,0,1,2,9,5,1,5,8,9,9,8,7,7,8,
2,9,7,3,2,4,4. Compare hit ratio for FIFO and
LRU.
Disk

Disk drive

Disk controller
 Sector 0, track 1
Sector 3, track n
Sector 0, track 0

Figure Organization of one surface of a disk.

 A disk system has 10 recording surfaces with
2048 track per surface,64 sector per track and
512 bytes of data per sector. The inner and
outer diameter of the cylinder 5 and 9 inch.
a. What is track density?
b. What is total capacity of disk?
c. What is data transfer rate, if rotational
speed is 2600 rpm?
d. What is maximum bit density?
surface=10
track/surface=2048
sector/track=64
bytes/sector=512
inner diameter=5 inch
outer diameter=9 inch
a)Track density=(Tracks/Surface)/((Radius of outer
cylinder- Radius of inner cylinder))
=2048/((4.5-2.5))
=1024 tracks/inch
b)Total capacity of
disk=bytes/sector*sector/track*track/surface*number
of surface
=512*64*2048*10
=671088640 bytes
=67.10 *10^7 bytes
c)Data transfer rate=(sector/track*byte/sector*
rotational speed)/60
=(64*512*2600)/60
=14.14 * 10^4 bytes/s
 d) Bit Density=Bit capacity of all tracks is
same but maximum bit density will occur
along the inner track.
Max bit density=(sector/track *
bit/sector)/(circumference of inner track)
=(64*512*8)/(Pi*5)
=16697.07 bit/inch
~~16698 bits/inch
 A disk system has 18 data recording with
1024 tracks/surface. There are 16
sector/track, each sector containing 1024
bytes. The inner and outer diameter of disk is
5 and 9 inch respectively.
1) What is total disk capacity?
2) What is track density?
3) What is maximum bit density?