UNIT IV

MEMORY SYSTEM

 Basic concepts

 Semiconductor RAM

 ROM

 Speed ,Size and cost

 Cache memories

 Improving cache performance

 Virtual memory

 Memory management requirements

 Associative memories

 Secondary storage devices

Performance consideration is here

BASIC CONCEPTS
The maximum size of the memory that can be used in any computer is determined
by the addressing scheme.

Address Memory Locations

16 Bit 216 = 64 K
32 Bit 232 = 4G (Giga)
40 Bit 240 = IT (Tera)

Fig: Connection of Memory to Processor:

If MAR is k bits long and MDR is n bits long, then the memory may contain upto
2K addressable locations and the n-bits of data are transferred between the
memory and processor.
This transfer takes place over the processor bus.
The processor bus has,

 Address Line
 Data Line
 Control Line (R/W, MFC – Memory Function Completed)

The control line is used for co-ordinating data transfer.

The processor reads the data from the memory by loading the address of the
required memory location into MAR and setting the R/W line to 1.
The memory responds by placing the data from the addressed location onto the
data lines and confirms this action by asserting MFC signal.
Upon receipt of MFC signal, the processor loads the data onto the data lines into
MDR register.
The processor writes the data into the memory location by loading the address of
this location into MAR and loading the data into MDR sets the R/W line to 0.

Memory Access Time → It is the time that elapses between the intiation of an
 Operation and the completion of that operation.
Memory Cycle Time → It is the minimum time delay that required between the
initiation of the two successive memory operations.

RAM (Random Access Memory):

In RAM, if any location that can be accessed for a Read/Write operation in fixed
amount of time, it is independent of the location‟s address.

Cache Memory:

It is a small, fast memory that is inserted between the larger slower main memory
and the processor.
It holds the currently active segments of a pgm and their data.

Virtual memory:

The address generated by the processor does not directly specify the physical
locations in the memory.
The address generated by the processor is referred to as a virtual / logical address.
The virtual address space is mapped onto the physical memory where data are
actually stored.
The mapping function is implemented by a special memory control circuit is often
called the memory management unit.
Only the active portion of the address space is mapped into locations in the
physical memory.
The remaining virtual addresses are mapped onto the bulk storage devices used,
which are usually magnetic disk.
As the active portion of the virtual address space changes during program
execution, the memory management unit changes the mapping function and
transfers the data between disk and memory.
Thus, during every memory cycle, an address processing mechanism determines
whether the addressed in function is in the physical memory unit.
If it is, then the proper word is accessed and execution proceeds.
If it is not, a page of words containing the desired word is transferred from disk to
memory.
This page displaces some page in the memory that is currently inactive.

SEMI CONDUCTOR RAM MEMORIES:

Semi-Conductor memories are available is a wide range of speeds.
Their cycle time ranges from 100ns to 10ns
INTERNAL ORGANIZATION OF MEMORY CHIPS:

Memory cells are usually organized in the form of array, in which each cell is
capable of storing one bit of in formation.
Each row of cells constitute a memory word and all cells of a row are connected
to a common line called as word line.
The cells in each column are connected to Sense / Write circuit by two bit lines.
The Sense / Write circuits are connected to data input or output lines of the chip.
During a write operation, the sense / write circuit receive input information and
store it in the cells of the selected word.

Fig: Organization of bit cells in a memory chip

The data input and data output of each senses / write ckt are connected to a single
bidirectional data line that can be connected to a data bus of the cptr.

R / W Specifies the required operation.

CS Chip Select input selects a given chip in the multi-chip memory system

Requirement of external
Bit Organization connection for address, data and
control lines
128 (16x8) 14
(1024) 128x8(1k) 19
Static Memories:

Memories that consists of circuits capable of retaining their state as long as power is
applied are known as static memory.

Fig:Static RAM cell

Two inverters are cross connected to form a batch

The batch is connected to two bit lines by transistors T1 and T2.
These transistors act as switches that can be opened / closed under the control of
the word line.
When the wordline is at ground level, the transistors are turned off and the latch
retain its state.

Read Operation:

In order to read the state of the SRAM cell, the word line is activated to close
switches T1 and T2.
If the cell is in state 1, the signal on bit line b is high and the signal on the bit line
b is [Link] b and b are complement of each other.
Sense / write circuit at the end of the bit line monitors the state of b and b‟ and set
the output accordingly.
Write Operation:

The state of the cell is set by placing the appropriate value on bit line b and its
complement on b and then activating the word line. This forces the cell into the
corresponding state.
The required signal on the bit lines are generated by Sense / Write circuit.
Fig:CMOS cell (Complementary Metal oxide Semi Conductor):
 Transistor pairs (T3, T5) and (T4, T6) form the inverters in the latch.
In state 1, the voltage at point X is high by having T5, T6 on and T4, T5 are OFF.
Thus T1, and T2 returned ON (Closed), bit line b and b will have high and low
signals respectively.
The CMOS requires 5V (in older version) or 3.3.V (in new version) of power
supply voltage.
The continuous power is needed for the cell to retain its state
Merit :

It has low power consumption because the current flows in the cell only when the
cell is being activated accessed.
Static RAM‟s can be accessed quickly. It access time is few nanoseconds.

Demerit:

SRAM‟s are said to be volatile memories because their contents are lost when the
power is interrupted.

Asynchronous DRAMS:-

Less expensive RAM‟s can be implemented if simplex calls are used such cells
cannot retain their state indefinitely. Hence they are called Dynamic RAM’s
(DRAM).
The information stored in a dynamic memory cell in the form of a charge on a
capacitor and this charge can be maintained only for tens of Milliseconds.
The contents must be periodically refreshed by restoring by restoring this
capacitor charge to its full value.

Fig:A single transistor dynamic Memory cell

In order to store information in the cell, the transistor T is turned „on‟ & the
appropriate voltage is applied to the bit line, which charges the capacitor.
After the transistor is turned off, the capacitor begins to discharge which is caused
by the capacitor‟s own leakage resistance.
Hence the information stored in the cell can be retrieved correctly before the
threshold value of the capacitor drops down.
 During a read operation, the transistor is turned „on‟ & a sense amplifier
connected to the bit line detects whether the charge on the capacitor is above the
threshold value.

If charge on capacitor > threshold value -> Bit line will have logic value „1‟.
If charge on capacitor < threshold value -> Bit line will set to logic value „0‟.

Fig:Internal organization of a 2M X 8 dynamic Memory chip.

DESCRIPTION:

The 4 bit cells in each row are divided into 512 groups of 8.
21 bit address is needed to access a byte in the memory(12 bitTo select a row,9
bitSpecify the group of 8 bits in the selected row).

A8-0 Row address of a byte.

A20-9 Column address of a byte.

During Read/ Write operation ,the row address is applied first. It is loaded into the
row address latch in response to a signal pulse on Row Address Strobe(RAS)
input of the chip.
When a Read operation is initiated, all cells on the selected row are read and
refreshed.
Shortly after the row address is loaded,the column address is applied to the
address pins & loaded into Column Address Strobe(CAS).
The information in this latch is decoded and the appropriate group of 8
Sense/Write circuits are selected.
R/W =1(read operation)The output values of the selected circuits are
transferred to the data lines D0 - D7.
R/W =0(write operation)The information on D0 - D7 are transferred to the
selected circuits.
 RAS and CAS are active low so that they cause the latching of address when they
change from high to low. This is because they are indicated by RAS & CAS.
To ensure that the contents of a DRAM „s are maintained, each row of cells must
be accessed periodically.
Refresh operation usually perform this function automatically.
A specialized memory controller circuit provides the necessary control signals
RAS & CAS, that govern the timing.
The processor must take into account the delay in the response of the memory.
Such memories are referred to as Asynchronous DRAM’s.

Fast Page Mode:

Transferring the bytes in sequential order is achieved by applying the consecutive

sequence of column address under the control of successive CAS signals.
This scheme allows transferring a block of data at a faster rate. The block of
transfer capability is called as Fast Page Mode.
Synchronous DRAM:

Here the operations e directly synchronized with clock signal.

The address and data connections are buffered by means of registers.
The output of each sense amplifier is connected to a latch.
A Read operation causes the contents of all cells in the selected row to be loaded
in these latches.
Fig:Synchronous DRAM
 Data held in the latches that correspond to the selected columns are transferred
into the data output register, thus becoming available on the data output pins.

Fig:Timing Diagram Burst Read of Length 4 in an SDRAM

First ,the row address is latched under control of RAS signal.

The memory typically takes 2 or 3 clock cycles to activate the selected row.
Then the column address is latched under the control of CAS signal.
After a delay of one clock cycle,the first set of data bits is placed on the data lines.
The SDRAM automatically increments the column address to access the next 3
sets of bits in the selected row, which are placed on the data lines in the next 3
clock cycles.

Latency & Bandwidth:

A good indication of performance is given by two [Link] are,

 Latency
 Bandwidth
Latency:

It refers to the amount of time it takes to transfer a word of data to or from the
memory.
For a transfer of single word,the latency provides the complete indication of
memory performance.
For a block transfer,the latency denote the time it takes to transfer the first word
of data.
Bandwidth:

It is defined as the number of bits or bytes that can be transferred in one second.
 Bandwidth mainly depends upon the speed of access to the stored data & on the
number of bits that can be accessed in parallel.

Double Data Rate SDRAM(DDR-SDRAM):

The standard SDRAM performs all actions on the rising edge of the clock signal.
The double data rate SDRAM transfer data on both the edges(loading edge,
trailing edge).
The Bandwidth of DDR-SDRAM is doubled for long burst transfer.
To make it possible to access the data at high rate , the cell array is organized into
two banks.
Each bank can be accessed separately.
Consecutive words of a given block are stored in different banks.
Such interleaving of words allows simultaneous access to two words that are
transferred on successive edge of the clock.

Larger Memories:

Dynamic Memory System:

The physical implementation is done in the form of Memory Modules.

If a large memory is built by placing DRAM chips directly on the main system
printed circuit board that contains the processor ,often referred to as
Motherboard;it will occupy large amount of space on the board.
These packaging consideration have led to the development of larger memory
units known as SIMM‟s & DIMM‟s .
SIMM-Single Inline memory Module
DIMM-Dual Inline memory Module

SIMM & DIMM consists of several memory chips on a separate small board that
plugs vertically into single socket on the motherboard.

MEMORY SYSTEM CONSIDERATION:

To reduce the number of pins, the dynamic memory chips use multiplexed
address inputs.
The address is divided into two [Link] are,

 High Order Address Bit(Select a row in cell array & it is provided first
and latched into memory chips under the control of RAS signal).
 Low Order Address Bit(Selects a column and they are provided on same
address pins and latched using CAS signals).

The Multiplexing of address bit is usually done by Memory Controller Circuit.

 Fig:Use of Memory Controller

The Controller accepts a complete address & R/W signal from the processor,
under the control of a Request signal which indicates that a memory access
operation is needed.
The Controller then forwards the row & column portions of the address to the
memory and generates RAS &CAS signals.
It also sends R/W &CS signals to the memory.
The CS signal is usually active low, hence it is shown as CS.

Refresh Overhead:

All dynamic memories have to be refreshed.

In DRAM ,the period for refreshing all rows is 16ms whereas 64ms in SDRAM.

Eg:Given a cell array of 8K(8192).

Clock cycle=4
Clock Rate=133MHZ
No of cycles to refresh all rows =8192*4
=32,768
Time needed to refresh all rows=32768/133*106
=246*10-6 sec
=0.246sec
Refresh Overhead =0.246/64
Refresh Overhead =0.0038

Rambus Memory:

The usage of wide bus is expensive.

Rambus developed the implementation of narrow bus.
Rambus technology is a fast signaling method used to transfer information
between chips.
 Instead of using signals that have voltage levels of either 0 or Vsupply to represent
the logical values, the signals consists of much smaller voltage swings around a
reference voltage Vref.
.The reference Voltage is about 2V and the two logical values are represented by
0.3V swings above and below Vref..
This type of signaling is generally is known as Differential Signalling.
Rambus provides a complete specification for the design of communication
links(Special Interface circuits) called as Rambus Channel.
Rambus memory has a clock frequency of 400MHZ.
The data are transmitted on both the edges of the clock so that the effective data
transfer rate is 800MHZ.
The circuitry needed to interface to the Rambus channel is included on the
[Link] chips are known as Rambus DRAM‟s(RDRAM).
Rambus channel has,

 9 Data lines(1-8Transfer the data,9th lineParity checking).

 Control line
 Power line

A two channel rambus has 18 data lines which has no separate address [Link] is
also called as Direct RDRAM’s.
Communication between processor or some other device that can serves as a
master and RDRAM modules are serves as slaves ,is carried out by means of
packets transmitted on the data lines.
There are 3 types of [Link] are,

 Request
 Acknowledge
 Data

READ ONLY MEMORY:

Both SRAM and DRAM chips are volatile,which means that they lose the stored
information if power is turned off.
Many application requires Non-volatile memory (which retain the stored
information if power is turned off).
Eg:Operating System software has to be loaded from disk to memory which
requires the program that boots the Operating System ie. It requires non-volatile
memory.
Non-volatile memory is used in embedded system.
Since the normal operation involves only reading of stored data ,a memory of this
type is called ROM.
Fig:ROM cell

At Logic value ‘0’  Transistor(T) is connected to the ground point(P).

Transistor switch is closed & voltage on bitline nearly drops to zero.
At Logic value ‘1’  Transistor switch is open.
The bitline remains at high voltage.

To read the state of the cell,the word line is activated.

A Sense circuit at the end of the bitline generates the proper output value.

Types of ROM:

Different types of non-volatile memory are,

 PROM
 EPROM
 EEPROM
 Flash Memory

PROM:-Programmable ROM:

PROM allows the data to be loaded by the user.

Programmability is achieved by inserting a „fuse‟ at point P in a ROM cell.
Before it is programmed, the memory contains all 0‟s
The user can insert 1‟s at the required location by burning out the fuse at these
locations using high-current pulse.
This process is irreversible.

Merit:
It provides flexibility.
It is faster.
It is less expensive because they can be programmed directly by the user.

EPROM:-Erasable reprogrammable ROM:

EPROM allows the stored data to be erased and new data to be loaded.
 In an EPROM cell, a connection to ground is always made at „P‟ and a special
transistor is used, which has the ability to function either as a normal transistor or
as a disabled transistor that is always turned „off‟.
This transistor can be programmed to behave as a permanently open switch, by
injecting charge into it that becomes trapped inside.
Erasure requires dissipating the charges trapped in the transistor of memory cells.
This can be done by exposing the chip to ultra-violet light, so that EPROM chips
are mounted in packages that have transparent windows.
Merits:
It provides flexibility during the development phase of digital system.
It is capable of retaining the stored information for a long time.

Demerits:
The chip must be physically removed from the circuit for reprogramming and its
entire contents are erased by UV light.

EEPROM:-Electrically Erasable ROM:

Merits:
It can be both programmed and erased electrically.
It allows the erasing of all cell contents selectively.
Demerits:
It requires different voltage for erasing ,writing and reading the stored data.

Flash Memory:

In EEPROM, it is possible to read & write the contents of a single cell.

In Flash device, it is possible to read the contents of a single cell but it is only
possible to write the entire contents of a block.
Prior to writing,the previous contents of the block are erased.
[Link] MP3 player,the flash memory stores the data that represents sound.
Single flash chips cannot provide sufficient storage capacity for embedded system
application.
There are 2 methods for implementing larger memory modules consisting of
number of [Link] are,
 Flash Cards
 Flash Drives.
Merits:
Flash drives have greater density which leads to higher capacity & low cost per
bit.
It requires single power supply voltage & consumes less power in their operation.

Flash Cards:
One way of constructing larger module is to mount flash chips on a small card.
Such flash card have standard interface.
 The card is simply plugged into a conveniently accessible slot.
Its memory size are of 8,32,64MB.
Eg:A minute of music can be stored in 1MB of memory. Hence 64MB flash cards
can store an hour of music.

Flash Drives:

Larger flash memory module can be developed by replacing the hard disk drive.
The flash drives are designed to fully emulate the hard disk.
The flash drives are solid state electronic devices that have no movable parts.
Merits:
They have shorter seek and access time which results in faster response.
They have low power consumption which makes them attractive for battery
driven application.
They are insensitive to vibration.
Demerit:
The capacity of flash drive (<1GB) is less than hard disk(>1GB).
It leads to higher cost perbit.
Flash memory will deteriorate after it has been written a number of
times(typically atleast 1 million times.)

SPEED,SIZE COST:
Characteristics SRAM DRAM Magnetis Disk
Speed Very Fast Slower Much slower than
DRAM
Size Large Small Small
Cost Expensive Less Expensive Low price

Magnetic Disk:
A huge amount of cost effective storage can be provided by magnetic disk;The
main memory can be built with DRAM which leaves SRAM‟s to be used in
smaller units where speed is of essence.

Memory Speed Size Cost

Registers Very high Lower Very Lower
Primary cache High Lower Low
Secondary cache Low Low Low
Main memory Lower than High High
Seconadry cache
Secondary Very low Very High Very High
Memory
Fig:Memory Hierarchy

Types of Cache Memory:

The Cache memory is of 2 [Link] are,

 Primary /Processor Cache(Level1 or L1 cache)
 Secondary Cache(Level2 or L2 cache)

Primary Cache  It is always located on the processor chip.

Secondary CacheIt is placed between the primary cache and the rest of the memory.

The main memory is implemented using the dynamic

components(SIMM,RIMM,DIMM).
The access time for main memory is about 10 times longer than the access time
for L1 cache.

CACHE MEMORIES
The effectiveness of cache mechanism is based on the property of „Locality of
reference’.
Locality of Reference:
Many instructions in the localized areas of the program are executed repeatedly
during some time period and remainder of the program is accessed relatively
infrequently.
It manifests itself in 2 [Link] are,
 Temporal(The recently executed instruction are likely to be executed again
very soon.)
 Spatial(The instructions in close proximity to recently executed instruction
are also likely to be executed soon.)
If the active segment of the program is placed in cache memory, then the total
execution time can be reduced significantly.