Chapter Six

Digital Electronics
6.1 Number Systems
The study of number systems is important from the view point of understanding how data are
represented before they can be processed by any digital system including a digital computer. It is
one of the most basic topics in digital electronics. In this chapter we will discuss different
number systems commonly used to represent data. We will begin the discussion with the decimal
number system. Although it is not important from the view point of digital electronics, a brief
outline of this will be given to explain some of the underlying concepts used in other number
systems. This will then be followed by the more commonly used number systems such as the
binary, octal and hexadecimal number systems.

There are three characteristics that define a number system. These are the number of independent
digits used in the number system, the place values of the different digits constituting the number
and the maximum numbers that can be written with the given number of digits. Among the three
characteristic parameters, the most fundamental is the number of independent digits or symbols
used in the number system. It is known as the radix or base of the number system. The decimal
number system with which we are all so familiar can be said to have a radix of 10 as it has 10
independent digits, i.e. 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9. Similarly, the binary number system with
only two independent digits, 0 and 1, is a radix-2 number system. The octal and hexadecimal
number systems have a radix (or base) of 8 and 16 respectively.

The place values of different digits in the integer part of the number are given by ,
and so on, starting with the digit adjacent to the radix point. For the fractional part, these are
and so on, again starting with the digit next to the radix point. Here, r is the radix of
the number system. Also, maximum numbers that can be written with n digits in a given number
system are equal to .

Example 1.1 Consider an arbitrary number system with the independent digits as 0, 1 and X.
What is the radix of this number system? List the first 10 numbers in this number system.

Solution

• The radix of the proposed number system is 3.

• The first 10 numbers in this number system would be 0, 1, X, 10, 11, 1X, X0, X1, XX and 100.

6.1.1 Decimal Number System

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The decimal number system is a radix-10 number system and therefore has 10 different digits or
symbols. These are 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9. All higher numbers after ‘9’ are represented in
terms of these 10 digits only. The process of writing higher-order numbers after ‘9’ consists in
writing the second digit (i.e. ‘1’) first, followed by the other digits, one by one, to obtain the next
10 numbers from ‘10’ to ‘19’. The next 10 numbers from ‘20’ to ‘29’ are obtained by writing the
third digit (i.e. ‘2’) first, followed by digits ‘0’ to ‘9’, one by one. The process continues until we
have exhausted all possible two-digit combinations and reached ‘99’. Then we begin with three-
digit combinations. The first three-digit number consists of the lowest two-digit number followed
by ‘0’ (i.e. 100), and the process goes on endlessly.

The place values of different digits in a mixed decimal number, starting from the decimal point,
are and so on (for the integer part) and and so on (for the
fractional part). The value or magnitude of a given decimal number can be expressed as the sum
of the various digits multiplied by their place values or weights.

As an illustration, in the case of the decimal number 3586.265, the integer part (i.e. 3586) can be
expressed as

and the fractional part can be expressed as

We have seen that the place values are a function of the radix of the concerned number system
and the position of the digits. We will also discover in subsequent sections that the concept of
each digit having a place value depending upon the position of the digit and the radix of the
number system is equally valid for the other more relevant number systems.

6.1.2 Binary Number System

The binary number system is a radix-2 number system with ‘0’ and ‘1’ as the two independent
digits. All larger binary numbers are represented in terms of ‘0’ and ‘1’. The procedure for
writing higherorder binary numbers after ‘1’ is similar to the one explained in the case of the
decimal number system. For example, the first 16 numbers in the binary number system would
be 0, 1, 10, 11, 100, 101, 110, 111, 1000, 1001, 1010, 1011, 1100, 1101, 1110 and 1111. The
next number after 1111 is 10000, which is the lowest binary number with five digits. This also
proves the point made earlier that a maximum of only 16 numbers could be written with
four digits. Starting from the binary point, the place values of different digits in a mixed binary
number are and so on (for the integer part) and and so on (for the
fractional part).

6.1.3 Octal Number System

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The octal number system has a radix of 8 and therefore has eight distinct digits. All higher-order
numbers are expressed as a combination of these on the same pattern as the one followed in the
case of the binary and decimal number systems described in Sections 1.3 and 1.4. The
independent digits are 0, 1, 2, 3, 4, 5, 6 and 7. The next 10 numbers that follow ‘7’, for example,
would be 10, 11, 12, 13, 14, 15, 16, 17, 20 and 21. In fact, if we omit all the numbers containing
the digits 8 or 9, or both, from the decimal number system, we end up with an octal number
system. The place values of different digits in a mixed octal number are and so on (for
the integer part) and and so on (for the fractional part).

6.1.4 Hexadecimal Number System

The hexadecimal number system is a radix-16 number system and its 16 basic digits are 0, 1, 2,
3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and F. The decimal equivalent of A, B, C, D, E and F are 10, 11,
12, 13, 14 and 15 respectively. The place values or weights of different digits in a mixed
hexadecimal number are and so on (for the integer part) and and
so on (for the fractional part).

6.2 Number System Conversion

6.2.1 Finding the Decimal Equivalent

The decimal equivalent of a given number in another number system is given by the sum of all
the digits multiplied by their respective place values. The integer and fractional parts of the given
number should be treated separately. Binary-to-decimal, octal-to-decimal and hexadecimal-to-
decimal conversions are illustrated below with the help of examples.

A, Binary-to-Decimal Conversion:
The decimal equivalent of the binary number is determined as follows:

The decimal equivalent of

B, Octal-to-Decimal Conversion
The decimal equivalent of the octal number is determined as follows:

C, Hexadecimal-to-Decimal Conversion
The decimal equivalent of the hexadecimal number is determined as follows:

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6.2.2 Decimal-to- Another Number System
To convert a given mixed decimal number into an equivalent in another number system, the
integer part is progressively divided by r and the remainders noted until the result of division
yields a zero quotient. The remainders written in reverse order constitute the equivalent. r is the
radix of the transformed number system. The fractional part is progressively multiplied by r and
the carry recorded until the result of multiplication yields a zero or when the desired number of
bits has been obtained. The carrys written in forward order constitute the equivalent of the
fractional part.

A, Decimal-to-Binary Conversion

As outlined earlier, the integer and fractional parts are worked on separately. For the integer part,
the binary equivalent can be found by successively dividing the integer part of the number by 2
and recording the remainders until the quotient becomes ‘0’. The remainders written in reverse
order constitute the binary equivalent. For the fractional part, it is found by successively
multiplying the fractional part of the decimal number by 2 and recording the carry until the result
of multiplication is ‘0’. The carry sequence written in forward order constitutes the binary
equivalent of the fractional part of the decimal number. If the result of multiplication does not
seem to be heading towards zero in the case of the fractional part, the process may be continued
only until the requisite number of equivalent bits has been obtained. This method of decimal–
binary conversion is popularly known as the double-dabble method. The process can be best
illustrated with the help of an example.

Example: Find the binary equivalent of

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B, Decimal-to-Octal Conversion:

The process of decimal-to-octal conversion is similar to that of decimal-to-binary conversion.

The progressive division in the case of the integer part and the progressive multiplication while
working on the fractional part here are by ‘8’ which is the radix of the octal number system.
Again, the integer and fractional parts of the decimal number are treated separately. The process
can be best illustrated with the help of an example.

Example: find the octal equivalent of

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C, Decimal-to-Hexadecimal Conversion:

The process of decimal-to-hexadecimal conversion is also similar. Since the hexadecimal

number system has a base of 16, the progressive division and multiplication factor in this case is
16. The process is illustrated further with the help of an example.

Example: Find the hexadecimal equivalent of

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6.2.3 Binary–Octal and Octal–Binary Conversion
An octal number can be converted into its binary equivalent by replacing each octal digit with its
three-bit binary equivalent. A binary number can be converted into an equivalent octal number
by splitting the integer and fractional parts into groups of three bits, starting from the binary
point on both sides. The 0s can be added to complete the outside groups if needed.

Example:

6.2.4 Hex–Binary and Binary–Hex Conversions:

A hexadecimal number can be converted into its binary equivalent by replacing each hex digit
with its four-bit binary equivalent. A given binary number can be converted into an equivalent

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hexadecimal number by splitting the integer and fractional parts into groups of four bits, starting
from the binary point on both sides. The 0s can be added to complete the outside groups if
needed.

Example:

6.2.5 Hex–Octal and Octal–Hex Conversions

For hexadecimal–octal conversion, the given hex number is firstly converted into its binary
equivalent which is further converted into its octal equivalent. An alternative approach is firstly
to convert the given hexadecimal number into its decimal equivalent and then convert the
decimal number into an equivalent octal number. The former method is definitely more
convenient and straightforward. For octal–hexadecimal conversion, the octal number may first
be converted into an equivalent binary number and then the binary number transformed into its
hex equivalent. The other option is firstly to convert the given octal number into its decimal
equivalent and then convert the decimal number into its hex equivalent. The former approach is
definitely the preferred one. Two types of conversion are illustrated in the following example.

Example:

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Activity:
Assume an arbitrary number system having a radix of 5 and 0, 1, 2, L and M as its independent
digits. Determine:

(a) The decimal equivalent of (12LM.L1);

(b) The total number of possible four-digit combinations in this arbitrary number system.

6.3 Boolean Algebra and Logic Gates

The logic gate is the most basic building block of any digital system, including computers. Each
one of the basic logic gates is a piece of hardware or an electronic circuit that can be used to
implement some basic logic expression. While laws of Boolean algebra could be used to do
manipulation with binary variables and simplify logic expressions, these are actually
implemented in a digital system with the help of electronic circuits called logic gates. Logic

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gates are electronic circuits that can be used to implement the most elementary logic expressions,
also known as Boolean expressions. The logic gate is the most basic building block of
combinational logic. There are three basic logic gates, namely the OR gate, the AND gate and
the NOT gate. Other logic gates that are derived from these basic gates are the NAND gate, the
NOR gate, the EXCLUSIVEOR gate and the EXCLUSIVE-NOR gate.

 Truth Table:

A truth table lists all possible combinations of input binary variables and the corresponding
outputs of a logic system. The logic system output can be found from the logic expression, often
referred to as the Boolean expression that relates the output with the inputs of that very logic
system. if a logic circuit has n binary inputs, its truth table will have possible input
combinations, or in other words rows. When the number of input binary variables is only
one, then there are only two possible inputs, i.e. ‘0’ and ‘1’. For example: If the number of inputs
is two, there can be four possible input combinations, i.e. 00, 01, 10 and 11. Similarly, for three
input binary variables, the number of possible input combinations becomes eight, i.e. 000, 001,
010, 011, 100, 101, 110 and 111.

6.3.1 OR Gate
An OR gate performs an ORing operation on two or more than two logic variables. The OR
operation on two independent logic variables A and B is written as Y =A+B and reads as Y
equals A OR B and not as A plus B. An OR gate is a logic circuit with two or more inputs and
one output. The output of an OR gate is LOW only when all of its inputs are LOW. For all other
possible input combinations, the output is HIGH. This statement when interpreted for a positive
logic system means the following. The output of an OR gate is a logic ‘0’ only when all of its
inputs are at logic ‘0’. For all other possible input combinations, the output is a logic ‘1’. Figure
6.1 shows the circuit symbol and the truth table of a two-input OR gate. The operation of a two-
input OR gate is explained by the logic expression:

Y =A+B

Figure 6.1: The circuit symbol and the truth table of a two-input OR gate.

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Figure 6.2 shows the circuit symbol and the truth table of a three-input OR gate. The operation of
a three -input OR gate is explained by the logic expression:

Y=A+B+C

Figure 6.2: The circuit symbol and the truth table of a three-input OR gate.

How would you hardware-implement a four-input OR gate using two-input OR gates only?

Solution Figure 6.3 a and b shows possible arrangement of two-input OR gates that simulates
a four-input OR gate. A, B, C and D are logic inputs and Y3 is the output. Y3=A+B+C+D.

Figure 6.3: hardware-implement a four-input OR gate using two-input OR gates.

The output waveform for the two input OR gate and the given pulsed input waveforms of
Fig. 6.4. is

Fig. 6.4: The output waveform for the two input OR gate.

6.3.2 AND Gate

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 An AND gate is a logic circuit having two or more inputs and one output. The output of an
AND gate is HIGH only when all of its inputs are in the HIGH state. In all other cases, the
output is LOW. When interpreted for a positive logic system, this means that the output of
the AND gate is a logic ‘1’ only when all of its inputs are in logic ‘1’ state. In all other cases,
the output is logic ‘0’. The logic symbol and truth table of a two-input AND gate are shown
in Figs 6.5 (a) and (b) respectively. The AND operation on two independent logic variables
A and B is written as Y =A.B and reads as Y equals A AND B and not as A multiplied by B.
Here, A and B are input logic variables and Y is the output. An AND gate performs an
ANDing operation:

Figure6.5: The logic symbol and truth table of a two-input AND gate.

Figure 6.6: (a) logic symbol for four-input AND gate and (b) the truth table of a four-input
AND gate.

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 Show the logic arrangement for implementing a four-input AND gate using two-input AND
gates only.

Figure 6.7: Implementation of a four-input AND gate using two-input AND gates.

6.3.3 NOT Gate

A NOT gate is a one-input, one-output logic circuit whose output is always the complement
of the input. That is, a LOW input produces a HIGH output, and vice versa. When interpreted
for a positive logic system, a logic ‘0’ at the input produces a logic ‘1’ at the output, and vice
versa. It is also known as a ‘complementing circuit’ or an ‘inverting circuit’. Figure 6.8
shows the circuit symbol and the truth table. The NOT operation on a logic variable X is
denoted as ̅ . That is, if X is the input to a NOT circuit, then its output Y is given by ̅
and reads as Y equals NOT X. Thus, if X=0, Y=1 and if X=1, Y=0.

Figure 6.8 (a) Circuit symbol of a NOT circuit and (b) the truth table of a NOT circuit.

6.3.4 EXCLUSIVE-OR Gate (EX-OR gate)

The output of EX-OR logic function is a logic ‘1’ when the number of 1s in the input
sequence is odd and a logic ‘0’ when the number of 1s in the input sequence is even,
including zero. That is, an all 0s input sequence also produces a logic ‘0’ at the output.

The output of a two-input EX-OR gate is expressed by:

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 Figures 6.9 (a) and (b) respectively show the logic symbol and truth table of a two-input EX-
OR gate.

Figures 6.9: (a, the logic symbol and b), truth table of a two-input EX-OR gate.

How can you implement a NOT circuit using a two-input EX-OR gate?

Solution

It is clear from the truth table that, if one of the inputs of the gate is permanently tied to logic
‘1’ level, then the other input and output perform the function of a NOT circuit. Figure 6.1.1
.(b) shows the implementation.

Figure 6.1.1: Implementation of a NOT circuit using an EX-OR gate.

6.3.5 NAND Gate

NAND stands for NOT AND. An AND gate followed by a NOT circuit makes it a NAND
gate. Figure 6.1.2 shows the circuit symbol of a two-input NAND gate and its truth table. The
truth table of a NAND gate is obtained from the truth table of an AND gate by
complementing the output entries. The output of a NAND gate is a logic ‘0’ when all its

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 inputs are a logic ‘1’. For all other input combinations, the output is a logic ‘1’. NAND gate
operation is logically expressed as:

In general, the Boolean expression for a NAND gate with more than two inputs can be
written as

Figure 6.1.2: a) The circuit symbol of a two-input NAND gate and b) its truth table.

6.3.6 NOR Gate

NOR stands for NOT OR. An OR gate followed by a NOT circuit makes it a NOR gate. The
truth table of a NOR gate is obtained from the truth table of an OR gate by complementing
the output entries. The output of a NOR gateis a logic‘1’when all its inputs are logic‘0’. For
all other input combinations, the output is a logic ‘0’. The output of a two-input NOR gate is
logically expressed as

In general, the Boolean expression for a NOR gate with more than two inputs can be written
as

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 Figure 6.1.3: a) the circuit symbol of a two-input NOR gate and, b) the truth table of a two-
input NAND gate.

6.3.7 EXCLUSIVE-NOR Gate

EXCLUSIVE-NOR (commonly written as EX-NOR) means NOT of EX-OR, i.e. the logic
gate that we get by complementing the output of an EX-OR gate. the output of a multiple-
input EX-NOR logic function is a logic ‘0’ when the number of 1s in the input sequence is
odd and a logic ‘1’ when the number of 1s in the input sequence is even including zero. That
is, an all 0s input sequence also produces a logic ‘1’ at the output. Figure 6.1.4 shows its
circuit symbol along with its truth table. The truth table of an EX-NOR gate is obtained from
the truth table of an EX-OR gate by complementing the output entries. Logically,

Figure 6.1.4: a) Circuit symbol of a two-input EXCLUSIVE-NOR gate and, b) the truth table
of a two-input EXCLUSIVE-NOR gate.

Activity:
1. Show the logic arrangements for implementing:

(a) a four-input NAND gate using two-input AND gates and NOT gates;

(b) a three-input NAND gate using two-input NAND gates;

(c) a NOT circuit using a two-input NAND gate;

(d) a NOT circuit using a two-input NOR gate;

(e) a NOT circuit using a two-input EX-NOR gate.

Solution

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 6.4 Universal Gates
OR, AND and NOT gates are the three basic logic gates as they together can be used to
construct the logic circuit for any given Boolean expression. NOR and NAND gates have the
property that they individually can be used to hardware-implement a logic circuit
corresponding to any given Boolean expression. That is, it is possible to use either only
NAND gates or only NOR gates to implement any Boolean expression. This is so because a
combination of NAND gates or a combination of NOR gates can be used to perform
functions of any of the basic logic gates. It is for this reason that NAND and NOR gates are
universal gates.

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 Asanillustration,Fig. 6.1.5 showshowtwo-inputNANDgatescanbeusedtoconstructaNOTcircuit
[Fig. . 6.1.5 (a)], a two-input AND gate [Fig. 6.1.5 (b)] and a two-input OR gate [Fig. 6.1.5
(c)]. Figure . 6.1.6 shows the same using NOR gates.

Figure . 6.1.5: Implementation of basic logic gates using only NAND gates.

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 Figure . 6.1.6: Implementation of basic logic gates using only NOR gates.

2. Draw the truth table of the logic circuit shown below.

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 3. Draw logic implementation of an inverter using (i) two-input NAND, (ii) two-input NOR,
(iii) two-input EX-OR and (iv) two-input EX-NOR.

answer

6.5 Flip-Flops
A flip-flop is a bistable circuit. Both of its output states are stable. The circuit remains in a
particular output state indefinitely until something is done to change that output status. In the
flip-flops of various types that are available in IC form, we will see that all these devices
offer complementary outputs usually designated as Q and ̅ . There are four types of flip
flops. These are R-S, J-K, T and D flip flops.

6.5 .1 R-S Flip-Flop

The R-S flip-flop is the most basic of all flip-flops. The letters ‘R’ and ‘S’ here stand for
RESET and SET. When the flip-flop is SET, its Q output goes to a ‘1’ state, and when it is
RESET it goes to a ‘0’ state. The ̅ output is the complement of the Q output at all times.

[Link] R-S Flip-Flop with Active LOW Inputs

Figure 6.1.7 a) shows a NAND gate implementation of an R-S flip-flop with active LOW
inputs. The two NAND gates are cross-coupled. That is, the output of NAND 1 is fed back to
one of the inputs of NAND 2, and the output of NAND 2 is fed back to one of the inputs of

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 NAND 1. The remaining inputs of NAND 1 and NAND 2 are the S and R inputs. The
outputs of NAND 1 and NAND 2 are respectively Q and ̅ outputs.

Figure 6.1.7: R-S flip-flop with active LOW inputs; a) NAND gate implementation, b)
logic symbol and c) truth table

The fact that this configuration follows the function table of Fig. 6.1.7 c) can be explained.
We will look at different entries of the function table, one at a time.

Let us take the case of R=S =1 (the first entry in the function table). We will prove that, for
R=S=1, the Q output remains in its existing state. In the truth table, represents the existing
state and represents the state of the flip-flop after it has been triggered by an
appropriate pulse at the R or S input. Let us assume that Q=0 initially. This ‘0’ state fed back
to one of the inputs of gate 2 ensures that ̅ . The ‘1’ state of ̅ fed back to one of the
inputs of gate 1 along with S=1 ensures that Q=0. Thus, R=S=1 holds the existing stage.
Now, if Q was initially in the ‘1’ state and not the ‘0’ state, this ‘1’ fed back to one of the
inputs of gate 2 along with R=1 forces ̅ to be in the ‘0’ state. The ‘0’ state, when fed back to
one of the inputs of gate 1, ensures that Q remains in its existing state of logic ‘1’. Thus,
whatever the state of Q, R=S=1 holds the existing state.

Let us now look at the second entry of the function table where S=0 and R=1. We can see
that such an input combination forces the Q output to the ‘1’ state. On similar lines, the input
combination S =1 and R=0 (third entry of the truth table) forces the Q output to the ‘0’ state.
It would be interesting to analyze what happens when S=R=0. This implies that both Q and ̅
outputs should go to the ‘1’ state, as one of the inputs of a NAND gate being a logic ‘0’
should force its output to the logic ‘1’ state irrespective of the status of the other input. This
is an undesired state as Q and ̅ outputs are to be the complement of each other. The input
condition (i.e. R=S=0) that causes such a situation is therefore considered to be an invalid
condition and is forbidden. Figure 6.1.7 b) shows the logic symbol of such a flip-flop. The R
and S inputs here have been shown as active LOW inputs, which is obvious as this flip-flop
of Fig. 6.1.7 a) is SET (that is, Q=1) when S=0 and RESET (that is, Q=0) when R=0. Thus, R

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 and S are active when LOW. The operation of the R-S flip-flop of Fig. 6.1.7 a) can be
summarized as follows:

Characteristic table of an R-S flip-flop with active LOW inputs is:

Figure 6.1.8: Characteristic table of an R-S flip-flop with active LOW inputs.
Characteristic equations for R-S flip-flops with active LOW inputs is
̅
[Link] R-S Flip-Flop with Active HIGH Inputs
Figure 6.1.9 a) shows another NAND gate implementation of the R-S flip-flop. Figures
6.1.9 b) and (c) respectively show its circuit symbol and function table. Such a circuit
would have active HIGH inputs. The input combination R=S =1 would be forbidden as
SET and RESET inputs in an R-S flip-flop cannot be active at the same time.

Figure 6.1.9: R-S flip-flop with active HIGH inputs.

Figure 6.2.0 the characteristic table of an R-S flip-flop with active HIGH inputs,

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 Figure 6.2.0 the characteristic table of an R-S flip-flop with active HIGH inputs

̅
6.5.2 J-K Flip-Flop
A J-K flip-flop behaves in the same fashion as an R-S flip-flop except for one of the
entries in the function table. In the case of an R-S flip-flop, the input combination S
=R=1 (in the case of a flip-flop with active HIGH inputs) and the input combination S
=R=0 (in the case of a flip-flop with active LOW inputs) are prohibited. In the case of a
J-K flip-flop with active HIGH inputs, the output of the flip-flop toggles, that is, it goes
to the other state, for J =K=1 . The output toggles for J =K=0 in the case of the flip-flop
having active LOW inputs. Thus, a J-K flip-flop overcomes the problem of a forbidden
input combination of the R-S flip-flop. Figures 6.2.1 a) and b) respectively show the
circuit symbol of J-K flip-flops with active HIGH and active LOW inputs, along with
their function tables.

Figure 6.2.1: a) J-K flip-flop active HIGH inputs and, b) J-K flip-flop active LOW inputs.

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 The characteristic equations for the J-K flip-flop with active HIGH J and K inputs and a
J-K flip-flop with active LOW J and K inputs are respectively

Figure 6.2.2: a) Characteristic table of a J-K flip-flop with active HIGH inputs, b) the
characteristic table of a J-K flip-flop with active LOW inputs
6.5.3 Toggle Flip-Flop (T Flip-Flop)
The output of a toggle flip-flop, also called a T flip-flop, changes state every time it is
triggered at its T input, called the toggle input. That is, the output becomes ‘1’ if it was
‘0’ and ‘0’ if it was ‘1’.
Its truth table is

6.5.4 D Flip-Flop
A D flip-flop, also called a delay flip-flop, can be used to provide temporary storage of
one bit of information. The characteristic equation is as follows:

The characteristic table of D flip-flop is:

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