CSE-312: Computer Architecture

Spring (Even) 2024-25

Lecture-5: Register Transfer

and Microoperations
Anil Kumar Singh
Dept. of CSE
IIT (BHU), Varanasi
 Register Transfer Language (RTL)
❏ Digital system: Interconnection of digital hardware modules
❏ Accomplish specific information-processing task
❏ Invariably use a modular approach
❏ Consist of registers, decoders, arithmetic elements and control logic
❏ Connected through common data and control paths
❏ (System) Best defined by the registers they contain and operations on them
❏ Operations called micro-operations: Elementary operations
❏ Shift, count, clear, load
❏ The result of operations might replace the contents of a register or it may be transferred
❏ Some digital components are registers implementing micro-operations
❏ E.g.: Counter with parallel load can do increment and load
❏ Bidirectional shift register can implement shift right and shift left
 Defining Internal Hardware
❏ Best defined by:
❏ Set of registers and their function
❏ Sequence of microoperations on contents of registers
❏ Control that initiates sequence of microoperations
❏ Instead of description, a ‘symbology’ or symbolic notation
❏ Called Register Transfer Language (RTL)
❏ More like a notation, but called a language
❏ By analogy with programming languages
❏ A symbol-system for sequence of microoperations
❏ Very few symbols, syntax and semantics
❏ Not hard to memorize and understand
❏ Differences in various RTLs only in variations of minor details
 Register Transfer
❏ Register denoted by capital letter and (optionally) numerals
❏ Names denote function: MAR for Memory Address Register, PC for Program Counter
❏ IR for Instruction Register, R1 for a processor register
❏ Individual bits (flip-flops) denoted by arguments PC(8-15) or PC(H) etc.
❏ Information transfer from one register to another with a replacement operator
❏ R2 <- R1 (content of R1 does not change after transfer)
❏ Implies hardware circuits available, e.g. parallel load capability
❏ Conditional transfer: If(P=1) then (R2 <- R1)
❏ P is control signal (function) from the control section: Usually separated from the transfer
❏ P: R2 <- R1 (Control condition separated by colon). If P = 1 then (R2 <- R1)
❏ Actual transfer occurs with positive clock transition at t+1
❏ Operations can be separated by a comma: T: R2 <- R1, R <- R2 (exchange)
❏ Simultaneous transfer possible with:
❏ Edge-triggered flip-flops
 BUS: Common Data Path
❏ Many registers: Paths needed for data transfer
❏ With separate lines too many wires: Common data path or bus
❏ One of each bit of a register: Transfer one at a time
❏ Controls signals determine register selection
❏ One way to implement bus system with multiplexers
❏ Select the source and put the contents on the bus
❏ For four registers: Four 4x1 multiplexers
❏ Each with 4 data inputs and two selection inputs S1 and S0
❏ Labels to show connections to avoid too many crossing lines
❏ In general, n-line common bus system with k multiplexers of n bits each
❏ Number of multiplexers equal to n (number of bits)
❏ Each multiplexer k x 1 as it multiplexes k data lines
❏ For 8 registers of 16 bits each: 16 multiplexers, one for each bit
❏ Each multiplexer has 8 data input lines and 3 selection lines (8 = 23)
❏ Selection lines connected to selection inputs of each multiplexer
❏ BUS <- C, R1 <- BUS: by activating the load control input of R1
Bus System for Four Registers
 Three-State Bus Buffer
❏ Bus system can be constructed with three-state gates instead of MUXes
❏ A digital circuit with with three states: 0, 1 and a high-impedance state
❏ High impedance state acts like an open circuit
❏ Meaning output is disconnected: no logic significance
❏ It can perform any conventional logic: AND, NAND etc.
❏ Most used in designing a bus system is a buffer gate
❏ The third special state allows large number of of gates to be connected
❏ With wires to form a common bus system without endangering loading effects
❏ Ex.: Four three-state buffers can be connected to create bus
❏ Not possible without three-state buffers
❏ Control inputs determine which buffer will communicate with bus line
❏ No more than one buffer active at a time
❏ Others in high-impedance state
❏ All four buffers inactive when enable input 0
❏ Works like 4 x 1 multiplexer
 Memory Transfer
❏ Transfer of information from memory word to outside: read operation
❏ Transfer of new information from outside to memory: write operation
❏ Memory word symbolized by letter M
❏ A particular memory word by memory address inside square brackets
❏ Memory unit receives address from a register AR, contents transferred to another register
❏ Read: DR <- M[AR];
❏ where DR is data register
❏ Write operation:
❏ Write: M[AR] <- R1
❏ Transfer to data from R1 into memory word selected by address in AR
 Arithmetic Microoperations
❏ Elementary arithmetic operations performed with data in registers
❏ Four most common categories of microoperations
❏ Register transfer micro-ops
❏ Transfer of binary information from one register to another
❏ Doesn’t change the information content
❏ Arithmetic operations on the contents of the registers
❏ Addition, subtraction, increment, decrement and shift
❏ Logic micro-ops: Bit manipulation operations on numeric data in registers
❏ Shift micro-ops: Shift operations on data in registers
❏ Subtraction usually implemented by addition with 1’s complement plus 1
❏ Which is 2’s complement
❏ Multiply and divide usually not included in the basis set of operations
❏ When included, implemented by a combinational circuit
❏ Result transferred to a register by a clock pulse after completion
❏ Multiplication often implemented by sequence of add and shift operations
Arithmetic Microoperations
 Binary Adder
❏ We need registers for the data
❏ And the digital components to perform addition
❏ Full adder: arithmetic sum of two bits with a (carry IN) and a carry OUT
❏ Binary adder: Sum of two binary numbers of any length
❏ Connected with full-adder circuits connected in a cascade
❏ Output carry of one going to the input carry of another
❏ Augend bits of A and Addend bits of B with subscript from right to left
❏ Carries connected in a chain through the full-adders
❏ S output of full-adders generate the required sum bits
❏ An n-bit binary requires n full-adders
❏ The bits for numbers come from two registers R1 and R2
❏ Result can be transferred to one of the source registers or to a third register
4-bit Binary Adder
 Binary Adder-Subtractor
❏ Subtraction can be done most conveniently by means of complements
❏ Subtraction can be done to addition of A and 2’s complement of B
❏ 2’s complement can be obtained from 1’s complement plus 1 to least significant pairs of bits
❏ 1’s complement can be implemented with inverters and one can be added
❏ To the sum through the input carry
❏ Addition and subtraction can be combined into one common circuit
❏ By including an exclusive-OR gate with each full-adder
❏ Mode input controls the operation: M = 0 for adder and 1 for subtractor
❏ Each XOR gets input M and one input of B
❏ When M = 0: B EXOR 0 = B, input carry is 0 and circuit performs addition
❏ When M = 1: B EXOR 1 = B’ and C0 = 1
❏ For u signed numbers it gives A - B if A >= B or 2’s complement of (B - A) if A < B
❏ For signed numbers the output is A - B if there is no overflow
4-bit Adder-Subtractor
 Binary Incrementer
❏ Increment micro-op adds one to a number in a register
❏ Easily implemented with a binary counter
❏ Every time the count enable is active
❏ A clock pulse transition increments the contents of a register by one
❏ One of the inputs to least significant half-adder (HA) is connected to logic 1
❏ The output connected to least significant bit of the number to be incremented
❏ Output carry from one half-adder connected to:
❏ One of the inputs of the next higher-order HA
❏ Circuit receives four bits A0 through A3, adds 1 to it
❏ Generates the incremented output in S0 through S3
❏ Output carry C4 will be 1 only after incrementing 1111
❏ Also causes output S0 through S3 to go to 0
❏ Can be extended to n-bit incrementer by including n HAs
❏ Least significant bit must have one input connected to logic 1
Binary Incrementer
 Arithmetic Circuit
❏ Arithmetic microoperations can be implemented in a single circuit
❏ Basic component for this is a parallel loader
❏ By controlling the data inputs to the adder different arithmetic operations can performed
❏ For a 4-bit arithmetic circuit
❏ Four full-adder circuits
❏ Four multiplexers for choosing the operation
❏ Two 4-bit inputs and one 4-bit output
❏ Two selection inputs
❏ Carry inputs and outputs in the full-adders
Arithmetic Circuit
 Logic Micro-operations
❏ Bit-by-bit (bitwise) logic operations
❏ Different symbols used in RTL for them
❏ To distinguish them from Boolean functions as used in designing logic gates
❏ And the logic operations in the logic circuit
❏ Context can disambiguate
❏ 16 different logic operations for two binary variables
Logic Micro-operations
 Logic Circuit
❏ Since operations are on bits separately, usual gates can be used
❏ Four gates usually are enough to implement the 16 operations
❏ AND, OR, XOR and complement
❏ Four gates and a multiplexer
❏ Two selection inputs
❏ Very useful for manipulating individual bits
❏ Or portion of a (memory) word stored in a register
❏ Some common operations:
❏ Selective set: Set some bits to one using logic-OR operation
❏ Selective complement: Sets some bit values to their complements using logic-XOR
❏ Selective clear: Sets some bits to 0 using logic-AND with complemented values
❏ Mask: Clearing bits only where corresponding 0s in B using logic-AND
❏ Insert: Inserting new values in groups of bits using masking and then logic-OR
❏ Clear: Sets all bits to 0s if two numbers are equal logic-XOR
Logic Circuit
 Shift Micro-operations
❏ Used for serial transfer to data
❏ Also in conjunction with arithmetic, logic and other data processing operations
❏ Contents of a register bit-shifted to the right or to the left
❏ Shift-left: Serial input transfer a bit into the rightmost position
❏ Shift-right: Serial input transfer a bit into the leftmost position
❏ The information transferred through the serial input determines the type of shift
❏ Three types of shift: logical, circular and arithmetic
❏ Logical shift: Transfer a 0 through the serial input
❏ Circular shift (rotate): Circulate the bits around the two end without loss
❏ By connecting serial output of the shift register to its serial input
❏ Arithmetic shift (left or right) of a signed binary number
❏ Multiplication or division by 2: Very useful even in high level programming languages
❏ Preserving the sign bit
❏ An overflow flip-flop can be used to detect an arithmetic shift-left overlow
 Shift Micro-operations
❏ Can be implemented in hardware by:
❏ A bidirectional shift register with parallel load
❏ Information can be transferred to the register in parallel
❏ And then bit-shifted
❏ One clock pulse for transferring the data into the register
❏ Another for bit-shifting
❏ In a processor with many registers:
❏ More efficient to implement with a combinational circuit
❏ Content of a register placed on a common bus
❏ Whose output is connected to the combinational shifter
❏ Shifted content then loaded back into register
❏ Requires only one clock pulse to load shifted content into a register
❏ Can be constructed with multiplexers
Arithmetic Logic Shift Unit
 Arithmetic Logic Shift Unit
❏ Instead of multiple registers performing micro-operations directly:
❏ Number of common register connected to a common operational unit (ALU)
❏ Connected to source registers and target register
❏ Shift operations often performed in a separate unit
❏ But can be made part of a common ALU
❏ Type of operation specified – understandably – with selection bits
One Stage of ALU
Arithmetic Logic Shift Unit
 Hardware Description Languages
❏ Design of complex digital systems at the gate and flip-flop is difficult process
❏ Also time consuming
❏ Digital systems can be described at the register transfer level:
❏ By means of Hardware Description Language (HDL)
❏ Viable solution for designing and debugging such systems
❏ At a higher level before conversion to gate and flip-flop level
❏ Computer-Aided Design (CAD) tools can be used
❏ Similar to conversion from high level languages to machine language
❏ By a compiler
❏ Some popular HDLs:
❏ VHSIC or VHDL and verilog HDL
❏ VHSIC: Very high speed integrated circuit
❏ HDLs can describe operations, IC design and test to verify design
 Introduction to VHDL
❏ industry standard to description, modelling and synthesis of digital systems
❏ Logic synthesis
❏ Process by which abstract form of desired circuit behaviour or model turned into design
implementation in terms of logic gates
❏ VHDL does not depend on specific programmable logic devices
❏ Or PLA (Programmable Logic Array) or FPGA (Field Programmable Gate Array)
❏ VHDL description can be placed in library and used again and again
❏ As technology develops
❏ Similar in syntax to OO languages like C++
❏ But not a programming language: a hardware description (representation) language
 VHDL: Basic Framework and Syntax
❏ Logic blocks: Split into two parts
❏ ENTITY: Much like a function declaration in C++. Just tell which device, not how it works
❏ ARCHITECTURE: Much like an actual function in C++