UNIT 2 COMBINATIONAL LOGIC

CIRCUITS

Static CMOS, Ratioed Circuits, Cascode Voltage Switch Logic, Dynamic

Circuits, Pass Transistor Logic, Transmission Gates, Domino, Dual Rail
Domino, CPL, DCVSPG, DPL, Circuit Pitfalls. Power Dissipation: Static
& Dynamic Power Dissipation.

1
 INTRODUCTION
• Digital logic is divided into combinational and sequential circuits.
• Combinational circuits are those whose outputs depend only on the
present inputs, while sequential circuits have memory.
• Generally, the building blocks for combinational circuits are logic gates,
while the building blocks for sequential circuits are registers and latches.
• Static CMOS gates used complementary nMOS and pMOS networks to
drive 0 and 1 outputs, respectively.
• RC delay model and logical effort is used to understand the sources of
delay in static CMOS logic. 2
 INTRODUCTION
Objectives:
• Examine techniques to optimize combinational circuits for lower delay
and/or energy
Advantages:
• power,
• robustness,
• Design Productivity considerations

3
 INTRODUCTION
• The delay of a logic gate depends on its output current I, load capacitance
C, and output voltage swing ∆V;

𝐶
𝑡𝛼 ∆V
𝐼
Circuit families:
Reason for other CMOS logic Configurations:
• certain circuits have particularly stringent speed, power, or density
restrictions that force another solution.
• Such alternative CMOS logic configurations are called circuit families.

• ratioed circuits, dynamic circuits, and Pass transistor circuits

4
 Static CMOS
BUBBLE PUSHING:
• CMOS stages are inherently inverting, so AND and OR functions must
be built from NAND and NOR gates.
• A NAND gate is equivalent to an OR of inverted inputs.
• A NOR gate is equivalent to an AND of inverted inputs.
• The same relationship applies to gates with more inputs.
• Switching between these representations is easy to do on a whiteboard
and is called bubble pushing.
EXAMPLE: Demorgans Law

5
Problem: Static CMOS
• Design a circuit to compute F = AB + CD using NANDs and NORs.
Solution :
Here, the circuit consists of two ANDs and an OR.
Step 1: The ANDs and ORs are converted to basic CMOS stages

-- ➔

Step 2: Bubble pushing is used to simplify the logic to three NANDs.

6
Drawback of Bubble Pushing:
• Number of Stages are more.
 COMPOUND GATES
• Particularly useful to perform complex functions with relatively low
logical efforts.
• static CMOS also efficiently handles compound gates by computing
various inverting combinations of AND/OR functions in a single stage.
• Example: The function F = AB + CD can be computed with an AND-OR
INVERT-22 (AOI22) gate and an inverter.

8
 Static CMOS
COMPOUND GATES: p →parasitic delay; G→ logical effort

9
 Static CMOS
COMPOUND GATES:
Drawback :

• Input Ordering Delay Effect

• The logical effort and parasitic delay of different gate inputs are often different.
Consider the falling output transition occurring when
one input held a stable 1 value and the other rises from 0
to 1:
• If input B rises last, node x will initially be at VDD – Vt
= VDD because it was pulled up through the nMOS
transistor on input A.
The Elmore delay is (R/2)(2C) + R(6C) = 7RC = 2.33
• If input A rises last, node x will initially be at 0 V because
it was discharged through the nMOS transistor on input B.
No charge must be delivered to node x.
The Elmore 10delay is simply R(6C) = 6RC = 2
 Static CMOS
Asymmetric Gates :

• In a Series network, the critical input arrives will offers less

series resistance.
• In a parallel network, the early input is connected to a
narrower transistor to reduce the parasitic capacitance.
• Under ordinary conditions, the path acts as a buffer between A
and Y.
• When reset is asserted, the path forces the output low.
• If reset only occurs under exceptional circumstances and can
take place slowly, the circuit should be optimized for input-to-
output delay at the expense of reset.
• The pulldown resistance is R/4 + R/(4/3) = R
• The capacitance on input A is only 10/3
• The logical effort is 10/9
11
Asymmetric Gates : Static CMOS

Advantages:
• Reduces its diffusion capacitance and parasitic delay at the expense of slower response
to reset.

Drawback :
It is not suitable for critical inputs

In other circuits such as arbiters, Gates are

build by perfectly symmetric so neither input
is favored.

12
 Static CMOS
Skewed Gates :
• It is used , when the one input transition is more important than the other.
• Two skewed gates are used.
➢ HI-skew gates →favors rising output transition
➢ LO-skew gates → favors falling output transition.
• This favoring can be done by decreasing the size of the noncritical transistor.
• The logical efforts for the rising (up) and falling (down) transitions are called gu and gd,
respectively.
• The ratio of the input capacitance of the skewed gate to the input capacitance of an
unskewed inverter with equal drive for that transition.

gd = 2.5/1.5 = 5/3

13
 Static CMOS
Skewed Gates (CONTD…)
• Alternating HI-skew and LO-skew gates can be used when only one transition is
needed.
• Skewed gates work particularly well with dynamic circuits,
P/N Ratios:

• The best P/N ratio for logic gates

• The ratio giving lowest average delay is the square root of the ratio that gives equal rise
and fall delays.
𝜇
• Mobility ratio should 𝑛 = 2.
𝜇𝑝

14
 Static CMOS
Multiple Threshold Voltages:

• Some CMOS processes offer two or more threshold voltages.

• Transistors with lower threshold voltages produce more ON current, but also leak

exponentially more OFF current.

• Libraries can provide both high- and low-threshold versions of gates.

• The low-threshold gates can be used sparingly to reduce the delay of critical paths

• Skewed gates can use low-threshold devices on only the critical network of transistors.

15
 Static CMOS
Drawback
• CMOS has a relatively large logical effort
Advantage :
• Good noise margins
• Fast
• Low power
• Insensitive to device variations
• easy to design
• Widely supported by CAD tools,
• Readily available in standard cell libraries.

16
 RATIOED CIRCUITS
• Ratioed circuits depend on the proper size or resistance of devices for
correct operation.
• It consists of an nMOS pulldown network and some pullup device
called the static load.
Operation:
• When the pulldown network is OFF, the static load pulls the output to
• When the pulldown network turns ON, it fights the static load. The
static load must be weak enough that the output pulls down to an
acceptable 0.
• Hence, there is a ratio constraint between the static load and pulldown
network.
• When weak 0 Exists,
• Stronger static loads →faster Output → VOL → noise margin
→static power
17
 RATIOED CIRCUITS
(a) A resistor is a simple static load but large resistors consume a large layout area in
typical MOS processes.
(b) Another technique is to use an nMOS transistor with the gate tied to VGG. If
VGG = VDD, the nMOS transistor will only pull up to VDD – Vt, the threshold is
increased by the body effect. Thus, using VGG > VDD was attractive.
(c) To eliminate this extra supply voltage, some NMOS processes offered depletion
mode transistors. These transistors, indicated with the thick bar, are identical to ordinary
enhancement mode transistors except that an extra ion implantation was performed to
create a negative threshold voltage. The depletion mode pullups have their gate wired to
the source so Vgs = 0 and the transistor is always weakly ON.
18
 RATIOED CIRCUITS

Advantages: Reduces the Chip area

19
Ratioed Logic
Ratioed Logic Concept
 PSEUDO NMOS
• The static load is built from a single
pmos transistor that has its gate
grounded so it is always ON.
• The DC transfer characteristics are
derived by finding Vout for which Idsn =
|Idsp| for a given Vin.
• The beta ratio affects the shape of
the transfer characteristics and the Pseudo-nMOS inverter
VOL of the inverter.
• Larger relative pMOS transistor sizes
offer faster rise times but less sharp
transfer characteristics.
 PSEUDO NMOS

• The above shows several pseudo-nMOS logic gates.

• The pulldown network is like that of an ordinary static gate, but the pullup network has
been replaced with a single pMOS transistor that is grounded so it is always ON.
• The pMOS transistor widths are selected to be about 1/4 the strength (i.e., 1/2 the
effective width) of the nMOS pulldown network as a compromise between noise
margin and speed;
• this best size is process-dependent, but is usually in the range of 1/3 to 1/6.
 Ganged CMOS

• Also called as symmetric2NOR

• When both inputs are 0 → both pMOS transistors turn on in parallel, pulling the
output high faster than they would in an ordinary pseudo nMOS gate.
• When both inputs are 1→both pMOS transistors turn OFF, saving static power
dissipation.
• Achieves both better performance and lower power dissipation than a 2-input
pseudo-nMOS NOR.
 Drawbacks in ratioed circuits

• Slow Rising Transitions,

• Contention On The Falling Transitions

• Static Power Dissipation, And

• Nonzero VOL.
 Cascode Voltage Switch Logic

a. Simple CVSL b. CMOS NAND c. 4-input XOR gate.

• It uses both true and complementary input signals and computes both true and
Complementary outputs using a pair of nMOS pulldown networks
• No static power dissipation occurs.
Advantages:
1. All of the logic is performed with nMOS transistors, thus reducing the input
capacitance .
2. Increased Speed.
 Cascode Voltage Switch Logic

Drawback :
1. CVSL gate requires both the low- and high-going transitions leads to adding
more delay thus Increases power consumption during switching period.
2. It is poorly suited to general NAND and NOR logic because it also requires the
complement, a slow tall NAND structure
 DYNAMIC CIRCUITS

• A clocked pullup transistor rather than a pMOS that is always ON.

• Dynamic circuit operation is divided into two modes namely precharge and evaluation
modes.
• During recharge, the clock is ∅, so the clocked pMOS is ON and initializes the output Y
high.
• During evaluation, the clock is 1 and the clocked pMOS turns OFF. The output may remain
high or may be discharged low through the pulldown network.
 DYNAMIC CIRCUITS

FEATURES:
• They have lower input capacitance
• No contention during switching.
• They also have zero static power dissipation.
• They require careful clocking
• Consume significant Dynamic power, and
• Sensitive to noise during evaluation.
DYNAMIC CIRCUITS- Footed Dynamic Inverter

• if the input A is 1 during precharge, contention will take place because both the
pMOS and nMOS transistors will be ON.
• When the input cannot be guaranteed to be 0 during precharge, an extra clocked
evaluation transistor can be added to the bottom of the nMOS stack to avoid
contention
 DYNAMIC CIRCUITS- Footed Dynamic Inverter

• if the input A is 1 during precharge, contention will take place because both the
pMOS and nMOS transistors will be ON.
• When the input cannot be guaranteed to be 0 during precharge, an extra clocked
evaluation transistor can be added to the bottom of the nMOS stack to avoid
contention.
• The extra transistor is sometimes called a foot
 DYNAMIC CIRCUITS- Footed Dynamic Inverter

• if the input A is 1 during precharge, contention will take place because both the
pMOS and nMOS transistors will be ON.
• When the input cannot be guaranteed to be 0 during precharge, an extra clocked
evaluation transistor can be added to the bottom of the nMOS stack to avoid
contention.
• The extra transistor is sometimes called a foot
DYNAMIC CIRCUITS- Footed Dynamic Inverter
• The pulldown transistors’ widths are chosen to give unit resistance.
• Precharge occurs while the gate is idle.
• The precharge transistor width is chosen for twice unit resistance.
• This reduces the capacitive load on the clock and the parasitic
capacitance at the expense of greater rising delays.
• Dynamic gates are particularly well suited to wide NOR functions or
multiplexers.
• Here, the logical efforts are independent of the inputs.
DYNAMIC CIRCUITS- Footed Dynamic Inverter

Footed Gates Unfooted Gates

Footed gates have higher logical effort logical
than their unfooted counterparts but are efforts are very low
still an improvement over static logic.
Velocity saturation means series nMOS High resistance
transistors have less resistance.
DYNAMIC CIRCUITS
DYNAMIC CIRCUITS
 DOMINO LOGIC

• The monotonicity problem can be solved by placing a static CMOS inverter

between dynamic gates
• The dynamic-static pair together is called a domino gate because precharge
resembles setting up a chain of dominos and evaluation causes the gates to
fire like dominos tipping over, each triggering the next.
 DOMINO LOGIC

• The monotonicity problem can be solved by placing a static CMOS

inverter between dynamic gates
 DOMINO LOGIC
• In general, more complex inverting static CMOS gates such as NANDs or NORs can be used in
place of the inverter .
• This mixture of dynamic and static logic is called compound domino.

• For example, The above figure shows an 8-input domino multiplexer built from two 4-input
dynamic multiplexers and a HI-skew NAND gate.
• This is often faster than an 8-input dynamic mux and HI-skew inverter because The dynamic stage
has less diffusion capacitance and parasitic delay.
 DOMINO LOGIC
Drawback:
• Domino gates are inherently noninverting, while some functions like XOR gates
necessarily require inversion.
Solution :
Three methods of addressing this problem include pushing inversions into static
logic, delaying clocks, and using dual-rail domino logic.
 Dual-Rail Domino Logic
• Dual-rail domino gates encode each signal with a pair of wires.
• The input and output signal pairs are denoted with _h and _l, respectively.
Dual-Rail Domino Logic
• Dual-rail domino gates encode each signal with a
pair of wires.
• The input and output signal pairs are denoted
with _h and _l, respectively.
• Dual-rail domino gates accept both true and
complementary inputs and compute both true
and complementary outputs.
• This is identical to static CVSL circuits except that
the cross-coupled pMOS transistors are instead
connected to the precharge clock.
• Therefore, dual-rail domino can be viewed as a
dynamic form of CVSL, sometimes called DCVS
Dual-Rail Domino Logic
• Dual-rail domino signals not only the result of a
computation but also indicates when the computation
is done.
• Before computation completes, both rails are
precharged.
• When the computation completes, one rail will be
asserted.
• A NAND gate can be used for completion detection.
• This is particularly useful for asynchronous circuits.
• Coupling can be reduced in dual-rail signal buses by
interdigitating the bits of the bus.
• Each wire will never see more than one aggressor
switching at a time because only one of the two rails
switches in each cycle.
 Pass-Transistor Circuits
• In pass-transistor circuits, inputs are also applied to the source/drain diffusion
terminals.
• These circuits build switches using either nMOS pass transistors or parallel pairs
of nMOS and pMOS transistors called transmission gates.
• Pass transistors are essential to the design of efficient 6-transistor static RAM
cells used in most modern systems.
• Full adders and other circuits rich in XORs also can be efficiently constructed
with pass transistors.
• static CMOS NAND and NOR gates are relatively efficient and benefit less from
pass transistors.
 Pass-Transistor Circuits
ADVANTAGES:
• Most Suitable For XOR Implementation(In CMOS , additional inverters are
required)
• Efficient
 DPL LOGIC (DIFFERENTIAL PASS-LOGIC)
• It is another logic family used in CMOS digital design, often focused on
improving power efficiency and speed.
• It is a differential logic family where pass transistors (typically NMOS or PMOS)
are used in combination with differential signaling to improve performance.
• It aims to address some of the issues associated with conventional CMOS logic,
such as speed and power dissipation.
 DPL LOGIC (DIFFERENTIAL PASS-LOGIC)
Key Characteristics:
• It operates with differential signals (complementary signals for both true and
false values). This gives it an advantage in noise immunity and signal integrity,
making it suitable for high-speed designs.
• By using differential signals, DPL avoids the issues of single-ended logic, which
can be more susceptible to noise, especially in high-frequency circuits.
• DPL relies heavily on pass transistors (usually NMOS or PMOS) to propagate
logic states.
• The use of pass transistors allows for fast switching and reduced power
dissipation compared to traditional CMOS logic gates, where static current
flows in the pull-up or pull-down resistors even when no switching occurs.
 DPL LOGIC (DIFFERENTIAL PASS-LOGIC)
Speed and Power Efficiency:
• It offers improved speed and lower power consumption compared to
conventional CMOS logic families because of the elimination of static power
consumption and the use of efficient differential signaling.
• Since only dynamic changes occur when switching between logic states, DPL
reduces the power consumed during the non-switching phase, making it
especially useful for low-power applications.
Applications:
• It is commonly used in high-performance digital circuits where power and
speed are crucial factors, such as signal processing, microprocessors, and high-
speed memory systems.
 DPL LOGIC (DIFFERENTIAL PASS-LOGIC)
Basic Structure of a DPL Gate:

A typical DPL gate includes:

Differential Inputs: Two complementary inputs
(true and complement) are provided to the gate.
Pass Transistors: These transistors (either NMOS
or PMOS) are used to implement the logic
function, passing the differential signals to the
output based on the logic level.
Differential Outputs: The outputs are also
differential, meaning they carry complementary
signal levels to represent logic states.
 DPL LOGIC (DIFFERENTIAL PASS-LOGIC)
Advantages of DPL:
[Link] Power Consumption: Because there are no static power dissipation
components (such as resistors in conventional CMOS), DPL offers significant
power savings, particularly in idle states.
[Link]-Speed Operation: The use of pass gates and differential signals helps
achieve faster switching speeds.
[Link] Immunity: Differential logic helps to reduce susceptibility to noise, which
is crucial in high-speed applications.
Differential Cascode Voltage Switch with Pass Gate
Logic(DCVSPG)
Differential Cascode Voltage Switch Logic (DCVSL):
• DCVSL is a high-speed, low-power logic family commonly used in CMOS
circuits. It improves upon conventional CMOS logic by using a differential input
structure that can enhance noise margins and reduce switching power dissipation.
• The core of DCVSL consists of pass-gate transistors (typically NMOS and
PMOS) arranged in a differential configuration.
• This allows the logic to handle both low and high logic levels efficiently, often
with reduced energy consumption compared to static CMOS circuits.
• Cascode refers to the arrangement of transistors that helps to improve output
resistance and overall performance.
Differential Cascode Voltage Switch with Pass Gate
Logic(DCVSPG)
Pass Gate Logic (PGL):
•Pass Gate Logic involves the use of pass transistors (usually NMOS or PMOS) to
directly pass logic signals through different parts of the circuit. This is in contrast to
traditional logic gates, which use pull-up or pull-down networks to define logic levels.
•Pass gates are used to implement simple logic functions and can be integrated into more
complex circuits to allow better performance in terms of speed and power consumption.
 Differential Cascode Voltage Switch with Pass Gate Logic(DCVSPG)

Working Principle:
• The DCVSL logic family is designed to operate differentially, meaning that
both the true and complement signals are handled simultaneously.
• This improves noise immunity and signal integrity compared to single-
ended logic families.
• Pass gate logic is typically incorporated into DCVSL circuits to enable
efficient signal routing while maintaining the integrity of the logic levels
across the circuit.
 Differential Cascode Voltage Switch with Pass Gate
Logic(DCVSPG)
Benefits of DCVSL with Pass Gate Logic:
• Low Power Consumption: The differential nature of DCVSL minimizes power
dissipation in many cases, especially in comparison to static CMOS logic.
• Noise Immunity: By utilizing differential signals, DCVSL offers better noise
immunity, which is critical for high-speed circuits.
• High-Speed Performance: The cascode and pass gate structure contributes to
fast switching, especially in high-frequency applications.
 Differential Cascode Voltage Switch with Pass Gate
Logic(DCVSPG)
Benefits of DCVSL with Pass Gate Logic:
• Low Power Consumption: The differential nature of DCVSL minimizes power
dissipation in many cases, especially in comparison to static CMOS logic.
• Noise Immunity: By utilizing differential signals, DCVSL offers better noise
immunity, which is critical for high-speed circuits.
• High-Speed Performance: The cascode and pass gate structure contributes to
fast switching, especially in high-frequency applications.
 CMOS with Transmission Gates
• Structures such as tristates, latches, and multiplexers are often drawn as
transmission gates in conjunction with simple static CMOS logic.
• The circuit was nonrestoring; i.e., the logic levels on the output are no better
than those on the input so a cascade of such circuits may accumulate noise.
• To buffer the output and restore levels, a static CMOS output inverter can be
added called as CMOSTG.
CMOS with Transmission Gates
• A single nMOS or pMOS pass transistor suffers from a
threshold drop.
• If used alone, additional circuitry may be needed to pull the
output to the rail.
• Transmission gates solve this problem but require two
transistors in parallel.
• The resistance of a unit-sized transmission gate can be
estimated as R for the purpose of delay estimation.
• Current flows through the parallel combination of the nMOS
and pMOS transistors.
• One of the transistors is passing the value well and the other
is passing it poorly;
 CMOS with Transmission Gates
Why a transmission gate made from unit transistors is approximately R in
either direction?
• In a transmission gate, One of the transistors is passing the value well and the
other is passing it poorly;
• When a logic 1 is passed, the current is passed well through the pMOS but poorly
through the nMOS.
• When passing a 0, the resistance is R
• || 4R = (4/5)R. The effective resistance passing a 1 is 2R || 2R = R.
Drawback :
• Boosting the size of the pMOS transistor only slightly improves the effective
resistance while significantly increasing the capacitance
CMOS with Transmission Gates
• From transistor level diagram, the shorting of the
intermediate nodes has two effects on delay.
• The effective resistance decreases somewhat
(especially for rising outputs) because the output
is pulled up or down through the parallel
combination of both pass transistors rather than
through a single transistor.
• However, the effective capacitance increases
slightly because of the extra diffusion and wire
capacitance required for this shorting.
 CMOS with Transmission Gates

• From the above figure, both are different based on contacted diffusion on N1
and N2 while the static CMOS gate.
• In most processes, the improved resistance dominates for gates with moderate
fanouts, making shorting generally faster at a small cost in power.
CMOS with Transmission Gates
Drawbacks:
• This input driver sensitivity makes characterizing
the gate more difficult and is incompatible with
most timing analysis tools.
• Diffusion inputs to tristate inverters are
susceptible to noise that may incorrectly turn on
the inverter.
• The contacts slightly increase area and their
capacitance.
• Increases power consumption.
• The logical effort of circuits involving transmission
gates is computed by drawing stages that begin at
gate inputs rather than diffusion inputs,
 Complementary Pass Transistor Logic (CPL)
• It has both NMOS and PMOS transistors are used in a complementary
manner that helps reduce the number of transistors required compared to
traditional CMOS logic.
• The key advantage is that CPL circuits typically have faster switching speeds
and lower power consumption because they reduce the need for complex pull-
up and pull-down networks.
 Complementary Pass Transistor Logic (CPL)
WORKING PRINCIPLE:
• Pass Transistors:NMOS transistors are used for pulling the node to ground,
while PMOS transistors are used to pull the node to VDD (power
supply).Each logic gate typically consists of a combination of pass transistors
and inverters to form the desired output.
• Complementary Structure:The term “complementary” refers to the fact that
for each logic function, a pair of transistors (PMOS and NMOS) work
together, ensuring that the logic function is achieved more efficiently.
• Example Gate: A NAND gate in CPL might use an NMOS pass transistor to
pull the output low when both inputs are high, and a PMOS pass transistor
to pull the output high when either input is low.
 Complementary Pass Transistor Logic (CPL)

Advantages of CPL:
• Speed: Faster operation due to fewer transistors and reduced parasitic capacitances.
• Lower Power Consumption: Since the output node is often driven directly by a pass
transistor (and not by a full CMOS inverter), the logic gates can consume less dynamic
power.
• Compactness: CPL circuits require fewer transistors than standard CMOS logic, making
them more area-efficient for certain applications.
 Complementary Pass Transistor Logic (CPL)
Disadvantages of CPL:
•Voltage Loss: Pass transistors in CPL can suffer from voltage
degradation (a voltage drop) when the input signal is not fully charged,
which can affect the output logic levels, especially for NMOS pass
transistors (since they have a threshold voltage drop).
•Complexity in Design: CPL circuits can be harder to design and
require careful planning of signal paths and transistor sizing to
maintain correct logic levels.
 Complementary Pass Transistor Logic (CPL)
• If a path consists of a cascade of CPL gates, the inverters can be viewed
equally well as being on the output of one stage or the input of the next.
• When the gate switches, one side pulls down well through its nMOS
transistors.
• The other side pulls up. CPL can be constructed without cross-coupled pMOS
transistors, but the outputs would only rise to VDD – Vt.
Drawbacks:
• This costs static power because the output inverter will be turned slightly
ON.
• Adding weak cross-coupled devices helps bring the rising output to the
supply rail while only slightly slowing the falling output.
• The output inverters can be LO-skewed to reduce sensitivity to the slowly
rising output.
 Circuit Pitfalls
• Circuit designers tend to use simple circuits because they are robust.
• Elaborate circuits, tend to add more area, more capacitance, and more
things that can go wrong.
• Static CMOS is the most robust circuit family and should be used
whenever possible.
• A variety of circuit pitfalls that can cause chips to fail. They include the
following:
 Circuit Pitfalls
• Threshold drops
• Ratio failures
• Leakage
• Charge sharing
• Power supply noise
• Coupling
• Minority carrier injection
• Back-gate coupling
• Diffusion input noise sensitivity Race conditions
• Delay matching
• Metastability
• Hot spots
• Soft errors
• Process sensitivity
 Sources of Power Dissipation
Definition of Power Dissipation:
Power dissipation refers to the energy consumed by a circuit, typically in the
form of heat, as it performs its operations.
Types of Power Dissipation in Digital Circuits:
• Static Power Dissipation
• Dynamic Power Dissipation
 Sources of Power Dissipation
Power dissipation in CMOS circuits comes from two components:
• Dynamic dissipation due to
➢ Charging and discharging load capacitances as gates switch
➢ “short-circuit” current while both pMOS and nMOS stacks are
partially ON
• Static dissipation is due to
○ subthreshold leakage through OFF transistors
○ gate leakage through gate dielectric
○ junction leakage from source/drain diffusions
○ contention current in ratioed circuits (see Section 9.2.2)
 Sources of Power Dissipation
• Putting this together gives the total power of a circuit gives,

• Power can also be considered in active, standby, and sleep modes.

• Active power is the power consumed while the chip is doing useful work.
• Standby power is the power consumed while the chip is idle.
• In sleep mode, the supplies to unneeded circuits are turned off to eliminate leakage
 Static Power Dissipation
Leakage Current: In CMOS, static power dissipation primarily comes from
leakage currents, especially as transistor sizes shrink.
Subthreshold leakage: Current when the transistor is supposed to be off
but still allows a small current.
Gate oxide leakage: Current leakage through the thin gate oxide.
Factors Affecting Static Power:
Supply voltage, Process technology, Temperature
 Static Power Dissipation
Io = Is(eqV/kT – 1)
Is →reverse saturation current ;
V → diode voltage
q → electronic charge

Where,
𝑛
Static Power = Ps = σ1 𝑙𝑒𝑎𝑘𝑎𝑔𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑋 𝑠𝑢𝑝𝑝𝑙𝑦 𝑣𝑜𝑙𝑡𝑎𝑔𝑒
Where n = number of devices
 Dynamic Power Dissipation
Dynamic power is the power consumed when the CMOS circuit is actively switching. It is
the most significant form of power dissipation in high-speed digital circuits.
Components of Dynamic Power:
• Switching Power: Power consumed during switching events.
• Short-circuit Power: Power dissipated during the overlap of both
transistors being on.
• Short-circuit current: Small but noticeable current flow between the
supply and ground during switching.

1 𝑡𝑝/2 1 𝑡𝑝
Pd = ‫׬‬0
𝑖𝑛 𝑡 𝑉𝑜𝑢𝑡𝑑𝑡 + ‫׬‬𝑡𝑝/2
𝑖𝑝 𝑡 (𝑉𝑑𝑑 − 𝑉𝑜𝑢𝑡)𝑑𝑡
𝑡𝑝 𝑡𝑝
Pd = CLVDD2fp
Where,
C: Capacitance; V: Supply voltage; f: Clock frequency
Short Circuit Dissipation:
Power Dissipation
It is a specific component of static power dissipation. As process nodes shrink (moving
from, for example, 45nm to 32nm), the leakage current increases due to the reduced
threshold voltage and other effects.
Types of Leakage Currents:
Subthreshold Leakage: When a transistor is turned off, there is still a small current that
flows between the source and drain due to thermal excitation.
Gate Oxide Leakage: This occurs when a small current flows through the gate oxide,
typically due to tunneling effects at smaller dimensions.
Junction Leakage: Caused by minority carriers in the pn-junctions of the MOSFETs.
Formula for Leakage Power: Psc = [Link] ; Psc = 𝛽/12(VDD-2Vt)3trf/tp

Total Power Dissipation: The total power dissipation in a CMOS circuit is the sum of
dynamic, static, and leakage power.

Ptotal = Ps+Pd+Psc
 Power Dissipation
Techniques to Reduce Power Dissipation
There are several strategies to reduce power consumption in CMOS circuits:
Low-VDD Design: Reducing the supply voltage is the most effective way to
reduce dynamic power since it is proportional to V2. However, lower voltage also
reduces the speed of the circuit.
Clock Gating: This technique turns off the clock to sections of the circuit that are
not in use, reducing dynamic power dissipation.
Power Gating: This technique completely shuts off the power supply to inactive
parts of the circuit, reducing both dynamic and static power dissipation.
Multi-Threshold CMOS (MTCMOS): This uses different threshold voltages for
different parts of the circuit to reduce leakage in non-critical areas.
Dynamic Voltage and Frequency Scaling (DVFS): This allows for adjusting the
voltage and frequency of the system based on the workload, thereby reducing
power consumption when full performance is not needed.
Thank You…