HINDUSTHAN COLLEGE OF ENGINEERING AND TECHNOLOGY

(An Autonomous Institution Affiliated to Anna University, Chennai)

(Approved by AICTE, New Delhi, Accredited by NAAC with ‘A++’ Grade)

Coimbatore - 641 032.

B.E- Computer Science and Engineering

22CS3203 - Digital Principles and Computer Organization

UNIT 1

COMBINATIONAL CIRCUITS
Circuits for arthmetic operations:adder : Half adder,full adder,Subtractor : Full subtractor-BCD adder-
Magnitude comparator-Encoders,Decoders Multiplexers,Demultiplexers,Code converters,binary to
gray,gray to binary

1. Introduction to Combinational circuits

Combinational Logic Circuits are made from the basic and universal gates. The output is defined by
the logic and it is depend only the present input states not the previous states.

Inputs and output(s) : logic 0 (low) or logic 1 (high).

Fig. Block diagram of a combinational circuits

Analysis and design procedures

The following are the basic steps to design a combinational circuits

1. Define the problem.

2. Determine the number of input and output variables.

3. Fix a letter symbols to the input and the outputs. (eg. A,B,C ,w, x, Y,F, etc)

4. Get the relationship between input and output from the truth table.

5. By using K-map obtain the simplified Boolean expression for the outputs.

6. Draw the logic diagram using gates.

Example : Design a combinational logic circuit with three inputs , the output is at logic 1 when more
than one inputs are at logic 1.

Solution: Assume A, B, C are inputs and Y is output .

Truth table

K map Simplification

Boolean Expression

Y=AC + BC + AB

Logic Diagram

Inputs Output

ABCY

0 0 00

0 0 10

0 1 00

0 1 11

1 0 00

1 0 11

1 1 01

1 1 11
 2. Adder

The Basic operation in digital computer is binary addition. The circuit which perform the addition of
binary bits are called as Adder.

The logic circuit which perform the addition of two bit is called Half adder and three bit is called Full
adder.

Rules for two bit addition

0+0=0

0+1=1

1+0=1

1 + 1 = 102

1. Half Adder

The two inputs of the half adders are augend and addend, the outputs are sum and carry.
Input Outputs
s

A B Carry Sum

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

2. Full Adder

The three inputs of the full adders are augend , addend and the carry input from the previous
addition, the outputs are sum and carry

Block diagram of Full adder

Inputs Outputs

A B Ci Cout Sum
n

000 0 0

001 0 1

010 0 1

011 1 0

100 0 1

101 1 0

110 1 0

111 1 1

The Full Adder can be implement using Two Half Adders and OR gates

The expression for sum is

The Expression for carry is

Logic Diagram

3. Subtractor

Subtractor is the logic circuit which is used to subtract two binary number (digit) and provides
Difference and Borrow as a output. In digital electronics we have two types of subtractor, Half
Subtractor and Full Subtractor.

Rules for two bit addition

0-0=0

0 - 1 = 1 with borrow 1

1-0=1

1-1=0

1. Half Subtractor
Half Subtractor is used for subtracting one single bit binary digit from another single bit binary

[Link] truth table of Half Subtractor is shown below.

Input Outputs
s

A B Difference Borrow

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

2. Full Subtractor

A logic Circuit Which is used for Subtracting Three Single bit Binary digit is known as Full
[Link] inputs are A,B, Bin and the outputs are D and Bout.

Inputs Outputs

A B Bin D Bout

000 0 0

001 1 1
010 1 1

011 0 1

100 1 0

101 0 0

110 0 0

111 1 1

We can further simplify the function of the Difference (D)

Simplified Logic diagram

 4. BCD Adder

In digital system, the decimal number is represented in the form of binary coded decimal (BCD).The
ten digit (0-9) decimal numbers are represented by the binary digits. The circuit which add the two
BCD number is called BCD adder. The BCD cannot be greater than 9. The representation of the BCD
number as follows, consider the 526 it can be expressed as

There are three different cases in BCD Addition

i. Sum is less than or equal to 9 with carry 0

Consider the addition of two BCD numbers 6 and 3, The addition is performed as normal binary
addition

ii. Sum is greater than 9 with carry 0

consider the number 6 and 8 in BCD

The sum is invalid BCD number, Add the sum with correction number 6

After addition of 6 carry is produced into the second decimal position.

iii. Sum equals 9 or less with carry 1

Consider the addition of 8 and 9 in BCD.

The result 0001 0001 is valid BCD number but it is incorrect. Add 6 to get correct number.
The procedure for BCD addition is

1. Add two BCD numbers using ordinary binary addition.

2. If four bit sum is less than or equal to zero, then correction is needed.

3. If the four bit sum is greater than 9 or if carry is generated then add 0110.

Implementation of BCD Adder

We require 4-bit binary adder for initial addition, Logic circuit to detect sum greater than 9, and
second 4 bit binary adder to add 0110.

The following truth table is used to design a circuit for the sum, which is greater than 9

Inputs Output K map for carry (Y) identification

S3 S2 S1 S0 Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0
Y = S3S2 + S3S1
0 1 0 1 0
If Y=1 add 0110 using binary adder
0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1
1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

Block diagram of Binary Adder

[Link] diagram of BCD adder

The binary adder add two BCD numbers, ifcarry is ‘0’ nothing to be added. If carry is ‘1’ add 0110
with the sum, consider the overall carry from the first stage of the addition.

Example : Design an8-bit BCD adder using IC 74283.

Solution: Use two 4-bit BCD adder to design 8-bit binary adder.
Fig. 8- bit BCD Adder using IC 74283

5. Decoder

Decoder is a combinational circuit. It has N inputs and 2N outputs.

2 to 4 Decoder

It has 2 inputs and 22 = 4 outputs.

Circuit Diagram
Truth Table

Logic Diagram

2 to 4 Decoder with Enable input

Truth Table
Logic Diagram

3 to 8 Decoder

It has 3 inputs and 23 = 8 outputs.

Logic Diagram

6. Encoders
Encoders is a combinational circuit which takes 2N inputs and gives out N outputs, the enable pin
should be kept 1 for enabling the circuit.

4 to 2 Encoder

It has 22 inputs and 2 outputs.

1. Priority Encoders

A Priority Encoder works opposite of the decoder circuit. If more than one input is active, the higher
order input has priority.
4 to 2 Priority Encoders

D0-D3 - inputs A1,A0 – outputs

Active (A)– Valid indicator. It indicates the output is valid or not Output is invalid when no inputs are
active .i.e, A=0

Output is valid when at least one input is active .i,e, A=1

K-map simplification

Logic Diagram
3 to 8 Priority Encoder

7. Mutliplexer (Mux)

Multiplexer is a combinational circuit that selects binary information from one of many inputs and
directs it into single output.

The selection of particular input is controlled by a set of selection line Mutliplexer has 2n inputs, n
select line (control input) and one output

It also called as Data selector

2 to 1 Multiplexer
has 21 inputs, 1 select line and one output

Circuit diagram

4 to 1 MUX

4 to 1 MUX has 22 = 4 inputs, 2 select line and one output

8 to1 MUX

8 to1 MUX has 23 = 8 inputs, 3 select line and one output

1. MUX as universal combinational modules

Each minterm of the function can be mapped to a data input of the multiplexer.

For each row in the truth table, where the output is 1, set the corresponding data input of the mux
to [Link] the remaining inputs of the mux to 0.

Example 1: Implement the following Boolean function using 4:1 MUX F(x,y,z) = Σm(1, 2, 6, 7)

Truth Table
Multiplexer Implementation

Example 2: Implement the following Boolean function using 8:1 MUX

F(A,B,C,D) = Σm(1, 3, 4, 11,12-15)

 8. Demultiplexer (DEMUX)

Demultiplexer has 2n outputs , n select lines, one input. A demultiplexer is also called a data
distributor.

1. to-2 demultiplexer

has 22 outputs , 2 select lines, one input.

The truth table

Logic diagram

1-to-4 Demultiplexer

It has one input,2 select lines,4 outputs

The truth table

Logic Diagram

1-to-8 Demultiplexer

Has one input 3-select lines 8-outputs

The truth table
Logic Diagram
1-to-8 DEMUX using Two 1-to- 4 Demultiplexers

1-to-8 demultiplexer can be implemented by using two 1-to-4 demultiplexers with a proper
cascading.

In the above figure, the highest significant bit A of the selection inputs are connected to the enable
inputs such that it is complemented before connecting to one DEMUX and to the other it is directly
[Link] this configuration, when A is set to zero, one of the output lines from Y0 to Y3 is
selected based on the combination of select lines B and C. Similarly, when A is set to one, based on
the select lines one of the output lines from Y4 to Y7 will be selected.

1. Applications of Demultiplexer

 Synchronous data transmission systems

 Boolean function implementation (as we discussed full subtractor function above)

 Data acquisition systems

 Combinational circuit design

 Automatic test equipment systems

  Security monitoring systems (for selecting a particular surveillance camera at a time), etc.

9. CODE CONVERTORS

Numbers are usually coded in one form or another so as to represent or use it as required. For
instance, a number ‘nine’ is coded in decimal using symbol (9)d. Same is coded in natural- binary as
(1001)b. While digital computers all deal with binary numbers, there are situations wherein natural-
binary representation of numbers in in-convenient or in-efficient and some other (binary) code must
be used to process the numbers.

One of these other code is gray-code, in which any two numbers in sequence differ only by one bit
change. This code is used in K-map reduction technique. The advantage is that when numbers are
changing frequently, the logic gates are turning ON and OFF frequently and so are the transistors
switching which characterizes power consumption of the circuit; since only one bit is changing from
number to number, switching is reduced and hence is the power consumption.

Let’s discuss the conversion of various codes from one form to other.

1. BINARY-TO-GRAY

The table that follows shows natural-binary numbers (upto 4-bit) and corresponding gray codes.
Looking at gray-code (G3G2G1G0), we find that any two subsequent numbers differ in only one bit-
change.

The same table is used as truth-table for designing a logic circuitry that converts a given 4-bit natural
binary number into gray number. For this circuit, B3 B2 B1 B0 are inputs while G3 G2 G1 G0 are
outputs.

K-map for the outputs:

And G3 = B3
So that’s a simple three EX-OR gate circuit that converts a 4-bit input binary number into its
equivalent 4-bit gray code. It can be extended to convert more than 4-bit binary numbers.

2. Gray-to-Binary

Truth-table:

Then the K-maps:

And B3 = G3

The realization of Gray-to-Binary converter is

10. Comparators

 A comparator will evaluate two binary strings and output a 1 if the two strings are exactly the
same.

 The Exclusive-NOR (Equality gate) is used to perform the comparison.

 One Exclusive-NOR is used per pair of Binary bits and the outputs of all Exclusive-NORS are
ANDed together.
  The 7485 is a 4-bit magnitude comparator.

A magnitude comparator will determine if A = B, A > B or A < B.

 Expansion inputs are provided on the 7483 so that word sizes larger then 4-bits may be
compared.
Magnitude Comparator Definition

A magnitude comparator is a combinational circuit that compares two numbers A & B to determine
whether:

A > B, or A = B, or A < B

2. bit magnitude comparator

4-bit magnitude comparator Inputs: 8-bits (A ⇒ 4-bits , B ⇒ 4-bits) A and B are two 4-bit numbers

_ Let A = A3A2A1A0 , and

_ Let B = B3B2B1B0

_ Inputs have 28 (256) possible combinations

_ Not easy to design using conventional techniques

The circuit possesses certain amount of regularity⇒ can be designed algorithmically. Design of the
EQ output (A = B) in 4-bit magnitude comparator