R. V. S.
COLLEGE OF ENGINEERING
RVS NAGAR, KARUR ROAD, DINDIGUL - 624 005
Affiliated to Anna University, Chennai & Approved by AICTE, New Delhi
INTERNAL ASSESSMENT I
III SEMESTER
B.E ECE-EC 3352– VLSI & CHIP DESIGN
Date : 19.09.2024 FN Time : 2.30 to 4.00
Faculty : [Link] Max. Marks : 50
Q. No Marks B.L CO’s
PART A (5 x 2=10 Marks)
Answer all the Questions
1 What is threshold voltage and body effect is with refers to mos transistor 2 1 1
2 Write the advantages CMOS technology 2 1 1
3 Draw the I-V characteristics and operating regions of MOS transistor 2 1 2
4 Define any two layout design rules. 2 1
4 What are factors that causes static power dissipation in CMOS circuits 2 2 1
5 List the various power losses in CMOS circuits. 2 2 2
PART B (2x 13 = 26 Marks)
Answer all the Questions
11 (a) Explain in detail about ideal and NON-ideal characteristics of MOS 13 1 1
transistor
[OR]
11 (b) Explain in detail about N-MOS transistor structure and operation 13 3 1
12(a) Describe the equation for source to drain current in the three regions
of operation of a MOS transistor and draw the VI characteristics.
[OR]
12(b)
12 (a) Discuss the design technique to reduce switching activity in a static 13 2 2
and dynamic C-MOS circuit
[OR]
12 (b) Give a brief notes on the theory and design of pass transistor 7 2 2
(i) logic
(ii) Explain the detail about pseudo-nmos gates circuit with neat 6 2 2
diagram
PART C (1 x 14=14 Marks)
Explain in detail about low power design prinicple
13 (a) 14 2 1
[OR]
13 (b) 7 2 2
Design stick diagram for two inputs N-MOS NAND gate
(i)
(ii) Design a stick diagram for N-MOS logic shown as Y=(A+B+C)’ 7 3 2
Signature of the Faculty Head of the Department
