SRI VIDYA COLLEGE OF ENGINEERING & TECHNOLOGY
DEPARTMENT OF ECE
QUESTION BANK
SUBJECT: EC8095 – VLSI DESIGN
SEM / YEAR: VI / III year
UNIT I – INTRODUCTION TO MOS TRANSISTOR
Part -A
1 What are the steps involved in IC fabrication?
2 Compare nMOS and pMOS transistor.
3 Define and List the effect of body bias voltage. (Nov/ dec -16)
4 Summarize the different types of scaling technique.
5 Illustrate latch up condition in CMOS circuits? How to prevent it? (May /June -16)
6 Define propagation delay of CMOS inverter (Apr/may -17)
7 Describe the lambda based design rules used for layout.
8 What is stick diagram? Sketch the stick diagram for CMOS inverter
9 Explain the hot carrier effect.
10 Draw the DC transfer characteristics of CMOS inverter.
11 What are the different operating modes of transistor?
12 Classify SPICE models for MOS transistor.
13 What is Channel length Modulation (Apr/may -17) (May /June -16)
14 Write the threshold voltage equation for nMOS and for pMOS transistor?
15 Discuss the need of design rules.
16 Define body effect and write the threshold equation including the body effect.
17 Design a 3 input NAND gate.
18 List out second order effects of MOS transistor.
19 Determine whether an nMOS transistor with a threshold voltage of 0.7v is operating in the
saturation region if GSV=2v and DSV=3v.
20 Summarize the equation for describing the channel length modulation effect in nMOS transistor.
21 Why the tunneling current is higher for nMOS transistors than pMOS transistors with silica gate?
22 Define any two Layout Design rules (May/June -16)
Part -B
22 Explain in detail about the i)ideal I-V characteristics of nMOS and pMOS devices
(ii) non-ideal I-V characteristics of nMOS and pMOS devices.
23 Explain the need of Scaling, scaling principles and fundamental units of CMOS inverter
(Apr/May-17) (May/June -16)
24 Illustrate with necessary diagrams the i) CV characteristics of CMOS. (May/June -16) (Nov/Dec-
16)
ii)Explain DC transfer characteristics of CMOS.(Nov/Dec-16),(Apr/May-17) (May/June -16)
25 i)Derive the drain current of MOS device in different operating regions.
ii)With neat diagram explain the n-well and channel formation in CMOS process.
26 Describe in detail about second order effects in MOS transistor.
27 Briefly discuss about the CMOS process enhancement and layout design rules.
28 Write short notes on i) device model and device characterization
29 i) Design the function Y = (A + B + C).D using CMOS compound gate. Function and draw the
stick diagram and layout diagram.
ii) Develop the necessary stick diagram and layout for the design of inverter, NAND and NOR
gates.
UNIT II– COMBINATIONAL MOS LOGIC CIRCUITS
Part -A
1 What are the sources of power dissipation?
2 List the methods to reduce dynamic power dissipation.
3 Calculate logical effort and parasitic delay of n input NOR gate.
4 Distinguish between static and dynamic CMOS design.
5 Explain pass transistor logic.
6 Design an AND gate using pass transistor.
7 Explain why the interconnect increase the circuit delay.
8 Define critical path.
9 What is Elmore delay model? (Apr/May -17) (May/June -16)
10 What is transmission gate and mention advantages (Apr/May -17)
11 Justify the reasons for the speed advantage of CVSL family.
12 Implement a 2:1 MUX using pass transistor. (May/June -16)
13 Define logical effort.
14 Summarize the expression for electrical effort of logic circuits.
15 Illustrate the method for reducing energy consumption of a logic circuit.
16 Discuss the advantages of power reduction in CMOS circuits.
17 Summarize the factors that cause static and dynamic power dissipation in CMOS circuits.
(May/June -16) (Nov/Dec -16)
18 Define path logical effort.
19 Draw the pseudo nMOS logic gate.
20 If load capacitance increases, What will happen to CMOS power dissipation?
PART B
21 i)Explain the static and dynamic power dissipation in CMOS circuits with necessary
diagrams and expression. (Apr/may -17) (May/June-16)(Nov/Dec-16)
ii) Write a note on power reduction in CMOS logic gates.
22 Describe in detail about delay estimation, logical effort and transistor sizing with example.
23 List out different methods of reducing i)Static power dissipation in CMOS circuits
ii)Dynamic power dissipation
in CMOS circuits.
24 • Write the expression for minimum possible delay of multistage logic networks.
• Design and estimate the frequency of n-stage ring oscillator and construct the
ring from an odd number of inverter.
25 Derive the expressions for effective resistance and capacitance Estimation Using Elmore’s RC
delay model.
26 What is transmission gate and Explain the use of transmission Gate(Apr/may -17)
(May/June-16)
27 i) Define the principle of constant field scaling and constant voltage scaling and also write its
effect on device characterization.
ii) Construct a 4 input pseudo nMOS NAND and NOR gates.
28 Write short notes on (i)ratioed circuits (ii) Dynamic CMOS circuits (Nov/Dec-16)
29 i)Compare CMOS dynamic Domino and pseudo nMOS logic families.
ii) Evaluate the transient response of simple AND/NAND DCVSL gate.
30 Write short notes on i) Static CMOS, ii) Bubble pushing, iii) Compound gates.
31 Illustrate the operation of dyn dynamic CMOS Domino and NP Domino logic with
necessary diagrams
UNIT III – SEQUENTIAL CIRCUITS DESIGN
Part -A
1 List the advantages of differe
2 Mention the qualities of an id
3 Draw the characteristic curve
4 Distinguish between a latche
5 Classify the sequential eleme
6 What are synchronizers?
7 Summarize the operation mo
8 Determine the property of clo
9 What is Klass semi dynamic
10 List the methods of sequenci
11 Discuss the methods of imple
12 Compare SRAM and DRAM
13 Explain simple synchronizer
14 Formulate hold-time problem
path circuits uses pulsed latc
15 Justify the advantages and ap
16 Design a 1-transistor DRAM
17 Explain the concept of clock
18 Give the properties of TSPC.
19 What is the need for pipelinin
20 Draw the schematic symbol f
PART B
21 (i) Explain the sequencing m
(ii) Write short notes on Puls
22 i) Discuss in detail about the
used in sequential circuits.
(ii) Explain briefly the conce
23 List the methodology of sequ
Explain
24 I) What are the Klass semi dy
II) Illustrate the problem of m
with neat diagrams
25 i) Design a D-latch using tran
ii) Evaluate a 1-bit dynamic i
transistor.
26 i)Draw and explain the opera
latches.
ii) Write a brief note on sequ
27 i) Compare the sequencing in
with neat diagrams.
ii) Illustrate a floating gate tr
28 i)Describe in detail about me
(ii) Explain in detail about 4T
29 Give a brief note on:
(i) CMOS 4T and 6T -SRAM
(ii) Dynamic RAM cell.
30 i) Consider a flip flop built fr
clocks. Determine the set-up
terms of the latch timing para
ii)Design a 2 input CVSL AN
CVSL OR/NOR gate . (8)
UNIT IV DESIGNING OF ARITHMETIC BUILDING BLOCKS & SUBSYSTEMS
Part -A
1 Design a logic to reduce the number of generated partial products by half for Multiplication.
2 Describe Vector merging adder.
3 What is Wallace tree multiplier?
4 Give a note on barrel Shifters.
5 Create a partial product selection table using modified booth’s recoding.
6 Identify the Arithmetic circuits in the design of processors.
7 Compare constant throughput/latency and variable throughput latency in active & leakage mode.
8 List the Advantages of dual supply approach.
9 Analyze the Dynamic voltage scaling and list its advantages.
10 List the uses of Clock gating?
11 Create a schematic for Sleep transistors used on both supply and ground.
12 Compare DVS & DTS.
13 Explain Bit sliced data path organization.
14 Explain the inverting property of full adder.
15 Illustrate Clock delayed domino logic?
16 What are the Arithmetic structures derived from a full adder?
17 Examine Power minimization techniques in design and sleep mode.
18 Define Clustered voltage scaling technique.
19 Give a neat sketch on Manchester carry gates.
20 Explain the Concept of logarithmic look ahead adder.
PART B
21 (i) Describe ripple carry adder and derive the worst case delay with example.
(ii)Describe the inversion property of full adder.
22 Classify circuit design considerations of full adder and explain
i) Mirror adder
ii) Transmission gate adder
23 List the logic design considerations of binary adder and explain
• Carry skip adder
• ii) Carry save adder
24 (i) Illustrate the concepts of monolithic and logarithmic look ahead adder.
(ii)Illustrate the concepts of monolithic and logarithmic look ahead adder.
25 Define shifter and give a short note on
i) Barrel shifter
ii) Carry save multiplier
26 (i) Demonstrate how to reduce the number of generated partial products by half.
(ii) Show the method to accumulate partial products in array
form.
27 (i) Design the arithmetic logic unit (ALU) of 64 bit high end microprocessor and arithmetic
operators involved in design.
(ii) Give a short note on Logarithmic shifter.
28 (i)Summarize the methods involved in run time power management.
(ii)Compare the difference between DVS and DTS.
29 (i)Explain the implementation of a look ahead adder in dynamic logic.
(ii)Explain the advantages of Carry bypass adder compared to other adders.
30 (i) Give a note on linear carry select adder.
(ii) Discuss the data paths in digital processor architectures
UNIT V IMPLEMENTATION STRATEGIES & TESTING
Part -A
1 Define Control module of DSP processor.
2 Classify the implementation approaches for digital integrated circuits.
3 List Advantages and disadvantages of cell based design methodology.
4 Demonstrate Programmable logic array.
5 Classify the types of Macro cells.
6 Give a note on Tape out of chip.
7 Define Gate array Logic.
8 Compare semi-custom and full custom design.
9 What are the advantages of FPGA?
10 Define Fuse based FPGA.
11 Distinguish between PAL and PLA.
12 Develop an array based architecture used in Altera MAX series.
13 Design a primitive gate array cell.
14 Explain configurable logic block.
15 Summarize the functions of Programmable Interconnect Points in FPGA.
16 Identify the issues in implementing Boolean functions on array of cells.
17 Summarize the design steps of Semicustom design flow.
18 Illustrate Composition of generic digital processor.
19 Outline the steps for ASIC design flow.
20 Sketch the Overview implementation of digital ICs.
PART B
21 List and explain the components that makeup the cell based design methodology.
Give a short note on programming of PAL.
22 (i)Describe the Steps involved in semicustom design flow.
(ii)Explain the concepts of programmable interconnect.
23 (i)Describe the Blocks involved in digital processor.
(ii)Define and explain the approaches of programmable wiring.
24 (i)Illustrate the concepts of Mask programmable arrays .
25 Classify the types of FPGA routing techniques and explain.
26 Explain the interconnect architectures of
i) Altera Max series
ii) Xilinx XC40XX series
27 (i)Describe the FPGA block structure and its components.
(ii)Describe the techniques involved in Switch box programmable wiring.
28 (i)Discuss the types of FPGA routing techniques.
(i)Demonstrate the types of ASICS.
29 (i)Design an LUT-Based Logic Cell.
(ii)Discuss the Classification of prewired arrays.
30 (i) Compare two types of macrocells.
(ii) Illustrate the datapaths in digital processor architectures.
