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Digital VLSI Design Exam Questions 2025-26

The document outlines the examination details for the Digital VLSI Design course at NM Institute of Engineering & Technology for the 7th semester, including the subjects covered and the format of the exam. It consists of three parts: short answer questions, focused short answer questions, and long answer questions, with a total of 100 marks available. Students are required to answer a selection of questions from each part, covering various topics related to VLSI design and MOSFET technology.

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rajarammalik15
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16 views2 pages

Digital VLSI Design Exam Questions 2025-26

The document outlines the examination details for the Digital VLSI Design course at NM Institute of Engineering & Technology for the 7th semester, including the subjects covered and the format of the exam. It consists of three parts: short answer questions, focused short answer questions, and long answer questions, with a total of 100 marks available. Students are required to answer a selection of questions from each part, covering various topics related to VLSI design and MOSFET technology.

Uploaded by

rajarammalik15
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Total Number of Pages:02 Course: [Link].

Sub_Code:REC5D006

NM INSTITUTE OF ENGINEERING & TECHNOLOGY


7th SEMESTER REGULAR/BACK EXAMINATION 2025-2026

Subject-DIGITAL VLSI DESIGN

BRANCH(S): CSE, EEE, EE, ECE & MECH

TIME: 3Hours Max Marks: 100


[Link]: R399

Q1 Answer the following questions:

a) Differentiate between Regularity and Modularity?

b) Draw a two input NOR gate using dynamic logic?

c) What is the limitation of a nMOS transistor when it is used as a pass transistor?

d) Explain channel width and channel length?

e) Define average propagation delay for a CMOS inverter?

f) What is the most important advantage of CMOS transmission gate compared to pass transistor logic?

g) CAM is mostly used in which memory circuits?

h) Compare and contrast volatile and non-volatile memory?

i) Design EX-NOR gate using minimum number of NAND gate?

j) Explain about the principles of Built in Self-Test?

Part-II

Q2 Only Focused-Short Answer Type Questions- (Answer Any Eight out of Twelve) (6 x 8)

a) What do you understand by MOSFET scaling? Describe some of the short channel effects that appear while performing
scaling of MOS devices.

b) Draw and explain the energy band diagrams for a pMOS and nMOS structures operating under inversion and
accumulation condition.

c) Explain the difference between semicustom and full custom VLSI design style.

d) With neat sketches explain oxidation process in IC fabrication.

e) Explain VLSI design flow using Y-chart.

f) Why cascading is not preferred in dynamic CMOS logic?

g) Create a circuit which will explain the Ad Hoc Testable Design Techniques.
h) Draw and explain the Scan-Based Techniques for testing of sequential circuits.

i) Design a shift register with the dynamic latch operated by a two-phase clock.

j) What is a multiplexer? Realize a 4X1 MUX using transmission logic.

k) Compare NORA and NP(ZIPPER) CMOS logic structures.

l) Draw the schematic of NAND flash memory cell.

Part-III

Only Long Answer Type Questions (Answer Any Two out of Four)

Q3 Describe about the different design methodologies used in VLSI design and thus explain design flow of VLSI circuits. (16)

Q4 Explain the structure and operation of the MOSFET under external biasing. Why drain current increases even the
transistor is in saturation? (16)

Q5 Describe the Pre-charge& Evaluate logic with regards to Dynamic CMOS logic circuits. What do we do for rectifying the
limitation of Dynamic logic circuits? (16)

Q6 Write short answer on any TWO: (8 x 2)

a) CMOS p-well fabrication process.


b) Edge Triggered Flip flop.
c) Flash memory vs SRAM.
d) Buit- in Self-Test(BIST).

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