EEE 465 – January 2022

Analog Integrated Circuits and Design

Lecture 1: Introduction

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Digital versus Analog

 Abstraction in digital is Boolean logic (1’s and 0’s)
Works because of noise margin
 At a higer level, it’s gate and registers (RTL)

 Digital Layuot is often automated

 Abstraction in analog is the device model

 (BSIM is a few thousand lines long)
 At a higer level, it’s the (opamps), (filters), (comparator)
 Abstraction depends on the problem you are solving

 Analog Layuot is usually hand crafted

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 Analog versus RF
 RF = “Analog with inductors”

 RF signal is usually narrowband (i.e. sinusoidal)

 Tuned circuit techniques used for signal processing
 RF Impedance levels are relatively low
 Can’t make antenna Impedance too high.

 Analog impedance are high (low) for voltage (current) gain

 Voltage/current gain versus power gain
 Mixed signal analog is often discrete time (sampled)

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Analog and Mixed-Signal Circuits

Physical
World
Transducer

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 Example RF Transceiver

iPhone 13 line has Qualcomm's X60 modem

mmWave 5G is 24 GHz to 40 GHz
Snapdragon X60 5G Modem-RF System is based on the 5 nanometer
process node

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Example RF Transceiver
iPhone 16 line has Qualcomm's X75 modem
mmWave 5G is 24 GHz to 40 GHz
Snapdragon X75 5G Modem-RF System is based on the 4 nanometer
process node. This 6th generation modem-to-antenna 5G solution is
the world’s first modem-RF system with an integrated AI tensor
accelerator - Qualcomm® 5G AI Processor Gen 2

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 Why CMOS?

Snapdragon X75 5G Modem-RF System is based on the TSMC 4

nanometer process node.

Like digital, CMOS is now the technology of choice for Analog also.

Analog mixed signal circuits are all based on CMOS

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Design Methodology

Top-down and Bottom-up Design

Abstraction level in circuit design (a) device level (b) Circuit level (c)
architecture level (d) System level
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 What You will Be Doing as an Analog
Design Engineer ?

 You will be tasked with building many

different variants of the same function/block

 You will be tasked with building many

different blocks

 You will be tasked with putting many different

blocks together to realize a (sub-) system

 How do you do this efficiently without (re-)

introducing any known errors?

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MOSFETs
The MOSFET (metal-oxide-semiconductor field-effect transistor), also
known as the MOS transistor, was invented by Mohamed Atalla and
Dawon Kahng at Bell Labs in 1959.

Dawon Kahng Mohammed Atalla

Enhancement mode MOSFET : Normally OFF. A gate voltage must be

applied to form a conductive channel i.e. to turn on the device. At zero gate
bias the device is OFF.
Depletion mode MOSFET : Normally ON. The Channel conducts with zero
gate bias and a gate voltage must be applied to turn the transistor off.
N-Channel MOSFET : current flows due to the movement of electron
P-Channel MOSFET : Current flows due to the movement of hole
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 Device Structure and Physical Operation
The MOSFET is a symmetrical device; thus its source and drain can be
interchanged with no change in device characteristics

Compared to Bipolar Junction Transistors (BJT), MOSTFETs;

- Can be made quite small (require small area).
- Can be manufactured with simple fabrication process.
- Can be operated with little power.
- Can be integrated densely (>200 millions on a single IC chip, Very-large-scale-integrated circuit
- Digital and analog functions can be implemented almost exclusively ( i.e., with very few or no resistors).
- Digital and analog functions can be implemented on the same IC chip (mixed-signal design).
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Operation with Zero Gate Voltage

2-~50 nm

0.1~3 μm

MOS

With zero voltage applied to the gate, two back-to-back diodes exist in
series between drain and source. One diode is formed by the pn junction
between the n+ drain region and the p type substrate, and the other diode
is formed by the pn junction between the p-type substrate and the n+
source region.
The back-to-back diodes prevent current conduction form drain to source
when a voltage VDS is applied. In fact, the path between drain and source
has a very high resistance (of the order of 1012 ohms)

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 Creating a Channel for Current Flow
The enhancement-type NMOS transistor with a
positive voltage applied to the gate. An n channel
is induced at the top of the substrate beneath the
gate.
The voltage across the parallel plate capacitor, i.e.
the voltage across the oxide, must exceed Vt for a
channel to form.
The excess VGS of over Vt is termed the effective
voltage or overdrive voltage and determine the
charge in the channel

- An n-channel is formed in a p-type substrate – inversion layer.

- If a voltage is applied between drain and source, current flows through this n-channel. (NMOS)
- Threshold voltage Vt : a voltage of υGS at which a sufficient number of mobile electrons
accumulate in the channel region to form a conducting channel.(+0.5 ~ 1 V)
- The gate and the channel form a capacitor.
- The positive charges on the gate and the electrons in the channel develop an electric field.

- This electric field controls the current flow in the channel.

Field-Effect Transistor (FET) !
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Applying a Small VDS (< 50 mV)

The device acts as a resistance whose value is

determined by VGS. Specifically, the channel VGS – Vt : excess gate voltage or
conductance is proportional to VGS – Vt and over drive Voltage
thus iD is proportional to (VGS – Vt) VDS.

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 Operation as VDS increases

When υDS = small or 0 V

The drain current iD versus the drain-to-source voltage vDS for

an enhancement-type NMOS transistor operated with vGS > Vt.
- As VDS is increased VGD =VGS – VDS decreases and channel takes the tapered form, and
resistance between the drain and gate increases.
- At VGD =VGS – VDS = Vt or VDS = VGS - Vt , the channel depth at the drain end is
almost zero! – The channel is pinched off.
- Increasing υDS beyond this value has, theoretically, no effect on the channel shape
and channel current.-Saturation!
VDSsat  VGS  Vt
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Derivation of the IDS-VDS Relationship : NMOS

Q  CVov For the infinitesimal MOS Capacitor

 oxWdx
dq  c (Vgx  Vt )  (Vgd  Vdx  Vt )
tox
 oxWdx
 (V gs  Vds  Vt  Vdx )
tox
 oxW x
 (Vgs  Vt  Vds  V )dx
tox L ds
Total Charge in the Channel , Q
L
 oxW x
Q (Vgs  Vt  Vds  V )dx
0
tox L ds
1
 C oxWL(Vgs  Vt  Vds )
2
1
I DS 
Q
; t
L
; Q CoxWL(Vgs  Vt  2 Vds ) W  1 2
t Ve I DS     nC ox  (Vgs  Vt )Vds  2 Vds 
t L2 L  
nVds

At the beginning of saturation region, Vds= Vgs-Vt

1 W
L2 I DS  C  (V  Vt )2 
t
L

L
 2 n ox L  gs
Ve  n E nVds
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 Current-Voltage Characteristics
Circuit Symbol of n-channel enhancement MOS

Amplifier - Saturation region

Normal direction of current
The iD-vDS Characteristics Switch – Cutoff and triode region
• For the operation in the triode region,

VGS  Vt (Induced channel)

and keep VDS small enough so that the channel

remains continuous.
VGD >Vt (Continuous channel) (4.9)

At VGD =VGS – VDS = Vt or VDS = VGS - Vt , the

channel depth at the drain end is almost zero! –
The channel is pinched off.
VGD  VDS  Vt , VDS  VGS  Vt (Continuous channel)

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Current-Voltage Characteristics
Drain-Source Resistance
W  1 2 W  1 2
I DS  nCox (Vgs  Vt )Vds  2 Vds  I DS  nC ox  (Vgs  Vt )Vds  2 Vds 
L   L  
1
VDS  W 
rDS    kn (VGS  Vt )  where K 'n  n C ox
iD VDS small  L 
 W   VOV  VGS  Vt gate-to-source overdrive voltage
rDS  1  k n   VOV 
  L  The operation of the MOS transistor as a linear resistance
whose value is controlled by gate voltage
1 W
VDS  VGS  Vt (Boundary) iD  kn (GS  Vt )2 Saturation current
2 L

The saturated MOSFET behaves as an ideal current source.

Saturation

Large-signal equivalent-circuit
model of an n-channel MOSFET
operating in the saturation region.
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 At the boundary between triode and saturation region,
 DS   GS  Vt (Boundary) (4.19)

(4.11)
1 W
i D  kn (GS  Vt )2 (4.20) Saturation current
2 L
1 W 2
iD  k  (4.21) Saturation current
2 n L DS

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Finite Output Resistance in Saturation

1 W
iD  kn (GS  Vt )2 Saturation current
2 L

Tthe saturation current is independent of the drain voltage,

but in practice, increasing VDS beyond VDSsat does affect the
channel length.

The phenomenon that the channel length is

reduced form L to L-ΔL is known as channel-
length modulation.

1 W
iD  kn (GS  Vt )2
2 L  L
Increasing vDS beyond vDSsat causes the channel pinch- 1 W 1
 kn (  Vt )2
2 L 1  ( L / L) GS
off point to move slightly away from the drain, thus
1 W  L 
reducing the effective channel length (by ΔL). = kn  1  L  (GS  Vt )
2

2 L  

1 W   
Assuming L    DS , iD  k 1   DS  ( GS  Vt )2 let   , process-technology parameter (V -1 )
2 n L  L  L

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 Finite Output Resistance in Saturation

1 W
iD  kn ( GS  Vt )2  1   DS 
2 L

With extrapolation, VA  1 /  , Early voltage

V A  V A L : V   5~50 [V/ m], entirely techology parameter

This equation gives ro as 1/, however

channel length modulation, which λ models,
is only part of the story for determining
MOSFET output resistance (ro). Other effects
such as drain-induced barrier lowering and
substrate current induced body effect (SCBE)
may also be important depending on the bias
point of the device.
1
r 
0
I D

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MOSFET Vt Measurement

Vt can be determined by plotting ID vs

VGS, using a low value of VDS.
W 1 
I DS  nC ox (V  Vt )  Vds  Vds
L  gs 2 

Method A : Vt is measured by
extrapoloting the linear portion of
the Ids vs Vgs cureve .

Method B : The Vgs at which

Ids=0.1uA  W/L

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 Regions of Operation of the Enhancement NMOS

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The Role of Substrate – The Body Effect

- Usually, the source terminal is connected to the substrate (or body) terminal.
- In integrated circuit, many MOS transistors are fabricated on a single substrate.
- In order to maintain the cutoff condition for all the substrate-to-channel junctions, the substrate is
usually connected to the most negative power supply in an NMOS circuit (the positive in a PMOS
circuit). - The reverse bias will widen the depletion region.
- The channel depth is reduced.
- To return the channel to its former states, υGS has to be
increased.

Vt  Vt 0   [ 2 f  VSB  2 f ]

2 f ( physical  parameter )  0.6 V

2qN A s
 ( body  effect  parameter ) 
C ox
The body effect can cause considerable degradation in
circuit performance

Temperature Effect Breakdown and Input Protection

- The overall observed effect of a temperature - Weak avalanche : υDS (20~150 V) breakdown between drain
increase is a decrease in drain current. and substrate.
- This very interesting result is put to use in applying - Punch-through : υDS (~20 V) breakdown between drain and
the MOSFET in power circuit (Chap. 11). source for short-channel devices.
- υGS (>30 V) breakdown between gate and source.

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 The p-Channel MOSFET and the CMOS Technology

- The p-Channel MOSFET is fabricated on an n-type substrate with p+ regions for the drain and
source. The p-Channel MOSFET has holes as charge carrier
- VGS, VDS, and Vt are negative. The current flows from the source to the drain.
Complementary MOS, or CMOS. CMOS technology is most widely used of all IC
technologies in analog and digital circuit design.

Figure Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed
in a separate n-type region, known as an n well. Another arrangement is also possible in
which an n-type body is used and the n device is formed in a p well. Not shown are the
connections made to the p-type body and to the n well; the latter functions as the body
terminal for the p-channel device.
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