CPU–MAIN MEMORY COMMUNICATION
From the system standpoint, the main memory unit can be considered as a black box
whose internal structure is not visible to the processor. The communication between the
CPU and the main memory takes place through two important registers known as the
Memory Address Register (MAR) and the Memory Data Register (MDR). The MAR is
used to store the address of the memory location that is to be accessed, while the MDR
is used to hold the data that is either read from or written into the memory.
The processor communicates with the memory through three types of buses, namely the
address bus, data bus, and control bus. The address bus is used to carry the address from
the MAR to the memory and it consists of k address lines, which allow the memory to
have up to 2 addressable locations. The data bus consists of n data lines and is used to
transfer data between the CPU and the memory, where each memory location stores n
bits of data, known as the word length. The control bus carries control signals such as
Read/Write and Memory Function Complete (MFC), which coordinate the memory
operations.
During a read operation, the processor places the address of the required memory
location into the MAR and sets the Read/Write control signal to read mode. The memory
responds by placing the data from the addressed location onto the data bus and then
asserts the Memory Function Complete signal to indicate that the operation has been
completed. Upon receiving this signal, the processor loads the data present on the data
bus into the MDR for further processing.
During a write operation, the processor first loads the address of the target memory
location into the MAR and places the data to be written into the MDR. The Read/Write
control signal is then set to write mode, and the memory stores the data from the MDR
into the specified memory location. Thus, data transfer between the CPU and main
memory is efficiently managed using MAR, MDR, and the system buses.
Memory Access Time and Memory Cycle Time
Memory access time is defined as the time interval between the initiation of a memory
operation and the completion of that operation. For example, it is the time taken from
issuing a read command until the Memory Function Complete signal is received.
Memory cycle time, on the other hand, is the minimum time required between the
initiation of two successive memory operations, and it is usually slightly longer than the
memory access time.
DYNAMIC RAM (DRAM)
Dynamic RAM is used to reduce the cost of memory when compared to Static RAM.
Static RAM is fast but expensive because it uses many transistors in each memory cell.
Dynamic RAM uses a simpler memory cell, which consists of one transistor and one
capacitor, making it cheaper and suitable for large-capacity main memory.
In a DRAM cell, the information is stored as an electrical charge on a capacitor. If the
capacitor is charged, the cell represents logic value 1, and if the capacitor is discharged,
it represents logic value 0. However, the capacitor cannot hold its charge for a long time
because of leakage, so the stored data slowly disappears. For this reason, DRAM is
called dynamic memory, and its contents must be periodically refreshed to retain the
data.
The figure shows a single-transistor DRAM cell, where the transistor T acts as a switch
controlled by the word line, and the capacitor C stores the data bit. The bit line is used
to transfer data during read and write operations.
Read Operation in DRAM
During a read operation, the word line is activated, which turns on the transistor. The
charge stored on the capacitor is connected to the bit line. A sense amplifier connected
to the bit line detects the voltage level. If the charge on the capacitor is above the
threshold value, the bit line is interpreted as logic 1, and if the charge is below the
threshold value, it is interpreted as logic 0. Since reading discharges the capacitor, the
data must be written back after reading.
Write Operation in DRAM
During a write operation, the word line is activated, turning on the transistor, and the
required voltage is applied to the bit line. This voltage charges or discharges the
capacitor to store logic 1 or logic 0. After the transistor is turned off, the capacitor
begins to slowly discharge due to leakage, which makes periodic refreshing necessary
SEMICONDUCTOR RAM MEMORIES – INTERNAL ORGANIZATION OF
MEMORY CHIPS
Semiconductor RAM memories are organized as an array of memory cells, where each
cell stores one bit of information. The memory cells are arranged in rows and columns,
and each row of cells forms a memory word. All the cells in a row are connected to a
common word line, which is selected by an address decoder.
The cells in each column are connected to sense/write circuits through bit lines. These
sense/write circuits are connected to the data input and output lines of the memory chip.
During a read operation, the sense/write circuits read the data stored in the selected
memory cells and send it to the output lines. During a write operation, the sense/write
circuits receive input data and store it in the selected memory cells.
A 16 × 8 memory organization means the chip contains 16 words with 8 bits in each
word, giving a total storage capacity of 128 bits. The data lines are bi-directional and
are connected to the system data bus. The Read/Write (R/W’) control line is used to
specify the type of operation, and the Chip Select (CS) line is used to enable the memory
chip. Including address lines, data lines, and control lines, the memory chip can be
implemented as a 16-pin integrated circuit.
ORGANIZATION OF A 1K × 1 MEMORY CHIP
In large memory systems, a 1K × 1 memory contains 1024 memory cells, which are
arranged in the form of a 32 × 32 array. To access these 1024 cells, a 10-bit address is
required, since 2 = 1024. This 10-bit address is divided into two groups of 5 bits
each, where one group is used as the row address and the other as the column address.
The 5-bit row address is applied to a 5-bit decoder, which selects one out of 32 rows
of the memory cell array. Each selected row represents a word, and each word contains
32 memory cells. When a row is selected, all 32 memory cells in that row become
active at the same time.
The 5-bit column address is applied to a 32-to-1 output multiplexer and input
demultiplexer. The multiplexer selects one bit from the 32 active cells during a read
operation, while the demultiplexer selects one cell position to store data during a write
operation.
During a read operation, the control signal R/W’ is set to 1. The row decoder selects
a word, and the data from the selected row is sent to the multiplexer. Based on the
column address, the multiplexer selects one bit and sends it to the data output line.
During a write operation, the control signal R/W’ is set to 0. A single data bit is given
at the data input line, and the demultiplexer uses the column address to decide which
bit position to write. The row address decides which word the data is written into.
The Chip Select (CS) signal is used to enable the memory chip, and the sense/write
circuitry is responsible for reading data from or writing data into the memory cells.
STATIC RAM (SRAM)
Static memory is a type of memory that can retain its stored data as long as power is
supplied, and therefore it is called volatile memory. A Static RAM (SRAM) cell is
implemented using electronic circuits, not capacitors, which allows it to store data
without the need for refreshing.
An SRAM cell is formed using two inverters that are cross-connected, which together
act as a latch. This latch has two stable states and is capable of storing one bit of
information, either 0 or 1. The latch is connected to two bit lines (b and b’) through two
transistors T1 and T2, which act as switches. These transistors are controlled by a signal
called the word line.
When the word line is low (ground level), the transistors T1 and T2 are turned off, and
the latch is isolated from the bit lines. In this condition, the SRAM cell retains its stored
value, because the cross-connected inverters continuously reinforce each other’s output.
For example, if the SRAM cell is storing logic 1, the voltage at point X is high and the
voltage at point Y is low. This state remains unchanged as long as power is applied and
the word line remains inactive.
Read Operation in SRAM
During a read operation, the word line is activated, which turns on transistors T1 and
T2. This connects the latch to the bit lines. The values stored at points X and Y are
transferred to bit lines b and b’. The sense/write circuit connected to the bit lines detects
these values and sends the stored data to the processor.
Write Operation in SRAM
During a write operation, the required data value is applied to bit line b, and its
complement is applied to bit line b’. The word line is then activated, which turns on
transistors T1 and T2. This forces the latch to change its state according to the input
values on the bit lines, thereby storing the new data in the SRAM cell.
Virtual Memory.
Virtual memory is a memory management technique that allows a computer to execute
programs larger than the physical main memory. The processor can generate a large
address space, such as 4 GB in a 32-bit system, even though the actual RAM may be
much smaller. When a program does not completely fit into main memory, the unused
parts are stored on secondary storage like disks. Only the required parts of the program
are loaded into main memory for execution. If the memory becomes full, one segment
is replaced by another segment when needed.
Virtual-memory techniques allow a computer system to automatically move program
instructions and data between secondary storage and main memory whenever they are
needed for execution. This enables programs to run even when the physical main
memory is smaller than the program size.
The processor generates virtual or logical addresses to access data and instructions.
These virtual addresses cannot directly access the main memory and must be translated
into physical addresses, which represent actual memory locations. This translation is
carried out by a special hardware unit called the Memory Management Unit (MMU).
If the required data is already present in the main memory, the MMU allows it to be
accessed immediately. If the data is not present, the MMU signals the operating system
to fetch the required data from secondary storage and load it into main memory. After
this, execution continues normally.
Paging
Paging is a technique in which both logical memory and physical memory are divided
into fixed-size blocks. The logical memory is divided into blocks called pages, and the
physical memory is divided into blocks of the same size called frames. The size of a
page and the size of a frame are always equal so that any page can be placed into any
frame.
A page is the basic unit of information that is transferred between secondary storage
and main memory. Typical page sizes range from 2 KB to 16 KB. Pages should not be
too small because disk access is slow, and pages should not be too large because unused
data may waste memory space. The page table stores the mapping between page
numbers and frame numbers.
Virtual Address Format in Paging
Every address generated by the CPU is divided into two parts:
a page number
a page offset
The page number identifies which page of the program is required, and the page offset
identifies the exact location inside that page. The offset remains the same during address
translation.
Each process has its own page table. The starting address of the page table is stored in
a special register called the Page Table Base Register (PTBR).
When the CPU generates a virtual address, the page number is used as an index into the
page table. The page table entry contains the frame number where that page is stored.
In this figure, the processor generates a logical address 0011. This logical address is
divided into two parts. The first two bits 00 represent the page number (p), and the last
two bits 11 represent the page offset (d).
The page number 00 is sent to the page table. The page table is used to find where this
page is stored in physical memory. From the page table shown in the figure, page 00 is
mapped to frame number 5.
Once the frame number is obtained, the physical address is formed by combining the
frame number 5 with the same offset 11. The offset does not change because it
represents the position inside the page.
Thus, the logical address (00, 11) is translated into the physical address (5, 11), and
the required data is accessed from physical memory.
The page number is used to access the page table, whose base address is stored in the
Page Table Base Register. Each page table entry contains control bits and the physical
page frame number corresponding to the page. If the valid bit indicates that the page is
present in main memory, the frame number is obtained and combined with the same
offset to form the physical address. This physical address is then used to access the
required data in main memory. If the page is not present, a page fault occurs and the
operating system loads the page from secondary storage.
To solve the slow access problem, the system uses a Translation Lookaside Buffer
(TLB).
The TLB is a small, fast memory that stores recently used page table entries.
Instead of going to the page table every time, the system first checks the TLB.
If the page number is found in TLB → TLB hit → fast access
If not found → TLB miss → page table is accessed.
A page fault occurs when the CPU requests a page that is not present in main
memory.
This means:
Valid bit = 0
Page is on disk, not in RAM
When a page fault occurs:
1. MMU detects it
2. CPU execution is stopped
3. Operating system is called
4. Required page is brought from disk into RAM
5. Page table is updated
6. Execution resumes
Segmentation
Segmentation is an address translation technique in which the logical address space of
a program is divided into variable-sized blocks called segments. Segmentation is
similar to paging, but the main difference is that pages are of fixed size, whereas
segments are of variable size. In segmentation, all information related to each segment
is stored in a special table called the segment table.
The segment table stores two important pieces of information for each segment: base
and limit.
The base specifies the starting address of the segment in main memory, and the limit
specifies the length or size of the segment.
In segmentation, the logical address generated by the CPU consists of two parts: a
segment number and an offset. The segment number identifies which segment is being
accessed, and the offset specifies the location within that segment. The segment
number is used as an index into a segment table, whose base address is stored in the
Segment Table Base Register (STBR). The segment table is also stored in the main
memory itself.
During address translation, the offset is first compared with the limit value. If the
offset is less than the limit, the address is valid. In this case, the physical address is
obtained by adding the base value and the offset, and the data is accessed from main
memory. If the offset is greater than or equal to the limit, the address is invalid, and an
addressing error (trap) occurs.
