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MST 2025

This document outlines the Mid Semester Examination for the Microprocessor Based Systems Design course at Thapar Institute of Engineering & Technology. It includes details such as the date, time, and marks, along with a series of questions related to 8085 microprocessor programming, assembly language, and addressing modes. All questions are compulsory, and students are instructed to assume any missing data while answering them.
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0% found this document useful (0 votes)
33 views2 pages

MST 2025

This document outlines the Mid Semester Examination for the Microprocessor Based Systems Design course at Thapar Institute of Engineering & Technology. It includes details such as the date, time, and marks, along with a series of questions related to 8085 microprocessor programming, assembly language, and addressing modes. All questions are compulsory, and students are instructed to assume any missing data while answering them.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Roll Number:

Thapar Institute of Engineering & Technology, Patiala


Department of Computer Science & Engineering
Mid Semester Examination
B. E. (COE): 3" year (6th Semester) Course Code: UCS617
Course Name: Microprocessor Based Systems Design
Date: March 13, 2025 Time: 3:00 PM — 5:00 PM
Time: 2 Hours, M. Marks: 30 Faculty: MJU/AAS/SMV/SOR/JPICSUC
Note: All questions are compulsory and carry equal marks. Attempt questions in sequence and assume any missing data.

Q. No. Questions MM CO Level


Ql Assume the following 8085 microprocessors assembly language program is loaded (1+ 1+ CO2 L2
in the 000011 address of memory. 1+ 2 = 5)

1. MVI A, 01H Based on the given information, answer the following


2 . CPI 01H questions.
3. JZ 000FH
4 . CPI 02H a) What is the size of the program in bytes?
5. JZ 0013H b) What would be the value of the HL pair after the
execution of the program?
6 . JMP 0021H
7 . LXI H, 0017H c) Count the number of T-States required to execute
8 . PCHL the program.
9. LXI H, 0013H d) If the processor is connected to a 4MHz crystal
10 . PCHL oscillator, then how long will it take to complete
11 . MVI B, 55H the execution?
12. JMP 0021H
13. MVI C, 0)(AA
14. JMP 0021H
15. HLT

Q2 a) An 8085 system uses the SIM instruction to enable interrupts and transmit serial (2+2+1 CO2 L4
data simultaneously. If the accumulator value is 6DH, what is the state of the = 5)
interrupts and the serial output?
b) After executing the RIM instruction, the accumulator value is E91-1. Interpret this
value and explain its significance in terms of interrupt status and serial input.
c) Write an 8085 assembly program to disable RST5.5 and RST6.5 and enable
RST7.5 interrupts, reset the RST 7.5 flip-flop, and transmit a high signal on the
SOD pin using the SIM instruction.

Q3 Design the timing diagram and also write the values at each machine cycle as below (2 + 3 = CO2 LI
mentioned table for the following instruction: 5)
A432 H: RST4 (SP: E8A0 H, and Opcode for RST4: E7H)
Machine T- Ao- Do- A8- ALE 10/Si So, RI) WR PC SP
cycle states A7 D7 A15 Si

(2 + 3 = COl L3
Q4 a) Write the four logidal differences between the Bus Interface Unit (BIU) and the
Execution Unit (EU) of 8086 microprocessor. 5)
b) Explain the following pins of 8086 microprocessor:
(i) DT/11 (ii) DEN (iii) RQ/GTo and RQ/GT1

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Q5 Suppose the segment registers, CS, SS, DS, and ES of 8086 microprocessor contain (1 * 5 = COI L4
segment addresses 2460H. 3460H, 4460H, and 5460H, respectively and the offset 5)
register contains the offset address BX = 0843H, SI = 1982H. DI = 79$AH. SP =
E729H, and BP = 004AH. Write the addressing mode and calculate the offset
address and physical memory address for each instruction given below from where
the destination registers will fetch the data.
a) MOV AL, [BP+DI]
b) MOV CH, [BX+DI+1910H]
c) MOV DX, [BX]
d) MOV CX, [SP+SI-7432H]
e) MOV AX, [DI+3489H]

Q6 Identify the register contents and flag status in 8085 as the following instructions are (I * 5 = CO2 L4
executed in sequence starting from the address 9234H (All the registers are clear at 5)
the beginning):
Instruction A E Sign Parity Carry
XRI 9EH ,
..,
MVI E, 97H
RAL
SUB E
CMA ,
ADD E
DAA
HLT

********

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